Hui; Angela

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hui; Angela.The latest application filed is for "split-gate semiconductor device with l-shaped gate".

Company Profile

0.48.25

Hui; Angela - San Jose CA
Hui; Angela - Milpitas CA
HUI; Angela - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Split-gate semiconductor device with L-shaped gate Grant 10,020,316 - Bell , et al. July 10, 2	2018-07-10
Split-gate Semiconductor Device With L-shaped Gate App 20170162586 - Bell; Scott ; et al.	2017-06-08
HTO offset for long leffective, better device performance Grant 9,455,352 - Cheng , et al. September 27, 2	2016-09-27
Split-gate Semiconductor Device With L-shaped Gate App 20160035576 - BELL; Scott ; et al.	2016-02-04
Oro and orpro with bit line trench to suppress transport program disturb Grant 9,245,895 - Cheng , et al. January 26, 2	2016-01-26
Hto Offset For Long Leffective, Better Device Performance App 20140167138 - Cheng; Ning ; et al.	2014-06-19
Etch stop layer for memory cell reliability improvement Grant 8,658,496 - Kinoshita , et al. February 25, 2	2014-02-25
HTO offset for long Leffective, better device performance Grant 8,653,581 - Cheng , et al. February 18, 2	2014-02-18
Self-aligned Si Rich Nitride Charge Trap Layer Isolation For Charge Trap Flash Memory App 20140001537 - FANG; Shenqing ; et al.	2014-01-02
Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory Grant 8,551,858 - Fang , et al. October 8, 2	2013-10-08
Selective silicide formation using resist etch back Grant 8,445,372 - Min , et al. May 21, 2	2013-05-21
Etch Stop Layer For Memory Cell Reliability Improvement App 20130078795 - KINOSHITA; Hiroyuki ; et al.	2013-03-28
Methods for forming a memory cell having a top oxide spacer Grant 8,384,146 - Fang , et al. February 26, 2	2013-02-26
Etch stop layer for memory cell reliability improvement Grant 8,319,266 - Kinoshita , et al. November 27, 2	2012-11-27
Methods For Forming A Memory Cell Having A Top Oxide Spacer App 20120181601 - FANG; Shenqing ; et al.	2012-07-19
Methods for forming a memory cell having a top oxide spacer Grant 8,202,779 - Fang , et al. June 19, 2	2012-06-19
Flash memory device and method of forming the same with improved gate breakdown and endurance Grant 8,093,646 - Hui , et al. January 10, 2	2012-01-10
Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb App 20110278660 - Cheng; Ning ; et al.	2011-11-17
Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications Grant 8,035,153 - Fang , et al. October 11, 2	2011-10-11
Methods For Forming A Memory Cell Having A Top Oxide Spacer App 20110233647 - FANG; Shenqing ; et al.	2011-09-29
Ultraviolet radiation blocking interlayer dielectric Grant 8,022,468 - Ngo , et al. September 20, 2	2011-09-20
ORO and ORPRO with bit line trench to suppress transport program disturb Grant 8,012,830 - Cheng , et al. September 6, 2	2011-09-06
SI trench between bitline HDP for BVDSS improvement Grant 7,951,675 - Xue , et al. May 31, 2	2011-05-31
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics Grant 7,906,807 - Cheng , et al. March 15, 2	2011-03-15
Use Of A Polymer Spacer And Si Trench In A Bitline Junction Of A Flash Memory Cell To Improve Tpd Characteristics App 20100264480 - Cheng; Ning ; et al.	2010-10-21
Self-aligned Patterning Method By Using Non-conformal Film And Etch For Flash Memory And Other Semiconductor Applications App 20100230743 - Fang; Shenqing ; et al.	2010-09-16
Dual storage node memory devices and methods for fabricating the same Grant 7,785,965 - Kim , et al. August 31, 2	2010-08-31
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics Grant 7,776,688 - Cheng , et al. August 17, 2	2010-08-17
Hto Offset For Long Leffective, Better Device Performance App 20100155817 - Cheng; Ning ; et al.	2010-06-24
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications Grant 7,732,276 - Fang , et al. June 8, 2	2010-06-08
Self-aligned Si Rich Nitride Charge Trap Layer Isolation For Charge Trap Flash Memory App 20100133646 - FANG; Shenqing ; et al.	2010-06-03
Selective Silicide Formation Using Resist Etch Back App 20100099249 - Min; Kyunghoon ; et al.	2010-04-22
Methods for fabricating flash memory devices Grant 7,696,038 - Cheng , et al. April 13, 2	2010-04-13
Selective silicide formation using resist etchback Grant 7,691,751 - Min , et al. April 6, 2	2010-04-06
Selective contact formation using masking and resist patterning techniques Grant 7,622,389 - Min , et al. November 24, 2	2009-11-24
Si Trench Between Bitline Hdp For Bvdss Improvement App 20090152669 - Xue; Lei ; et al.	2009-06-18
Selective Silicide Formation Using Resist Etchback App 20090111265 - Min; Kyunghoon ; et al.	2009-04-30
Use Of A Polymer Spacer And Si Trench In A Bitline Junction Of A Flash Memory Cell To Improve Tpd Characteristics App 20090042378 - Cheng; Ning ; et al.	2009-02-12
Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb App 20090039405 - Cheng; Ning ; et al.	2009-02-12
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications App 20080265301 - Fang; Shenqing ; et al.	2008-10-30
Method For Manufacturing A Memory Device App 20080096357 - Suh; Youseok ; et al.	2008-04-24
Dual Storage Node Memory Devices And Methods For Fabricating The Same App 20080064165 - Kim; Unsoon ; et al.	2008-03-13
Flash memory device and method of forming the same with improved gate breakdown and endurance Grant 7,067,388 - Hui , et al. June 27, 2	2006-06-27
Undoped oxide liner/BPSG for improved data retention Grant 7,023,046 - Ngo , et al. April 4, 2	2006-04-04
Method and system for forming dual gate structures in a nonvolatile memory using a protective layer Grant 6,974,995 - Hui , et al. December 13, 2	2005-12-13
Method for fabricating a memory device having reverse LDD Grant 6,936,515 - Ogawa , et al. August 30, 2	2005-08-30
Method of forming planarized shallow trench isolation App 20050158963 - Chan, Darin ; et al.	2005-07-21
Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control Grant 6,894,342 - Hui , et al. May 17, 2	2005-05-17
Undoped oxide liner/BPSG for improved data retention App 20050006693 - Ngo, Minh Van ; et al.	2005-01-13
Structure and method for preventing process-induced UV radiation damage in a memory cell Grant 6,833,581 - Hui , et al. December 21, 2	2004-12-21
Innovative method of hard mask removal Grant 6,809,033 - Hui , et al. October 26, 2	2004-10-26
Method and system for providing a contact hole in a semiconductor device Grant 6,764,929 - Hui , et al. July 20, 2	2004-07-20
Structure and method for preventing UV radiation damage and increasing data retention in memory cells Grant 6,765,254 - Hui , et al. July 20, 2	2004-07-20
Dual bit memory device with isolated polysilicon floating gates Grant 6,713,809 - Ogura , et al. March 30, 2	2004-03-30
Laser thermal annealing of silicon nitride for increased density and etch selectivity Grant 6,706,576 - Ngo , et al. March 16, 2	2004-03-16
RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist Grant 6,642,148 - Ghandehari , et al. November 4, 2	2003-11-04
Method for minimizing nitride residue on a silicon wafer Grant 6,605,517 - Bhakta , et al. August 12, 2	2003-08-12
Methods for improving carrier mobility of PMOS and NMOS devices Grant 6,573,172 - En , et al. June 3, 2	2003-06-03
Process for making a dual bit memory device with isolated polysilicon floating gates Grant 6,573,140 - Ogura , et al. June 3, 2	2003-06-03
Hard mask removal process App 20030087529 - Wu, Yider ; et al.	2003-05-08
Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device Grant 6,509,232 - Kim , et al. January 21, 2	2003-01-21
Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory Grant 6,465,303 - Ramsbey , et al. October 15, 2	2002-10-15
Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers Grant 6,461,951 - Besser , et al. October 8, 2	2002-10-08
Process for fabricating an integrated circuit with a self-aligned contact Grant 5,907,781 - Chen , et al. May 25, 1	1999-05-25
Simplified dual damascene process for multi-level metallization and interconnection structure Grant 5,635,423 - Huang , et al. June 3, 1	1997-06-03

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