U.S. patent application number 13/666611 was filed with the patent office on 2013-03-07 for method and apparatus for dynamic power management control using serial bus management protocols.
The applicant listed for this patent is Brian M. Morlock, Michael J. Schmitz, Christopher J. Tremel. Invention is credited to Brian M. Morlock, Michael J. Schmitz, Christopher J. Tremel.
Application Number | 20130061068 13/666611 |
Document ID | / |
Family ID | 41114340 |
Filed Date | 2013-03-07 |
United States Patent
Application |
20130061068 |
Kind Code |
A1 |
Tremel; Christopher J. ; et
al. |
March 7, 2013 |
METHOD AND APPARATUS FOR DYNAMIC POWER MANAGEMENT CONTROL USING
SERIAL BUS MANAGEMENT PROTOCOLS
Abstract
An apparatus for on-demand power management including an I/O
serial communication master device, peripheral devices that
communicate with the master device along the serial communications
bus, and a power manager that buffers the peripheral devices from
the serial communication master. The power manager also manages
voltage regulation and clock sources to the peripheral devices,
with the ability of placing the peripheral devices in an inactive
state, or in any number of active states as a means to conserve
energy. In some embodiments, the I/O serial communications master
acts as if the peripheral devices are always in the highest
activity state, and the power manager manages the communications to
and from the peripheral devices and the power management of the
peripheral devices to reduce energy consumption and system
latency.
Inventors: |
Tremel; Christopher J.;
(West Fargo, ND) ; Morlock; Brian M.; (West Fargo,
ND) ; Schmitz; Michael J.; (Fargo, ND) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Tremel; Christopher J.
Morlock; Brian M.
Schmitz; Michael J. |
West Fargo
West Fargo
Fargo |
ND
ND
ND |
US
US
US |
|
|
Family ID: |
41114340 |
Appl. No.: |
13/666611 |
Filed: |
November 1, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12411932 |
Mar 26, 2009 |
8312299 |
|
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13666611 |
|
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61072268 |
Mar 28, 2008 |
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Current U.S.
Class: |
713/300 |
Current CPC
Class: |
G06F 1/325 20130101;
G06F 1/3203 20130101; Y02D 10/126 20180101; G06F 1/324 20130101;
Y02D 10/00 20180101; G06F 1/3296 20130101; Y02D 10/172
20180101 |
Class at
Publication: |
713/300 |
International
Class: |
G06F 1/26 20060101
G06F001/26 |
Claims
1. A computer-implemented method, comprising: providing a first
operating voltage and a first clock frequency to a peripheral
device, operating in a first operating state, wherein the
peripheral device is coupled to an input-output (I/O) controller in
a processing system with a serial bus; monitoring bus transactions
on the serial bus using a power manager, coupled between the I/O
controller and the peripheral device, to assess a current
processing demand for the peripheral device; and dynamically
adjusting at least one of the first operating voltage or the first
clock frequency in response to the current processing demand.
2. The method of claim 1, wherein monitoring comprises: receiving
at the power manager a current bus transaction from the I/O
controller; and determining whether the peripheral device is to
operate in a second operating state to process the current bus
transaction, wherein the second operating state corresponds to the
current processing demand, and wherein dynamically adjusting
comprises switching the peripheral device to operate in the second
operating state to allow the peripheral device to process the
current bus transaction, wherein the first operating state is a
lower power state than the second operating state.
3. The method of claim 1, wherein dynamically adjusting comprises:
adjusting the first operating voltage to a second operating
voltage; and adjusting the first clock frequency to a second clock
frequency, wherein the second clock frequency is phase-locked to a
reference frequency and phase-matched to the first clock
frequency.
4. The method of claim 3, wherein adjusting the second clock
frequency comprises: generating the second clock frequency in
response to the current processing demand; and switching from the
first clock frequency to the second clock frequency without halting
the processing system.
5. The method of claim 1, wherein dynamically adjusting comprises
adjusting the first operating voltage to a second operating
voltage.
6. The method of claim 1, wherein dynamically adjusting comprises
adjusting the second clock frequency to a second clock frequency,
wherein the second clock frequency is phase-locked to a reference
frequency and phase-matched to the first clock frequency.
7. The method of claim 2, further comprising delaying the current
bus transaction from being sent to the peripheral device using the
power manager, wherein the current bus transaction is delayed until
the power manager finishes adjusting the at least one of the first
operating voltage or the first clock frequency.
8. The method of claim 7, wherein delaying the current bus
transaction comprises: storing the current bus transaction in a
buffer; and transmitting the current bus transaction to the
peripheral device when the power manager finishes the
adjusting.
9. The method of claim 7, wherein delaying the current bus
transaction comprises notifying the I/O controller that the
peripheral device is busy to pause the current bus transaction from
the I/O controller.
10. The method of claim 7, wherein delaying the current bus
transaction comprises stretching a clock signal between the I/O
controller and the power manager to place the I/O controller in a
wait state for the current bus transaction.
11. The method of claim 10, wherein the current bus transaction is
an inter-integrated circuit (I2C) transaction, and wherein
stretching the clock signal comprises holding the clock line
between the power manager and the I/O controller low until the
power manager finishes the adjusting to pause the I2C transaction
from the I/O controller.
12. The method of claim 1, wherein a plurality of peripheral
devices are coupled to the I/O controller by way of the power
manager, including the peripheral device, and wherein the
monitoring comprises: receiving a start signal from the I/O
controller for a current bus transaction; decoding a device address
of the current bus transaction to select one of the plurality of
peripheral devices to send the current bus transaction; delaying
the current bus transaction from being sent to the selected
peripheral device by placing the I/O controller in a wait state for
the current bus transaction; while delaying the current bus
transaction, powering up the selected peripheral device to a second
operating state from the first operating state by said dynamically
adjusting, wherein the first operating state is a lower power state
than the second operating state; and initiating a device
communication flow between the I/O controller and the peripheral
device for the current bus transaction when the selected peripheral
device is operating at the second operating state.
13. The method of claim 12, wherein the monitoring further
comprises powering down the selected peripheral device to the first
operating state from the second operating state when the current
bus transaction is completed.
14. The method of claim 12, wherein the monitoring further
comprises determining that the selected peripheral device is an I2C
device, and wherein initiating the device communication flow
comprises: sending the start signal to the I2C device; releasing
the clock line between the I/O controller and the power manager to
activate the I/O controller from the wait state; and buffering data
and clock lines between the I/O controller and the I2C device.
15. The method of claim 12, wherein the monitoring further
comprises determining that the selected peripheral device is a
universal asynchronous receiver and transceiver (UART) device, and
wherein initiating the device communication flow comprises
determining whether the current bus transaction is a read operation
or a write operation, wherein if the current bus transaction is a
read operation, the determining comprises: for each byte of data to
be read, holding the clock line between the I/O controller and the
power manager low; reading a byte of data from a buffer of the UART
device; releasing the clock line between the I/O controller and the
power manager; and sending the byte to the I/O controller, and
wherein if the current bus transaction is a write operation, the
determining comprises: for each byte of data to be written,
buffering a byte received from the I/O controller; acknowledging
the I/O controller; holding the clock line between the I/O
controller and the power manager low; sending the byte received
from the I/O controller to the UART device; and releasing the clock
line between the I/O controller and the power manager.
16. An apparatus, comprising: a first bus interface coupled to an
input-output (I/O) controller to communicate bus transactions of a
serial bus between the I/O controller and a peripheral device in a
processing system; a second bus interface coupled to the peripheral
device to communicate the bus transactions of the serial bus
between the I/O controller and the peripheral device, wherein the
first peripheral device is operated at a first operating state; and
a monitoring engine coupled to the first and second bus interfaces
to monitor the bus transactions on the serial bus to assess a
current processing demand for the peripheral device, and to
dynamically adjust at least one of a first operating voltage or a
first clock frequency, supplied to the peripheral device in the
first operating state, in response to the current processing
demand.
17. The apparatus of claim 16, wherein the monitoring engine is
configured to receive a current bus transaction from the I/O
controller, to determine whether the peripheral device is to
operate in a second operating state for the current bus
transaction, and to switch the peripheral device to operate in the
second operating to allow the peripheral device to process the
current bus transaction, wherein the first operating state is a
lower power state than the second operating state.
18. The apparatus of claim 17, further comprising an adjustable
voltage regulator coupled to receive a signal from the monitoring
engine to adjust the first operating voltage supplied to the
peripheral device to a second operating voltage when the monitoring
engine switches the peripheral device to the second operating
state.
19. The apparatus of claim 17, further comprising a multiplexer
coupled to the monitoring engine to adjust the first clock
frequency to a second clock frequency when the monitoring engine
switches the peripheral device to the second operating state.
20. The apparatus of claim 17, further comprising a converter
coupled between the monitoring engine and the second bus interface
to translate a first bus protocol of the current bus transaction,
used by the I/O controller, to a second bus protocol, used by the
peripheral device.
21. A computer-implemented method, comprising: buffering bus
transactions on a serial bus between a plurality of peripheral
devices and a host processing device in a processing system using a
power manager; monitoring the bus transactions on the serial bus to
assess a current processing demand for at least one of a plurality
of peripheral devices, wherein the current processing demand
correlates to an operating state of the at least one peripheral
device; and compensating for the current processing demand by
dynamically scaling at least one of an operating voltage or a clock
frequency supplied to the at least one peripheral device to meet
the current processing demand.
22. The method of claim 21, wherein the at least one peripheral
device is operating at a first clock frequency, and wherein
dynamically scaling the clock frequency supplied to the at least
one peripheral device comprises: generating a second clock
frequency in response to the current processing demand, wherein the
second clock frequency is phase-matched to the first clock
frequency; and switching from the first clock frequency to the
second clock frequency without halting the processing system.
23. The method of claim 21, wherein the at least one peripheral
device is operating at a first voltage, and wherein dynamically
scaling the operating voltage supplied to the at least one
peripheral device comprises: generating a second voltage in
response to the current processing demand; and switching from the
first voltage to the second voltage without halting the processing
system.
Description
RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 12/411,932, filed Mar. 26, 2009, which claims
the benefit of U.S. Provisional Application No. 61/072,268, filed
Mar. 28, 2008, which are hereby incorporated by reference in its
entirety.
TECHNICAL FIELD
[0002] The present invention relates generally to power management
and in particular to managing voltages and frequencies supplied to
peripheral devices in response to processing demands, using bus
management methods as a means to assess processing demand and
control dynamic voltage and frequency scaling.
BACKGROUND
[0003] As digital electronic processing systems trend toward higher
operating frequencies and smaller device geometries, power
management has become increasingly important to prevent thermal
overload while maintaining system performance and prolonging
battery life in portable systems.
[0004] The two principal sources of power dissipation in digital
logic circuits are static power dissipation and dynamic power
dissipation. Static power dissipation is dependent on temperature,
device technology and processing variables, and is composed
primarily of leakage currents. Dynamic power dissipation is the
predominant loss factor in digital circuitry and is proportional to
the operating clock frequency, the square of the operating voltage
and the capacitive load. Capacitive load is highly dependent on
device technology and processing variables, so most approaches to
dynamic power management focus on frequency and voltage
control.
[0005] Digital design architectures are characterized as having a
master or controller interoperating with a number of devices on a
shared bus, also referred to as a shared communication channel. One
conventional approach is to have all peripheral devices connected
on a communication bus to be powered from a common power
distribution system. The power management algorithms will enable or
disable devices along this power distribution system as needed, in
order to conserve energy from devices when they are not required
for system operation. The means to enable and disable devices is
controlled by software, typically by the input/output (I/O)
controller of the serial communications bus.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The present invention is illustrated by way of example, and
not of limitation, in the figures of the accompanying drawings in
which:
[0007] FIG. 1 illustrates one embodiment of on-demand power
management in a processing system 100;
[0008] FIG. 2A illustrates one embodiment of on-demand power
management design with an I/O controller and the same devices on a
serial bus;
[0009] FIG. 2B illustrates one embodiment of the power manager of
FIG. 2A.
[0010] FIG. 3 illustrates one embodiment of a bus multiplexing
flow;
[0011] FIGS. 4A-4C illustrate one embodiment of a device
communication flow; and
[0012] FIG. 5 illustrates one embodiment of phase-matching in
on-demand power management.
DETAILED DESCRIPTION
[0013] In the following description, numerous specific details are
set forth such as examples of specific components, devices,
methods, etc., in order to provide a thorough understanding of
embodiments of the present invention. It will be apparent, however,
to one skilled in the art that these specific details need not be
employed to practice embodiments of the present invention. In other
instances, well-known materials or methods have not been described
in detail in order to avoid unnecessarily obscuring embodiments of
the present invention. It should be noted that the "line" or
"lines" discussed herein, that connect elements, may be single
lines or multiple lines. It will also be understood by one having
ordinary skill in the art that lines and/or other coupling elements
may be identified by the nature of the signals they carry (e.g., a
"clock line" may implicitly carry a "clock signal") and that input
and output ports may be identified by the nature of the signals
they receive or transmit (e.g., "clock input" may implicitly
receive a "clock signal").
[0014] Various embodiments of on-demand power management are
described, specifically improving upon a system using serial
communication structures between components. The embodiments
described herein are directed at reducing the total energy
consumption of the peripheral devices. The embodiments described
herein relate to a power management scheme that manages voltages
and frequencies of the peripheral devices in response to processing
demands, using bus management methods as a means to assess
processing demand and control dynamic voltage and frequency
scaling.
[0015] In one embodiment, an apparatus for on-demand power
management includes an I/O serial communication master device,
peripheral devices that communicate with the master along the
serial communications bus, and a power manager that buffers the
peripheral devices from the serial communication master. The power
manager also manages voltage regulation and clock sources to the
peripheral devices, with the ability of placing the peripheral
devices in an inactive state, or in any number of active states as
a means to conserve energy. In some embodiments, the I/O serial
communication master device acts as if the peripheral devices are
always in the highest activity state, and the power manager manages
the communications to and from the peripheral devices and the power
management of the peripheral devices to reduce energy consumption
and system latency.
[0016] In one embodiment, a power manager is disposed between an
I/O controller (e.g., I/O controller of a host processing device)
and a peripheral device. The power manager adjusts the operating
voltage and/or clock frequency of the peripheral device to reduce
power consumption, depending on the operating state of operation of
the peripheral device. The power manager determines the operating
state of the peripheral device by monitoring and buffering the bus
transactions between the I/O controller and the peripheral device
to determine the current processing demand. If a particular bus
transaction requires that the peripheral device be in a different
operating or power state, the power manager can delay the bus
transactions sent from the I/O controller until the power manager
has finished adjusting the operating voltage and/or clock frequency
required for the new operating state. For example, the power
manager can hold the clock line low for the serial bus (e.g., an
inter-IC (I2C or I.sup.2C) bus) to pause the bus transaction being
sent from the I/O controller. In addition, a bus multiplexer could
be combined with the power manager such that multiple peripheral
devices using different types of busses could be managed by one
power manager with an interface to one I/O controller via one bus.
The bus multiplexer power manager can translate between different
protocols and bus communication schemes.
[0017] In one embodiment, the method includes monitoring a serial
bus to assess a processing demand for a peripheral device in a
processing system. The serial bus is sometimes referred to as a
serial communication channel. The processing demand is correlated
to energy demand, which is appropriately addressed with dynamic
voltage scaling and dynamic frequency scaling. The dynamic
frequency scaling also includes generating a second set of one or
more clock frequencies in response to the processing demand, and
switching to the second set of clock frequencies from a first set
of one or more clock frequencies. The second set of one or more
clock frequencies are phase-locked to the reference frequency and
phase-matched to the first set of one or more clock frequencies.
The method also includes switching from the first set of clock
frequencies to the second set of clock frequencies without halting
the processing system. In one embodiment, the method further
includes generating a first set of one or more operating voltages
in response to the processing demand, and switching from a first
set of one or more operating voltages to the second set of one or
more operating voltages without halting the processing system.
[0018] FIG. 1 illustrates one embodiment of on-demand power
management in a processing system 100. Processing system 100
includes an I/O controller 101. The I/O controller 100 may be part
of a general-purpose processing device such as a microprocessor or
central processing unit, or the like. Alternatively, I/O controller
101 may also be part of a special-purpose processing device such as
an application specific integrated circuit (ASIC), a field
programmable gate array (FPGA), a digital signal processor (DSP) or
the like. The I/O controller 101 may also be any combination of a
general-purpose processing device and a special-purpose processing
device. Alternatively, the I/O controller 101 may be part of a
chipset that extends the bus of a host processing device to the
peripheral devices. In the following discussion, I/O controller 101
acts as an I/O serial communication master device in the processing
system 100, such as, for example, an I2C master. In one embodiment,
the I/O controller 101 is coupled to a host processing device (not
illustrated), such one or more microprocessors, or central
processing units, or the like.
[0019] The I/O controller 101 is coupled to a system bus 102 which
carries system data and commands to and from the I/O controller
101. The system bus 102 is a serial communication bus. The system
bus 102 is coupled to peripheral devices 103, which provide input
and output functions to the processing system 100. A peripheral
device is a device attached to a host processing device (e.g., host
computer), and whose primary functionality is dependent upon the
host, and can therefore be considered as expanding the host's
capabilities, while not forming part of the host's core
architecture. The peripheral devices 103 may be on-chip integrated
peripheral devices, such an Ethernet device, a memory device, a USB
device, audio devices, or the like. The peripheral device may also
be other types of I/O devices, for example, displays, keyboards,
wireless communication channel devices, wired communication channel
devices, user input devices, printers, scanners, disk drives, tape
drives, microphones, speakers, cameras, or the like.
[0020] Processing system 100 also includes a power manager 105
(also referred to herein as bus multiplexing power manager), which
may be coupled to system bus 102, a frequency source 108, and a
voltage source 109, as illustrated in FIG. 2A. The power manager
105 is coupled to I/O controller 101 and peripheral devices 103-1
through 103-k via system bus 102, which may include a clock bus and
voltage bus. The power manager 105 buffers the peripheral devices
103 from the serial communication master, the I/O controller 101.
The power manager 105 manages voltage regulation and clock sources
to the peripheral devices 103, with the ability of placing the
peripheral devices 103 in an inactive state, or in any number of
active states as a means to conserve energy. In some embodiments,
the I/O controller 101 acts as if the peripheral devices 103 are
always in the highest activity state, and the power manager 105
manages the communications to and from the peripheral devices 103
and the power management of the peripheral devices 103 to reduce
energy consumption and system latency.
[0021] In one embodiment, as illustrated in FIG. 2A, the power
manager 105 is coupled to the external frequency source 108, and
uses the reference frequency f.sub.0 from frequency source 108 to
generate one or more clock frequencies f.sub.1 through f.sub.m,
phase-locked to the reference frequency f.sub.0, to provide clock
signals to the I/O controller 101 and the peripheral devices 103-1
through 103-k. In another embodiment, the frequency source 108 may
provide multiple clock frequencies to the power manager 105, and
the power manager 105 can provide the appropriate clock frequency
to one or more of the peripheral devices 103. In other embodiments,
frequency source 108 may be integrated with the power manager 105
and reside with the power manager 105 on a common carrier substrate
such as, for example, an integrated circuit (IC) die substrate, a
multi-chip module substrate, or the like.
[0022] In one embodiment, as illustrated in FIG. 2A, the power
manager 105 is coupled to the voltage source 109, and uses a
voltage V.sub.0 from the voltage source 109 to generate one or more
operating voltages V.sub.1 through V.sub.n to provide voltages to
the I/O controller 101 and peripheral devices 103-1 through 103-k.
In another embodiment, the voltage source 109 may provide multiple
operating voltages to the power manager 105, and the power manager
105 can select the appropriate operating voltage to provide to one
or more of the peripheral devices 103. In other embodiments,
voltage source 109 may be integrated with the power manager 105 and
reside with the power manager 105 on a common carrier substrate
such as, for example, an IC die substrate, a multi-chip module
substrate, or the like.
[0023] Each of the I/O controller 101 and the peripheral devices
103-1 through 103-k may have one or more voltage inputs and one or
more clock inputs. In one embodiment, two or more of I/O controller
101, power manager 105, frequency source 108, and peripheral
devices 103-1 through 103-k may reside on a common carrier
substrate, for example, a printed circuit board (PCB) such as
motherboard, a daughter board, or a line card. Alternatively, the
common carrier substrate on which the two or more of I/O controller
101, power manager 105, frequency source 108, voltage source 109,
and peripheral devices 103-1 through 103-k may reside on IC die
substrate.
[0024] With reference to FIG. 2A, peripheral devices 103-1 through
103-k may be any type of device, component, circuit, subsystem or
system capable of communicating with I/O controller 101 via system
bus 102. For example, any of peripheral devices 103-1 through 103-k
may be a single chip device such as a system on a chip, an ASIC, an
FPGA, a memory chip or like device. Any of peripheral devices 103-1
through 103-k may also be a multi-chip module including any
combination of single chip devices on a common integrated circuit
substrate. Alternatively, peripheral devices 103-1 through 103-k
may reside on one or more printed circuit boards such as, for
example, a mother board, a daughter board or other type of circuit
card. The serial bus 102 between the I/O controller 101 and the
power manager 105 may be any type of serial bus, such as, for
example, a serial peripheral interface (SPI) bus, an I2C bus, a
universal asynchronous receiver and transceiver (UART) bus, a
System Management bus (SMB or SMBus), a one-wire bus, or the
like.
[0025] In the depicted embodiment of FIG. 2A, the system bus 102 is
an I2C bus, and the peripheral device 103-1 is a SPI device,
peripheral device 103-2 is an I2C device, and peripheral device
103-k is a UART device. The buses between the power manager 105 and
the respective peripheral devices 103 are based on the type of the
particular peripheral device. Alternatively, the system bus 102 may
be other types of serial buses, and the peripheral devices, and
their corresponding buses may be other types than those depicted in
FIG. 2A.
[0026] In one embodiment, the power manager 105 is capable of
monitoring a bus transaction from the I/O controller 101 and
determining whether the bus transaction is addressed to the SPI
device, the I2C device, or the UART device. Details of one
embodiment of a bus multiplexing flow between the I/O controller
101 (e.g., I2C master device) and the power manager 105, and the
power manager 105 and these different types of peripheral devices
103-1 through 103-k in processing system 100 are described below
with respect to FIGS. 3 and 4A-4C.
[0027] FIG. 2B illustrates one embodiment of the power manager 105
of FIG. 2A. The power manager 105 is coupled to the I/O controller
101 by way of the bus 102, and is coupled to the peripheral devices
103-1 through 103-3 by way of bus lines 104-1 through 104-3,
respectively. The power manager 105 includes a bus interface unit
(BIU) 116 that is coupled to the bus 102 to communicate bus
transactions to and from the I/O controller 101. Similarly, BIUs
106-1 through 106-3 are coupled to the bus lines 104-1 through
104-3, respectively, to communicate bus transactions to and from
the peripheral device 103-1 through 103-3, respectively. The BIUs
in the power manager 105 are the physical circuit interfaces that
enable the internal bus signals of the power manager 105 to connect
to the external busses (e.g., 102, 104-1 through 104-3).
[0028] In one embodiment, the power manager 105 can inform the I/O
controller 101 that a particular peripheral device is busy by
sending a busy signal 111 to pause the transmission of the bus
transaction until the particular peripheral device is ready for the
bus transaction. The busy signal 111 sent by the power manager 105
to the I/O controller can be part of, or separate from the serial
bus 102 connecting the I/O controller 101 and the power manager
105. For example, the busy signal 111 may be embedded within the
serial bus 102 to be used for clock stretching when the serial bus
102 is an I2C bus, a SMBus, or the like.
[0029] The power manager 105 includes a monitoring engine 200
coupled to the BIU 116 to monitor bus transactions between the I/O
controller 101 and the peripheral device 103. The monitoring engine
200 decodes the data (e.g., bus transaction) transmitted by the I/O
controller 101 and determines which peripheral device to which the
data from the I/O controller 101 should be transmitted. The
monitoring engine 200 also determines what operating state (also
referred to as power state) the peripheral devices must be in based
on the data being transmitted by the I/O controller 101. For
example, the monitoring engine 200 uses the determined operating
state to adjust the operating voltage and clock frequency supplied
to the peripheral devices such that energy consumption and/or power
consumption is reduced.
[0030] In one embodiment, the monitoring engine 200 monitors the
bus transactions to assess processing demand for the peripheral
devices 103, and the monitoring engine 200 dynamically adjusts
either or both operating voltage on the voltage lines 114-1 through
114-3 and the clock frequency for the peripheral device on the
clock lines 115-1 through 115-3 based on the processing demands.
Each of the processing demands correlate to the required operating
state for the peripheral device to process the particular bus
transaction.
[0031] In one embodiment, the monitoring engine 200 determines
whether the peripheral devices 103-1 through 103-3 are to operate
in a specified operating state for one or more bus transactions. In
one embodiment, the monitoring engine 200 switches one or more of
the peripheral devices 103 from a first operating state to a second
operating state based on the determinations. In the depicted
embodiment, the monitoring engine 200 switches to the second
operating state by sending a signal 112 (Vset) to adjustable
voltage regulators 210 to adjust the operating voltages of the
peripheral devices 103. The adjustable voltage regulators 210
receives an operating voltage (V.sub.0) from voltage source(s) 109,
and provide the adjusted operating voltages to the peripheral
devices 103-1 through 103-k by way of voltage lines 114-1 through
114-3, respectively. Alternatively, the adjustable voltage
regulators 210 can receive multiple voltages from the voltage
source(s) 109, and select the appropriate voltage to provide to the
peripheral devices 103-1 through 103-k by way of voltage lines
114-1 through 114-3, respectively.
[0032] In the depicted embodiment, the monitoring engine 200
switches to the second operating state by sending a signal 113
(Fset) to multiplexers 220 to adjust the clock frequencies of the
peripheral devices. The adjustable voltage regulators 210 provide
the adjusted clock frequencies to the peripheral devices 103-1
through 103-k by way of clock lines 115-1 through 115-3,
respectively. In one embodiment, the multiplexer 220 receives the
reference frequency f.sub.0 from frequency source 108, and one or
more clock frequencies f.sub.1 through f.sub.m, which are generated
by the power manager 105. The multiplexers 220 receives a command
or a signal from the monitoring engine 200 to select which of
available frequencies to provide as a clock signal to the
peripheral devices 103. The one or more clock frequencies f.sub.1
through f.sub.m for the clock signals are phase-locked to the
reference frequency f.sub.0, and the one or more clock frequencies
f.sub.1 through f.sub.m may be phased-matched with one another, as
described below. In another embodiment, the multiplexers 220
receive multiple clock frequencies one or more frequency sources,
which are either part of the power manager 105 or external to the
power manager 105, such as the frequency source(s) 108. In another
embodiment, the reference frequency f.sub.0 is provided to the
power manager 105 from the I/O controller 101, and the power
manager 105 generates the one or more clock frequencies f.sub.1
through f.sub.m. In another embodiment, the power manager 105
receives the reference frequency f.sub.0 from an external source,
such as the frequency source 108, and provides the reference
frequency f.sub.0 to the I/O controller 101, and the power manager
105 generates the one or more clock frequencies f.sub.1 through
f.sub.m and provides the one or more clock frequencies f.sub.1
through f.sub.m to the peripherals 103 as directed by the
monitoring engine 200. Although FIG. 2B depicts the clock signals
being provided to the peripheral devices through clock lines 115,
in another embodiment, the clock signals may be provided to the
peripheral devices by way of the bus lines 104-1 through 104-3, and
the multiplexers 220 are integrated into the monitoring engine
200.
[0033] In the depicted embodiment, the monitoring engine 200 is
coupled to the peripheral devices 103-1 through 103-3 by way of the
BIUs 106-1 through 106-3, which are coupled to the bus lines 104-1
through 104-3, respectively. Since the peripheral devices 103 may
be different types of devices and may communicate using different
types of bus protocols, converters 107-1 through 107-3 can be
coupled between the monitoring engine 200 and the BIUs 106-1
through 106-3, respectively, to translate between different
protocols and bus communication schemes. The converters 107-1
through 107-3 converts the bus protocol used on the system bus 102
that interfaces the I/O controller 101 to the power manager 105 to
a different bus protocol that is used on the bus (e.g., 104-1,
104-2, or 104-3) that interfaces the power manager 105 to a
peripheral device (e.g., 103-1, 103-2, or 103-3). In one
embodiment, the converters 107-1 through 107-3 are Media Access
Control (MAC) converters. For example, the converter 107-1
translate a first bus protocol, used by the I/O controller 101
(e.g., I2C protocol), to a second bus protocol, used by the
peripheral device (e.g., SPI protocol since the peripheral device
103-1 is a SPI device). In another embodiment, the BIUs 106 and the
converters 107 may be integrated together to handle both the bus
protocol conversions (MAC conversions) and the physical (PHY)
conversions. In some embodiments, the converters may not translate
the bus protocol when the bus protocols are the same for the I/O
controller 103 and the peripheral device 103. For example, the
converter 107-2 does not need to translate the I2C bus protocol,
used by the I/O controller 101, since the peripheral device 103-2
is an I2C device. Alternatively, other configurations of devices
and bus protocols may be used, as would be appreciated by one of
ordinary skill in the art having the benefit of this disclosure by
one of ordinary skill in the art having the benefit of this
disclosure.
[0034] In one embodiment, the monitoring engine 200 receives a
current bus transaction from the I/O controller 101 over the serial
bus 102 and determines whether the destination peripheral device is
to operate in a second operating state to process the current bus
transaction, and switches the destination peripheral device to
operate in the second operating state to allow the peripheral
device to process the current bus transaction. The second operating
state corresponds to the current processing demand for the
destination peripheral device. In this embodiment, the first
operating state is a lower power state than the second operating
state.
[0035] FIG. 3 illustrates one embodiment of a bus multiplexing
flow. The flow may be performed by processing logic of various
components in processing system 100 described above, such as I/O
controller 101 and power manager 105 in FIGS. 2A and 2B. Processing
logic may include software, hardware, or a combination of both.
Referring to FIG. 3, processing logic waits for an I/O controller
start signal of a bus transaction from a master device, such as the
I/O controller 101 in FIGS. 1, 2A, and 2B (processing block 310).
The processing system includes a serial communication bus, such as
the system bus 102 in FIGS. 1, 2A and 2B. In the depicted
embodiment, the I/O controller 101 is an I2C device. Processing
logic decodes an I2C device address on the serial bus (processing
block 315) for the bus transaction. Then processing logic checks if
the I2C device address is valid (processing block 320). If the I2C
device address is not valid, then processing logic returns to
processing block 310. Otherwise, processing logic transitions to
processing block 325.
[0036] At processing block 325, processing logic delays the bus
transaction until the power manager has finished adjusting the
operating voltage and/or clock frequency required for the new
operating state. In one embodiment, the processing logic delays the
bus transaction by stretching a clock signal while the master
device waits in this state. In clock stretching, the power manager
105 may hold the clock line (SCL1) low after receiving (or sending)
a bit, indicating that it is not yet ready to process more data.
Alternatively, the power manager 105 may hold the clock line (SCL2)
low. Clock stretching allows the power manager 105 to control the
flow of incoming data.
[0037] In some embodiments, processing logic stretches the clock
signal by holding the I2C clock low in the I2C bus to pause the I2C
transaction from the I/O controller 101. In another embodiment, the
processing logic delays the bus transaction by storing the clock
signal in a buffer and retransmitting it at a later time. In
another embodiment, the power manager can inform the I/O controller
101 that the peripheral device is busy (busy signal 111 depicted in
FIG. 2B), such that the I/O controller 101 pauses the transmission
of the bus transaction until a later time. Then processing logic
powers up the addressed peripheral device addressed (processing
block 330). In one embodiment, the processing logic powers up the
addressed peripheral device by adjusting the voltage supply and
clock frequency. In another embodiment, the processing logic powers
up the addressed peripheral device by adjusting the voltage supply
or the clock frequency. Processing logic initiates a device
communication flow (processing block 335). Details of some
embodiments of the device communication flow are discussed below
with reference to FIGS. 4A-4C. Then the bus transaction is
completed in processing block 340. Subsequently, processing logic
powers down the device (processing block 345) and returns to
processing block 310.
[0038] FIGS. 4A-4C illustrate one embodiment of a device
communication flow. The flow may be performed by processing logic
of various components in system 100 described above, such as I/O
controller 101 and power manager 105 in FIGS. 2A and 2B. Processing
logic may include software, hardware, or a combination of both.
Referring to FIG. 4A, processing logic determines if an I2C device
is addressed (processing block 410). If so, processing logic sends
the START byte of the current bus transaction to an I2C slave
device (processing block 412). Processing logic then releases an
I2C clock line to activate the master device (processing block 414)
to continue with the bus transaction. Processing logic further
buffers the clock line (SCL1) and the data line (SDA1) between the
master device and the slave device (processing block 416), and the
process ends at processing block 418. Otherwise, processing logic
transitions to processing block 420.
[0039] At processing block 420, processing logic determines if a
SPI device is addressed. If so, processing logic asserts a chip
select (CS) signal for the SPI device (processing block 422). Then
processing logic releases I2C clock line to activate the master
device (processing block 424) to continue with the bus transaction.
Next, referring to FIG. 4B, processing logic determines if a read
or a write operation is to be performed (processing block 426).
[0040] If a write operation is to be performed, processing logic
buffers a byte of data from the master device (processing block
430). Processing logic acknowledges the master device (processing
block 432). Processing logic stretches the clock by holding the I2C
clock low (processing block 434). Then processing logic sends the
byte to the SPI device (processing block 436). Subsequently,
processing logic releases SCL (processing block 438). Then
processing logic checks if the data transfer has been stopped
(processing block 439). If not, processing logic returns to
processing block 430. Otherwise, the process ends at processing
block 450.
[0041] If a read operation is to be performed, processing logic
holds the I2C clock low (processing block 440). Then processing
logic reads a byte of data for the SPI device (processing block
442). Processing logic then releases the I2C clock (processing
block 444). Processing logic sends the byte of data to I2C master
device (processing block 446). Then processing logic checks if the
data transfer has been stopped (processing block 448). If not,
processing logic returns to processing block 440. Otherwise, the
process ends at processing block 450.
[0042] Referring back to processing block 420 in FIG. 4A, if
processing logic determines that the SPI device is not addressed,
then the device addressed is an UART device. Thus, processing logic
transitions to processing block 428 in FIG. 4C to determine if a
write or a read operation is to be performed. Referring to FIG. 4C,
if a write operation is to be performed, processing logic buffers a
byte of data from the master device (processing block 470). Then
processing logic acknowledges the master device (processing block
472). Then processing logic holds the I2C clock low (processing
block 474). Processing logic further sends the byte of data to the
UART device (processing block 476). Processing logic then releases
the I2C clock (processing block 478). Then processing logic checks
if the data transfer has been stopped (processing block 479). If
not, processing logic returns to processing block 470. Otherwise,
the process ends at processing block 480.
[0043] If a read operation is to be performed on the UART device,
processing logic transitions from processing block 428 to
processing block 460. Processing logic holds I2C clock low
(processing block 460). Then processing logic reads a byte of data
from a buffer (e.g., a first-in-first-out buffer) of the UART
device (processing block 462). Next, processing logic releases the
I2C clock (processing block 464). Processing logic sends the byte
of data to the I2C master device (processing block 466). Then
processing logic checks if the data transfer has been stopped
(processing block 468). If not, processing logic returns to
processing block 460. Otherwise, the process ends at processing
block 480.
[0044] In another embodiment, the processing logic provides a first
operating voltage and a first clock frequency to a peripheral
device 103, operating at a first operating state. The processing
logic monitors bus transactions on a serial bus (e.g., bus 102 and
104) between the I/O controller and the peripheral device to assess
a current processing demand for the peripheral device 103, and
dynamically adjust one or both of the first operating voltage and
first clock frequency in response to the current processing demand.
The processing logic can monitor the bus transactions by receiving
a current bus transaction from the I/O controller 101, and
determining whether the peripheral device 103 is to operate in a
second lower-power operating state to process the current bus
transaction. The processing logic switches the peripheral device
103 to operate in the second operating state to allow the
peripheral device 103 to process the current bus transaction. The
processing logic can delay the current bus transaction being sent
to the peripheral device 103 until the processing logic has
finished adjusting the operating voltage and/or the clock
frequency. In one embodiment, the processing logic delays the
current bus transaction by storing the current bus transaction in a
buffer, and subsequently transmitting the current bus transaction
to the peripheral device 103 when the processing logic has finished
the adjusting. In another embodiment, the processing logic delays
by notifying the I/O controller 101 that the peripheral device is
busy, for example, by sending a busy signal (e.g., 111 in FIG. 2B).
Alternatively, the processing logic may delay by stretching a clock
signal between the I/O controller 101 and the power manager 105 to
place the I/O controller 101 in a wait state for the current bus
transaction.
[0045] It will be appreciated by one of ordinary skill in the art
that all clock frequencies f.sub.1-f.sub.m will be harmonically
related because all are phase-locked to the common reference
frequency 110 (f.sub.0). In particular, any two clock frequencies
in a single frequency control channel (e.g., clock frequencies
f.sub.1' and f.sub.1'' in frequency control channel 501-1) will be
harmonically related. FIG. 5 illustrates how this harmonic
relationship may be used to switch between a first clock frequency
and a second clock frequency without halting the processing system
100. FIG. 5 depicts reference frequency 110 having frequency
f.sub.0 and period T.sub.0 a=1/f.sub.0, clock frequency
f.sub.1'=Af.sub.0 and period T.sub.1=T.sub.0/A, and frequency
f.sub.1''=Bf.sub.0 and period T.sub.2=T.sub.0/B. As shown in FIG.
5, the phase of clock frequency f.sub.1' will periodically align
with the phase of clock frequency f.sub.1'' (e.g., at times
t.sub.1, t.sub.2, t.sub.3, etc.) at time intervals corresponding to
the lowest common multiples of T.sub.1 and T.sub.2. This time
interval may be calculated, for example, by I/O controller 101.
Therefore, when a new operating state is commanded by the
monitoring engine 200 in response to the processing demand, the
switch from the first clock frequency (e.g., f.sub.1') to the
second clock frequency (e.g., f.sub.1'') may be timed to occur when
the phases of the first clock frequency and the second clock
frequency are aligned. If the phases of the first clock frequency
and the second clock frequency are aligned when the frequencies are
switched (e.g., by a multiplexer), there is no phase discontinuity
in the processing system 100 and the frequencies may be switched
without halting the processing system 100. In one embodiment, the
ratio of the second clock frequency to the first clock frequency
may be very large, approximately up to six orders of magnitude
depending on the stability of the reference frequency 110.
Alternatively, other ratios may be used.
[0046] Thus, a method and apparatus for on-demand power management
has been described. It will be apparent from the foregoing
description that aspects of the present invention may be embodied,
at least in part, in software. That is, the techniques may be
carried out in a computer system or other data processing system in
response to a processing device executing sequences of instructions
contained in a memory. In various embodiments, hardwired circuitry
may be used in combination with software instructions to implement
the present invention. Thus, the techniques are not limited to any
specific combination of hardware circuitry and software or to any
particular source for the instructions executed by the data
processing system. For example, in some embodiments, the techniques
may be carried out using firmware (e.g., embedded software).
Alternatively, the techniques may be carried out using any
combination of hardware, firmware, and software. In addition,
throughout this description, various functions and operations may
be described as being performed by or caused by software code to
simplify description. However, those skilled in the art will
recognize what is meant by such expressions are that the functions
result from execution of the code by a processor or controller.
[0047] A machine-readable medium can be used to store software and
data which when executed by a data processing system causes the
system to perform various methods of the present invention. This
executable software and data may be stored in various places
including, for example, read-only memory (ROM) and programmable
memory or any other device that is capable of storing software
programs and/or data.
[0048] Thus, a computer-readable medium includes any mechanism that
stores information in a form accessible by a machine (e.g., a
computer, network device, personal digital assistant, manufacturing
tool, any device with a set of one or more processors, etc.). For
example, a computer-readable medium includes
recordable/non-recordable media (e.g., read only memory (ROM);
random access memory (RAM); magnetic disk storage media; optical
storage media; flash memory devices; etc.); etc. In one embodiment,
the computer-readable medium stores instruction therein that, when
executed by a processing device, cause the processing device to
perform the operations described herein.
[0049] It should be appreciated that references throughout this
specification to "one embodiment" or "an embodiment" means that a
particular feature, structure or characteristic described in
connection with the embodiment is included in at least one
embodiment of the present invention. Therefore, it is emphasized
and should be appreciated that two or more references to "an
embodiment" or "one embodiment" or "an alternative embodiment" in
various portions of this specification are not necessarily all
referring to the same embodiment. Furthermore, the particular
features, structures or characteristics may be combined as suitable
in one or more embodiments of the invention. In addition, while the
invention has been described in terms of several embodiments, those
skilled in the art will recognize that the invention is not limited
to the embodiments described. The embodiments of the invention can
be practiced with modification and alteration within the scope of
the appended claims. The specification and the drawings are thus to
be regarded as illustrative instead of limiting on the
invention.
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