Tremel; Christopher J

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tremel; Christopher J.The latest application filed is for "method and apparatus for dynamic power management control using serial bus management protocols".

Company Profile

0.6.7

Tremel; Christopher J - West Fargo ND US
Tremel; Christopher J. - West Fargo ND
Tremel; Christopher J. - St. Louis Park MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Synchronization of position and current measurements in an electric motor control application using an FPGA Grant 8,779,705 - Wu , et al. July 15, 2	2014-07-15
Method And Apparatus For Dynamic Power Management Control Using Serial Bus Management Protocols App 20130061068 - Tremel; Christopher J. ; et al.	2013-03-07
Method and apparatus for dynamic power management control using serial bus management protocols Grant 8,312,299 - Tremel , et al. November 13, 2	2012-11-13
Synchronization of Position and Current Measurements in an Electric Motor Control Application using an FPGA App 20120217909 - Wu; Long ; et al.	2012-08-30
Method And Apparatus For Dynamic Power Management Control Using Serial Bus Management Protocols App 20090249089 - Tremel; Christopher J. ; et al.	2009-10-01
Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design Grant 7,231,625 - Dillon , et al. June 12, 2	2007-06-12
Process for designing base platforms for IC design to permit resource recovery and flexible macro placement, base platform for ICs, and process of creating ICs Grant 7,216,323 - Dillon , et al. May 8, 2	2007-05-08
Process for designing base platforms for IC design to permit resource recovery and flexible macro placement, base platform for ICs, and process of creating ICs App 20060095880 - Dillon; Michael N. ; et al.	2006-05-04
Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design App 20060075369 - Dillon; Michael N. ; et al.	2006-04-06
Method of repeater insertion for hierarchical integrated circuit design Grant 6,662,349 - Morgan , et al. December 9, 2	2003-12-09
Method of repeater insertion for hierarchical integrated circuit design App 20030163795 - Morgan, David A. ; et al.	2003-08-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.