U.S. patent application number 13/633425 was filed with the patent office on 2013-02-14 for spiral staircase shaped stacked semiconductor package and method for manufacturing the same.
This patent application is currently assigned to HYNIX SEMICONDUCTOR INC.. The applicant listed for this patent is HYNIX SEMICONDUCTOR INC.. Invention is credited to Jung Tae JEONG, Jae Myun KIM, Ki Bum KIM, Tae Hoon KIM, Bok Gyu MIN, Da Un NAH.
Application Number | 20130040425 13/633425 |
Document ID | / |
Family ID | 43973557 |
Filed Date | 2013-02-14 |
United States Patent
Application |
20130040425 |
Kind Code |
A1 |
NAH; Da Un ; et al. |
February 14, 2013 |
SPIRAL STAIRCASE SHAPED STACKED SEMICONDUCTOR PACKAGE AND METHOD
FOR MANUFACTURING THE SAME
Abstract
A spiral staircase shaped stacked semiconductor package is
presented. The package includes a semiconductor chip module, a
substrate and connection members. The semiconductor chip module
includes at least two semiconductor chips which have chip selection
pads and through-electrodes. The semiconductor chips are stacked
such that the chip selection pads are exposed and the
through-electrodes of the stacked semiconductor chips are
electrically connected to one another. The substrate has the
semiconductor chip module mounted thereto and has connection pads.
The connection members electrically connect the chip selection pads
to respective connection pads.
Inventors: |
NAH; Da Un; (Seoul, KR)
; KIM; Jae Myun; (Gyeonggi-do, KR) ; KIM; Tae
Hoon; (Gyeonggi-do, KR) ; JEONG; Jung Tae;
(Gyeonggi-do, KR) ; MIN; Bok Gyu; (Gyeonggi-do,
KR) ; KIM; Ki Bum; (Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
HYNIX SEMICONDUCTOR INC.; |
Gyeonggi-do |
|
KR |
|
|
Assignee: |
HYNIX SEMICONDUCTOR INC.
Gyeonggi-do
KR
|
Family ID: |
43973557 |
Appl. No.: |
13/633425 |
Filed: |
October 2, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12819279 |
Jun 21, 2010 |
8304879 |
|
|
13633425 |
|
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Current U.S.
Class: |
438/109 ;
257/E21.499 |
Current CPC
Class: |
H01L 2224/32145
20130101; H01L 2224/48227 20130101; H01L 23/481 20130101; H01L
24/48 20130101; H01L 25/0657 20130101; H01L 2924/00014 20130101;
H01L 2924/00014 20130101; H01L 2224/73265 20130101; H01L 2924/01033
20130101; H01L 2224/73265 20130101; H01L 2224/13025 20130101; H01L
2924/01075 20130101; H01L 2924/00014 20130101; H01L 2224/73265
20130101; H01L 2224/48108 20130101; H01L 2224/48091 20130101; H01L
24/73 20130101; H01L 2224/48091 20130101; H01L 2224/16145 20130101;
H01L 2224/73257 20130101; H01L 2225/06562 20130101; H01L 2224/32225
20130101; H01L 24/16 20130101; H01L 2924/207 20130101; H01L
2224/32145 20130101; H01L 2924/00014 20130101; H01L 2224/45015
20130101; H01L 2224/45099 20130101; H01L 2924/01013 20130101; H01L
2924/00012 20130101; H01L 2924/00012 20130101; H01L 2224/13099
20130101; H01L 2225/0651 20130101; H01L 2224/48227 20130101; H01L
2224/48227 20130101; H01L 2224/32225 20130101; H01L 2224/05554
20130101; H01L 2924/01047 20130101; H01L 2924/01029 20130101 |
Class at
Publication: |
438/109 ;
257/E21.499 |
International
Class: |
H01L 21/50 20060101
H01L021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 9, 2009 |
KR |
10-2009-0107588 |
Claims
1. A method for manufacturing a stack package, comprising the steps
of: preparing semiconductor chips, each semiconductor chip having
an upper surface and a lower surface facing away from the upper
surface and having at least one chip selection pad disposed
adjacent to at least one corner of each corresponding semiconductor
chip and having through-electrodes which pass through the upper
surface and the lower surface of each corresponding semiconductor
chip; forming a semiconductor chip module by stacking at least two
semiconductor chips together such that chip selection pads of the
semiconductor chips are exposed and so that the through-electrodes
of the stacked semiconductor chips are electrically connected
respectively to each other; and mounting the semiconductor chip
module onto a substrate which has connection pads.
2. The method according to claim 1, wherein the step of mounting
the semiconductor chip module onto the substrate comprises the step
of: bonding together, using conductive wires, chip selection pads
of the stacked semiconductor chips to respective connection pads of
the substrate.
3. The method according to claim 1, wherein the step of preparing
the semiconductor chips further comprises the step of: forming
additional through-electrodes which pass through the chip selection
pads; and wherein the step of mounting the semiconductor chip
module onto the substrate comprises the step of: electrically
connecting together, using conductive members, the additional
through-electrodes to extensions which extend from the connection
pads of the substrate to portions facing the additional
through-electrodes, in which of the conductive members have
spherical or column shapes.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to Korean patent
application number 10-2009-0107588 filed on Nov. 9, 2009, which is
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a stack package, and more
particularly, to a stack package which allows a certain
semiconductor chip to be easily selected among stacked
semiconductor chips and a method for manufacturing the same.
[0003] These days, semiconductor chips capable of storing and
processing huge amounts of data within a relatively short period of
time and semiconductor packages having the semiconductor chips have
been developed.
[0004] Recently, a stack package, in which a plurality of memory
chips are stacked on each other so as to increase data storage
capacity, has been developed in a variety of types. In addition,
another stack package, in which memory chips and system chips are
stacked together so as to not only increase data storage capacity
but also improve a data processing speed, has also been developed
in a variety of types.
[0005] However, in the case of the conventional stack packages,
since respective semiconductor chips are stacked in such a way as
to completely overlap with one another, it is difficult to select
respective semiconductor chips and apply and output data to and
from the selected semiconductor chips.
BRIEF SUMMARY OF THE INVENTION
[0006] Embodiments of the present invention are directed to a stack
package in which the stack structure of through-electrodes and
semiconductor chips is changed such that a certain semiconductor
chip can be easily selected among stacked semiconductor chips.
[0007] Also, embodiments of the present invention are directed to a
method for manufacturing the stack package.
[0008] In one embodiment of the present invention, a stack package
comprises a semiconductor chip module including at least two
semiconductor chips which have chip selection pads and
through-electrodes and are stacked such that the chip selection
pads are exposed and the through-electrodes are electrically
connected with one another; a substrate having the semiconductor
chip module mounted thereto and connection pads; and connection
members electrically connecting the respective chip selection pads
and the respective connection pads with each other.
[0009] The respective semiconductor chips may be disposed in a
state in which they are sequentially rotated by predetermined
angles about centers of the respective semiconductor chips in such
a way as to define the shape reminiscent of a spiral staircase so
that the chip selection pads of the respective stacked
semiconductor chips are exposed.
[0010] The chip selection pad may be disposed adjacent to any one
corner of four corners when each semiconductor chip has the shape
of a quadrangular plate.
[0011] The chip selection pads may be disposed adjacent to two
corners of four corners which are opposite in a diagonal direction
when each semiconductor chip has the shape of a quadrangular
plate.
[0012] The chip selection pads may be disposed adjacent to two
adjoining corners of four corners when each semiconductor chip has
the shape of a quadrangular plate.
[0013] The through-electrodes may be disposed in a symmetrical
matrix shaped pattern on each semiconductor chip.
[0014] The through-electrodes may have a shape possessing a
sectional area gradually decreasing from one ends thereof, on which
the chip selection pads are formed, to the other ends thereof,
which face away from the one ends.
[0015] The chip selection pad may have a first sectional area, and
the through-electrode may have a second sectional area that is
greater than the first sectional area.
[0016] The respective chip selection pads and the respective
connection pads corresponding to the chip selection pads may be
separated by the same distance.
[0017] The connection members may comprise bonding wires.
[0018] The stack package may further comprise additional
through-electrodes passing through the chip selection pads; and
extensions extending from the connection pads corresponding to the
additional through-electrodes to portions facing the additional
through-electrodes such that the additional-through electrodes and
the connection pads can be electrically connected with each other
by the connection members.
[0019] The connection members may comprise conductive members which
have a spherical shape or a column shape.
[0020] In another embodiment of the present invention, a method for
manufacturing a stack package comprises the steps of preparing
semiconductor chips, each semiconductor chip possessing an upper
surface and a lower surface facing away from the upper surface and
having at least one chip selection pad which is disposed adjacent
to at least one corner of corners of the semiconductor chip and
through-electrodes which pass through the upper surface and the
lower surface; forming a semiconductor chip module by stacking at
least two semiconductor chips such that chip selection pads of the
semiconductor chips are exposed and through-electrodes of the
semiconductor chips are electrically connected with each other; and
mounting the semiconductor chip module onto a substrate which has
connection pads.
[0021] The step of mounting the semiconductor chip module onto the
substrate may comprise the step of bonding the respective chip
selection pads of the respective stacked semiconductor chips and
the connection pads of the substrate, corresponding to the chip
selection pads, by means of conductive wires.
[0022] The step of preparing the semiconductor chips may further
comprise the step of forming additional through-electrodes which
pass through the chip selection pads; and the step of mounting the
semiconductor chip module onto the substrate may comprise the step
of electrically connecting the additional through-electrodes with
extensions which are formed to extend from the connection pads of
the substrate to portions facing the additional through-electrodes,
by means of conductive members which has a spherical shape or a
column shape.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a plan view illustrating a semiconductor chip of a
stack package in accordance with an embodiment of the present
invention.
[0024] FIG. 2 is a cross-sectional view taken along the line I-I'
of FIG. 1.
[0025] FIG. 3 is a plan view illustrating a semiconductor chip of a
stack package in accordance with another embodiment of the present
invention.
[0026] FIG. 4 is a plan view illustrating a semiconductor chip of a
stack package in accordance with another embodiment of the present
invention.
[0027] FIGS. 5 and 6 are a plan view and a cross-sectional view
illustrating the stack package in accordance with the embodiment of
the present invention.
[0028] FIG. 7 is a plan view illustrating the stack package in
accordance with another embodiment of the present invention.
[0029] FIG. 8 is a plan view illustrating a stack package in
accordance with another embodiment of the present invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0030] Hereafter, specific embodiments of the present invention
will be described in detail with reference to the accompanying
drawings.
[0031] It is to be understood herein that the drawings are not
necessarily to scale and in some instances proportions may have
been exaggerated in order to more clearly depict certain features
of the invention.
[0032] FIG. 1 is a plan view illustrating a semiconductor chip of a
stack package in accordance with an embodiment of the present
invention, and FIG. 2 is a cross-sectional view taken along the
line I-I' of FIG. 1.
[0033] Referring to FIGS. 1 and 2, a semiconductor chip 110
includes a chip selection pad 120 and through-electrodes 130.
[0034] The semiconductor chip 110 has, for example, the shape of a
quadrangular plate. The semiconductor chip 110 has an upper surface
111, a lower surface 112 which faces away from the upper surface
111, and side surfaces 113. The semiconductor chip 110 having the
shape of a quadrangular plate possesses four corners. The
semiconductor chip 110 has a circuit unit 114 which includes a data
storage section (not shown) for storing data and a data processing
section (not shown) for processing data.
[0035] The chip selection pad 120 is disposed on the upper surface
111 of the semiconductor chip 110. The chip selection pad 120 is
disposed on the upper surface 111 of the semiconductor chip 110
adjacent to any one of the four corners. The chip selection pad 120
is electrically connected with the circuit unit 114. The chip
selection pad 120 which is disposed adjacent to the corner on the
upper surface 111 of the semiconductor chip 110 has a first
sectional area.
[0036] The through-electrodes 130 pass through the upper surface
111 and the lower surface 112, facing away from the upper surface
111, of the semiconductor chip 110. In the embodiment, the
through-electrodes 130 may have a circular or elliptical cross
sectional shape when viewed from above. Unlike this, the
through-electrodes 130 may have a curved sectional shape. Examples
of materials which can be used to form the through-electrodes 130
include copper, copper alloy, and aluminum.
[0037] In the embodiment, one or more through-electrodes 130 can be
disposed through the semiconductor chip 110 in the form of a
symmetrical matrix shaped pattern. Each through-electrode 130 may
have a second sectional area that is greater than the first
sectional area of the chip selection pad 120.
[0038] While it is illustrated and described in the embodiment that
the through-electrodes 130 have a column-like shape, unlike this,
the through-electrodes 130 may have a shape which has a sectional
area gradually decreasing from one ends thereof to the other ends
thereof. For example, the through-electrodes 130 may have the shape
of a truncated cone.
[0039] FIG. 3 is a plan view illustrating a semiconductor chip of a
stack package in accordance with another embodiment of the present
invention. The semiconductor chip shown in FIG. 3 is substantially
the same as the semiconductor chip described above with reference
to FIG. 1, except the number and the disposal of chip selection
pads. Therefore, repeated description for the same component parts
will be omitted herein, and the same technical terms and the same
reference numerals will be used to refer to the same component
parts.
[0040] Referring to FIG. 3, a semiconductor chip 110 includes chip
selection pads 122 and 124, and through-electrodes 130.
[0041] In the embodiment, the chip selection pads 122 and 124
include a first chip selection pad 122 and a second chip selection
pad 124. For example, the first chip selection pad 122 is disposed
adjacent to the upper left corner in FIG. 3, and the second chip
selection pad 124 is disposed adjacent to the lower right corner in
FIG. 3, which is positioned in a diagonal direction with respect to
the first chip selection pad 122. Unlike this, it can be envisaged
that the first chip selection pad 122 is disposed adjacent to the
upper right corner in FIG. 3, and the second chip selection pad 124
is disposed adjacent to the lower left corner in FIG. 3, which is
positioned in a diagonal direction with respect to the first chip
selection pad 122.
[0042] FIG. 4 is a plan view illustrating a semiconductor chip of a
stack package in accordance with another embodiment of the present
invention. The semiconductor chip shown in FIG. 4 is substantially
the same as the semiconductor chip described above with reference
to FIG. 1, except the number and the disposal of chip selection
pads. Therefore, repeated description for the same component parts
will be omitted herein, and the same technical terms and the same
reference numerals will be used to refer to the same component
parts.
[0043] Referring to FIG. 4, a semiconductor chip 110 includes chip
selection pads 122 and 124 and through-electrodes 130.
[0044] In the embodiment, the chip selection pads 122 and 124
include a first chip selection pad 122 and a second chip selection
pad 124 which are respectively disposed adjacent to two adjoining
corners. For example, the first chip selection pad 122 is disposed
adjacent to the upper left corner in FIG. 4, and the second chip
selection pad 124 is disposed adjacent to the lower left corner in
FIG. 4, which adjoins the first chip selection pad 122. Unlike
this, it can be envisaged that the second chip selection pad 124
can be disposed adjacent to the upper right corner in FIG. 4.
[0045] FIGS. 5 and 6 are a plan view and a cross-sectional view
illustrating the stack package in accordance with the embodiment of
the present invention.
[0046] Referring to FIGS. 5 and 6, a stack package 500 includes a
semiconductor chip module 140, a substrate 150, and connection
members 160.
[0047] The semiconductor chip module 140 includes at least two, for
example, four, stacked semiconductor chips 110. Each of the stacked
semiconductor chips 110 includes a chip selection pad 120 and
through-electrodes 130.
[0048] The chip selection pad 120 is disposed adjacent to any one
of corners on the upper surface of each semiconductor chip 110. The
respective semiconductor chips 110 are stacked in such a manner
that the chip selection pads 120 are exposed. The
through-electrodes 130 which pass through the respective
semiconductor chips 110 are electrically connected with one
another.
[0049] In the embodiment, in order to ensure that the chip
selection pads 120 are exposed from the four stacked semiconductor
chips 110, the respective semiconductor chips 110 are sequentially
rotated by predetermined angles about the rotation centers of the
respective semiconductor chips 110. Due to this fact, the stacked
semiconductor chips 110 are disposed in such a way as to define the
substantial shape of a spiral staircase when viewed from the
top.
[0050] The semiconductor chip module 140, which has the
semiconductor chips 110 disposed in the substantial shape of a
spiral staircase and the chip selection pads 120 exposed from the
respective semiconductor chips 110, is mounted to the upper surface
of the substrate 150.
[0051] Connection pads 152 are formed on the upper surface of the
substrate 150. In the embodiment, the connection pads 152 are
disposed on the upper surface of the substrate 150, for example, in
a number corresponding to the number of the chip selection pads
120. In the embodiment, it is preferred that the chip selection
pads 120 and the connection pads 152 respectively corresponding to
the chip selection pads 120 be separated by the same distance. In
the embodiment, the connection pads 152 can be disposed on the
substrate 150, for example, in the form of a symmetrical matrix
shaped pattern.
[0052] The connection members 160 electrically connect the chip
selection pads 120 disposed on the respective semiconductor chips
110 and the connection pads 152 of the substrate 150. In the
embodiment, the connection members 160 may comprise, for example,
bonding wires.
[0053] FIG. 7 is a plan view illustrating the stack package in
accordance with another embodiment of the present invention.
Repeated description for the same component parts as those shown in
FIG. 5 will be omitted herein, and the same technical terms and the
same reference numerals will be used to refer to the same component
parts.
[0054] Referring to FIG. 7, a semiconductor package 700 includes a
semiconductor chip module 140, a substrate 150, and connection
members 160.
[0055] The semiconductor chip module 140 includes at least two, for
example, four, stacked semiconductor chips 110. Each of the stacked
semiconductor chips 110 includes first and second chip selection
pads 122 and 124, and through-electrodes 130.
[0056] The first chip selection pad 122 is disposed adjacent to any
one of the corners on the upper surface of each semiconductor chip
110, and the second chip selection pad 124 is disposed adjacent to
another corner of the corners on the upper surface of each
semiconductor chip 110, which is positioned in a diagonal direction
with respect to the first chip selection pad 122.
[0057] The respective semiconductor chips 110 having the first and
second chip selection pads 122 and 124 are stacked in such a manner
that the first and second chip selection pads 122 and 124 are
exposed. The through-electrodes 130 which pass through the
respective semiconductor chips 110 are also electrically connected
to one another.
[0058] In the embodiment, in order to ensure that the first and
second chip selection pads 122 and 124 are exposed from the four
stacked semiconductor chips 110, the respective semiconductor chips
110 are sequentially rotated by predetermined angles about the
rotation centers of the respective semiconductor chips 110. Due to
this fact, the stacked semiconductor chips 110 are disposed in such
a way as to define the substantial shape of a spiral staircase when
viewed from the top.
[0059] The semiconductor chip module 140, which has the
semiconductor chips 110 disposed in the substantial shape of a
spiral staircase and the first and second chip selection pads 122
and 124 exposed from the respective semiconductor chips 110, is
mounted to the upper surface of the substrate 150. First and second
connection pads 154 and 156 are formed on the upper surface of the
substrate 150. In the embodiment, the first and second connection
pads 154 and 156 are disposed on the upper surface of the substrate
150, for example, adjacent to the first and second chip selection
pads 122 and 124.
[0060] The connection members 160 electrically connect the first
and second chip selection pads 122 and 124 disposed on the
respective semiconductor chips 110 and the first and second
connection pads 154 and 156 of the substrate 150. In the
embodiment, the connection members 160 may comprise, for example,
bonding wires.
[0061] While it was described above that one or two chip selection
pads are formed adjacent to one or two corners of each
semiconductor chip 110, unlike this, it can be envisaged that chip
selection pads can be formed adjacent to respective corners on the
upper surface of each semiconductor chip 110 and through this, an
increased number of semiconductor chips 110 can be stacked on the
substrate 150.
[0062] FIG. 8 is a plan view illustrating a stack package in
accordance with another embodiment of the present invention. The
stack package shown in FIG. 8 is substantially the same as the
stack package described above with reference to FIG. 5, except
additional through-electrodes of semiconductor chips, connection
pads and connection members. Therefore, repeated description for
the same component parts as those shown in FIG. 5 will be omitted
herein, and the same technical terms and the same reference
numerals will be used to refer to the same component parts.
[0063] Referring to FIG. 8, a stack package 800 includes a
semiconductor chip module 140, a substrate 150, and connection
members 170.
[0064] The semiconductor chip module 140 includes at least two, for
example, four, stacked semiconductor chips 110. Each of the stacked
semiconductor chips 110 includes a chip selection pad 120,
through-electrodes 130, and an additional through-electrode
125.
[0065] The chip selection pad 120 is disposed adjacent to any one
of corners on the upper surface of each semiconductor chip 110. The
respective semiconductor chips 110 are stacked in such a manner
that the chip selection pads 120 are exposed. The
through-electrodes 130 pass through the respective semiconductor
chips 110 and are electrically connected with one another. The
additional through-electrode 125 passes through the chip selection
pad 120 and a portion of each semiconductor chip 110 which
corresponds to the chip selection pad 120.
[0066] In the embodiment, in order to ensure that the chip
selection pads 120 are exposed from the four stacked semiconductor
chips 110, the respective semiconductor chips 110 are sequentially
rotated by predetermined angles about the rotation centers of the
respective semiconductor chips 110. Due to this fact, the stacked
semiconductor chips 110 are disposed in such a way as to define the
substantial shape of a spiral staircase when viewed from the
top.
[0067] The semiconductor chip module 140, which has the
semiconductor chips 110 disposed in the substantial shape of a
spiral staircase and the chip selection pads 120 exposed from the
respective semiconductor chips 110, is mounted to the upper surface
of the substrate 150.
[0068] Connection pads 152 are formed on the upper surface of the
substrate 150. In the embodiment, the connection pads 152 are
disposed on the upper surface of the substrate 150, for example, in
a number corresponding to the number of the chip selection pads
120.
[0069] The respective connection pads 152 have extensions 158 which
extend to portions facing the additional through-electrodes 125 of
the respective chip selection pads 120.
[0070] The connection members 170 are interposed between the
additional through-electrodes 125 disposed in respective
semiconductor chips 110 and the extensions 158 facing the
additional through-electrodes 125. The additional
through-electrodes 125 and the connection pads 152 are electrically
connected with each other by the connection members 170. In the
embodiment, the connection members 170 may be conductive members
having, for example, a spherical shape or a column shape.
[0071] While, not shown in a drawing, the additional
through-electrodes 125 may be formed to pass through the portion of
the semiconductor chips 110 which are away from the chip selection
pads 120. This case, the connection members 170 may be a conductive
pattern, that is, re-distribution layer formed on the upper surface
111 of the semiconductor chips 110 to connect between the chip
selection pad and the additional through-electrode 125.
[0072] Hereinafter, a method for manufacturing a stack package in
accordance with another embodiment of the present invention will be
described with reference to the attached drawings.
[0073] First, referring to FIGS. 1 and 2, the semiconductor chip
110 including the chip selection pad 120 and the through-electrodes
130 is manufactured through a semiconductor chip manufacturing
process and a through-electrode forming process well known in the
art.
[0074] The semiconductor chip 110 has the shape of a quadrangular
plate. The semiconductor chip 110 has the circuit unit 114 which
includes a data storage section (not shown) for storing data and a
data processing section (not shown) for processing data.
[0075] The chip selection pad 120 is disposed on the upper surface
111 of the semiconductor chip 110. The chip selection pad 120 is
disposed on the upper surface 111 of the semiconductor chip 110
adjacent to any one of the four corners. The chip selection pad 120
is electrically connected with the circuit unit 114.
[0076] The through-electrodes 130 pass through the upper surface
111 and the lower surface 112, facing away from the upper surface
111, of the semiconductor chip 110. In the embodiment, the
through-electrodes 130 may be formed to have a circular or
elliptical cross sectional shape when viewed from above. Unlike
this, the through-electrodes 130 may be formed to have a curved
sectional shape. Examples of a material which can be used to form
the through-electrodes 130 include copper, a copper alloy, and
aluminum.
[0077] After the semiconductor chip 110 including the chip
selection pad 120 and the through-electrodes 130 is manufactured,
as shown in FIG. 5, at least two, for example, four, semiconductor
chips 110 are stacked in the shape of a spiral staircase in such a
manner that chip selection pads 120 are exposed and the
through-electrodes 130 are electrically connected with one another.
In this way, the semiconductor chip module 140 is prepared.
[0078] After the semiconductor chip module 140 is prepared, the
semiconductor chip module 140 is mounted onto the substrate 150
which is formed with the connection pads 152.
[0079] After the semiconductor chip module 140 is mounted onto the
substrate 150, the chip selection pads 120 of the respective
semiconductor chips 110 and the connection pads 152 of the
substrate 150 are electrically connected with each other by means
of the connection members 160 such as conductive wires, by which
the stack package 500 is manufactured.
[0080] It was illustrated and described in the embodiment that the
chip selection pads 120 of the semiconductor chips 110 and the
connection pads 152 of the substrate 150 are electrically connected
with each other by means of the conductive wires. However, as shown
in FIG. 8, it can be contemplated that the additional
through-electrodes 125 are formed in the semiconductor chips 110 to
pass through the chip selection pads 120, the extensions 156 are
formed on the substrate 150 to extend from the connection pads 152
to the positions of the additional through-electrodes 125, and the
connection members 160 are interposed between the additional
through-electrodes 125 and the extensions 156 such that the chip
selection pads 120 of the semiconductor chips 110 and the
connection pads 152 of the substrate 150 are electrically connected
with each other by means of the additional through-electrodes 125
and the extensions 156.
[0081] As is apparent from the above description, the stack package
according to the present invention provides advantages in that, in
the state in which a plurality of semiconductor chips are stacked,
a certain semiconductor chip can be easily selected among the
stacked semiconductor chips.
[0082] Although specific embodiments of the present invention have
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
the spirit of the invention as disclosed in the accompanying
claims.
* * * * *