U.S. patent application number 13/200335 was filed with the patent office on 2013-01-10 for semiconductor package and method of manufacturing the same.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Myeong Woo Han, Jung Aun Lee, Chul Gyun Park, Do Jae Yoo, Jung Ho Yoon.
Application Number | 20130009320 13/200335 |
Document ID | / |
Family ID | 47438172 |
Filed Date | 2013-01-10 |
United States Patent
Application |
20130009320 |
Kind Code |
A1 |
Yoo; Do Jae ; et
al. |
January 10, 2013 |
Semiconductor package and method of manufacturing the same
Abstract
There are provided a semiconductor package including an antenna
formed integrally therewith, and a method of manufacturing the
same. The semiconductor package includes: a semiconductor chip; a
sealing part sealing the semiconductor chip; a substrate part
formed on at least one surface of the sealing part; and an antenna
part formed on the sealing part or the substrate part and
electrically connected to the semiconductor chip.
Inventors: |
Yoo; Do Jae; (Suwon, KR)
; Yoon; Jung Ho; (Anyang, KR) ; Park; Chul
Gyun; (Yongin, KR) ; Han; Myeong Woo;
(Hwaseong, KR) ; Lee; Jung Aun; (Suwon,
KR) |
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
47438172 |
Appl. No.: |
13/200335 |
Filed: |
September 23, 2011 |
Current U.S.
Class: |
257/774 ;
257/E21.502; 257/E23.011; 438/107 |
Current CPC
Class: |
H01L 2224/32145
20130101; H01L 23/5226 20130101; H01L 21/4857 20130101; H01L
2224/0401 20130101; H01L 25/0657 20130101; H01L 23/49838 20130101;
H01L 2924/181 20130101; H01L 2924/01029 20130101; H01L 2224/04105
20130101; H01L 2224/16225 20130101; H01L 2224/48227 20130101; H01L
2224/97 20130101; H01L 2924/181 20130101; H01L 25/16 20130101; H01L
23/66 20130101; H01L 2224/97 20130101; H01L 21/78 20130101; H01L
23/49827 20130101; H01L 2924/12042 20130101; H01L 2924/3011
20130101; H01L 2924/15787 20130101; H01L 24/19 20130101; H01L
21/568 20130101; H01L 21/561 20130101; H01L 24/96 20130101; H01L
23/3142 20130101; H01L 2223/6677 20130101; H05K 2203/061 20130101;
H01L 21/56 20130101; H01L 2223/6616 20130101; H01L 2223/6683
20130101; H01L 2924/12042 20130101; H01L 23/5389 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2224/81 20130101;
H01L 2924/00 20130101; H01L 2224/48227 20130101; H01L 2224/48227
20130101; H01L 2924/00 20130101; H01L 21/4853 20130101; H01L 21/486
20130101; H05K 1/185 20130101; H01L 2224/73265 20130101; H01L 24/97
20130101; H01L 2924/15787 20130101; H01L 23/49822 20130101; H01L
2224/73265 20130101; H01L 2224/73265 20130101; H01L 2924/3011
20130101; H01L 24/73 20130101; H01L 2224/97 20130101; H01L 21/565
20130101; H01L 2224/32145 20130101; H01L 2224/97 20130101; H01L
2224/32145 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/73265 20130101; H01L 2924/00012 20130101 |
Class at
Publication: |
257/774 ;
438/107; 257/E23.011; 257/E21.502 |
International
Class: |
H01L 23/48 20060101
H01L023/48; H01L 21/56 20060101 H01L021/56 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 7, 2011 |
KR |
10-2011-0067437 |
Claims
1. A semiconductor package comprising: a semiconductor chip; a
sealing part sealing the semiconductor chip; a substrate part
formed on at least one surface of the sealing part; and an antenna
part formed on the sealing part or the substrate part and
electrically connected to the semiconductor chip.
2. The semiconductor package of claim 1, further comprising a via
connection part penetrating through the sealing part, wherein the
antenna part and the semiconductor chip are electrically connected
to each other through the via connection part.
3. The semiconductor package of claim 1, wherein the substrate part
includes: an upper substrate formed on an upper surface of the
sealing part; and a lower substrate formed on a lower surface of
the sealing part.
4. The semiconductor package of claim 3, wherein the antenna part
is formed on an outer surface of the upper substrate.
5. The semiconductor package of claim 4, wherein the upper
substrate is a multi-layer substrate, and the antenna part includes
a plurality of radiators formed on several layers of the upper
substrate.
6. The semiconductor package of claim 1, wherein the antenna part
is formed on an outer surface of the sealing part.
7. The semiconductor package of claim 6, wherein the antenna part
is formed in a groove formed in the outer surface of the sealing
part.
8. The semiconductor package of claim 1, wherein the substrate part
has fine circuit patterns formed in an inner portion thereof
through a semiconductor manufacturing process.
9. The semiconductor package of claim 1, wherein the semiconductor
chip transceives a high frequency in a millimeter wave band through
the antenna part.
10. A method of manufacturing a semiconductor package, the method
comprising: disposing a plurality of semiconductor chips; forming a
sealing part sealing the plurality of semiconductor chips; forming
a substrate part on at least one surface of the sealing part; and
forming an antenna part on the sealing part or the substrate
part.
11. The method of claim 10, wherein the disposing of the plurality
of semiconductor chips includes arranging semiconductor chips
sorted into good products on a carrier.
12. The method of claim 11, wherein the disposing of the plurality
of semiconductor chips includes attaching the semiconductor chips
to an adhesive layer formed on the carrier.
13. The method of claim 10, wherein the forming of the sealing part
includes forming the sealing part using an epoxy mold compound
(EMC).
14. The method of claim 10, further comprising, after the forming
of the sealing part, forming a via connection part penetrating
through the sealing part.
15. The method of claim 14, wherein the forming of the antenna part
includes electrically connecting the antenna part and the
semiconductor chips through the via connection part.
16. The method of claim 10, wherein the forming of the substrate
part includes forming a multi-layer substrate part on each of upper
and lower surfaces of the sealing part.
17. The method of claim 16, wherein the forming of the antenna part
includes forming a plurality of radiators on several layers of the
substrate part.
18. The method of claim 10, wherein the forming of the antenna part
includes forming a groove in an outer surface of the sealing part
and forming the antenna part therein.
19. The method of claim 10, wherein the forming of the substrate
part includes repeatedly forming fine circuit patterns and
insulating layers through a semiconductor manufacturing process.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the priority of Korean Patent
Application No. 10-2011-0067437 filed on Jul. 7, 2011, in the
Korean Intellectual Property Office, the disclosure of which is
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor package and
a method of manufacturing the same, and more particularly, to a
semiconductor package including an antenna formed integrally
therewith, and a method of manufacturing the same.
[0004] 2. Description of the Related Art
[0005] As a frequency resource for a next generation information
communication service, a frequency in the millimeter wave band, a
super high frequency band of 30 GHz or more, has been actively
studied.
[0006] This frequency in the millimeter wave band has advantages in
that a large amount of information may be transferred at high speed
using wideband characteristics and that the frequency may be
re-used, that is, a band having the same frequency may be used
without interference in an adjacent geographical area due to
significant electrical wave attenuation in the air. Therefore, many
researchers have been interested in the frequency in the millimeter
wave band.
[0007] As a result, the development of an information communication
service and system using the frequency in the millimeter wave as
well as research into, and development of, various components
required for the information communication service and system have
been conducted.
[0008] In this millimeter wave band, an electrical connection
distance between an antenna and a semiconductor chip is very
important. That is, when a distance between the antenna and the
semiconductor chip increases, loss increases. Therefore, an antenna
in the millimeter wave band (particularly, the 60 GHz band) may be
electrically connected to the semiconductor chip to be close
thereto.
[0009] To this end, according to the related art, an antenna is
disposed at a position significantly adjacent to a semiconductor
package in which a semiconductor chip is embedded, and the antenna
and the semiconductor package are electrically connected to each
other at the shortest possible distance.
[0010] In the case of the related art, after the semiconductor
package and the antenna are separately manufactured, they are
mounted on a substrate and electrical connections are made.
Therefore, a manufacturing process is complicated.
[0011] Accordingly, the demand for a structure in which an antenna
and a semiconductor package are disposed at a closer distance to
one other has increased. In addition, the necessity for a
manufacturing method capable of simplifying a process has
increased.
SUMMARY OF THE INVENTION
[0012] An aspect of the present invention provides a semiconductor
package capable of being easily manufactured while minimizing an
electrical connection distance between an antenna and a
semiconductor chip.
[0013] Another aspect of the present invention provides a method of
manufacturing a semiconductor package through a simplified
semiconductor manufacturing process.
[0014] Another aspect of the present invention provides a method of
manufacturing a semiconductor package capable of producing a
compact and thin semiconductor package through a semiconductor
manufacturing process.
[0015] According to an aspect of the present invention, there is
provided a semiconductor package including: a semiconductor chip; a
sealing part sealing the semiconductor chip; a substrate part
formed on at least one surface of the sealing part; and an antenna
part formed on the sealing part or the substrate part and
electrically connected to the semiconductor chip.
[0016] The semiconductor package may further include a via
connection part penetrating through the sealing part, and the
antenna part and the semiconductor chip may be electrically
connected to each other through the via connection part.
[0017] The substrate part may include an upper substrate formed on
an upper surface of the sealing part, and a lower substrate formed
on a lower surface of the sealing part.
[0018] The antenna part may be formed on an outer surface of the
upper substrate.
[0019] The upper substrate may be a multi-layer substrate, and the
antenna part may include a plurality of radiators formed on several
layers of the upper substrate.
[0020] The antenna part may be formed on an outer surface of the
sealing part.
[0021] The antenna part may be formed in a groove formed in the
outer surface of the sealing part.
[0022] The substrate part may have fine circuit patterns formed in
an inner portion thereof through a semiconductor manufacturing
process.
[0023] The semiconductor chip may transceive a high frequency in a
millimeter wave band through the antenna part.
[0024] According to another aspect of the present invention, there
is provided a method of manufacturing a semiconductor package, the
method including: disposing a plurality of semiconductor chips;
forming a sealing part sealing the plurality of semiconductor
chips; forming a substrate part on at least one surface of the
sealing part; and forming an antenna part on the sealing part or
the substrate part.
[0025] The disposing of the plurality of semiconductor chips may
include arranging semiconductor chips sorted into good products on
a carrier.
[0026] The disposing of the plurality of semiconductor chips may
include attaching the semiconductor chips to an adhesive layer
formed on the carrier.
[0027] The forming of the sealing part may include forming the
sealing part using an epoxy mold compound (EMC).
[0028] The method may further include, after the forming of the
sealing part, forming a via connection part penetrating through the
sealing part.
[0029] The forming of the antenna part may include electrically
connecting the antenna part and the semiconductor chips through the
via connection part.
[0030] The forming of the substrate part may include forming a
multi-layer substrate part on each of upper and lower surfaces of
the sealing part.
[0031] The forming of the antenna part may include forming a
plurality of radiators on several layers of the substrate part.
[0032] The forming of the antenna part may include forming a groove
in an outer surface of the sealing part and forming the antenna
part therein.
[0033] The forming of the substrate part may include repeatedly
forming fine circuit patterns and insulating layers through a
semiconductor manufacturing process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The above and other aspects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0035] FIG. 1 is a perspective view schematically showing a
semiconductor package according to an embodiment of the present
invention;
[0036] FIG. 2 is a cross-sectional view taken along line A-A' of
the semiconductor package shown in FIG. 1;
[0037] FIGS. 3A through 3I are views describing a method of
manufacturing a semiconductor package according to an embodiment of
the present invention;
[0038] FIG. 4 is a flowchart showing a method of manufacturing a
semiconductor package according to an embodiment of the present
invention; and
[0039] FIGS. 5 and 6 are cross-sectional views schematically
showing a semiconductor package according to other embodiments of
the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0040] Prior to a detailed description of the present invention,
the terms or words, which are used in the specification and claims
to be described below, should not be construed as having typical or
dictionary meanings. The terms or words should be construed in
conformity with the technical idea of the present invention on the
basis of the principle that the inventor(s) can appropriately
define terms in order to describe his or her invention in the best
way. Embodiments described in the specification and structures
illustrated in drawings are merely exemplary embodiments of the
present invention. Thus, it is intended that the present invention
covers the modifications and variations of this invention, provided
they fall within the scope of their equivalents at the time of
filing this application.
[0041] Exemplary embodiments of the present invention will be
described in detail with reference to the accompanying drawings.
The same reference numerals will be used throughout to designate
the same or like elements in the accompanying drawings. Moreover,
detailed descriptions related to well-known functions or
configurations will be ruled out in order not to unnecessarily
obscure subject matters of the present invention.
[0042] In the drawings, the shapes and dimensions of some elements
may be exaggerated, omitted or schematically illustrated. Also, the
size of each element does not entirely reflect an actual size.
[0043] Hereinafter, embodiments of the present invention will be
described in detail with reference to the accompanying
drawings.
[0044] FIG. 1 is a perspective view schematically showing a
semiconductor package according to an embodiment of the present
invention, and FIG. 2 is a cross-sectional view taken along line
A-A' of the semiconductor package shown in FIG. 1.
[0045] As shown in FIGS. 1 and 2, a semiconductor package 100
according to the present embodiment includes a semiconductor chip
10, a sealing part 20 sealing the semiconductor chip 10, a
substrate part 30 disposed on both surfaces of the sealing part 20,
and an antenna part 40.
[0046] The semiconductor chip 10 includes a plurality of connection
pads 12 for connecting to the outside and is electrically connected
to the substrate part 30 and the antenna part 40 (to be described
below) through the connection pads 12. The connection pads 12 may
have the form of a solder bump. However, the present invention is
not limited thereto but may be variously applied. For example, the
connection pads 12 may have the form of a pad for wire bonding.
[0047] This semiconductor chip 10 may perform wireless
communications with the outside through the antenna part 40.
[0048] The sealing part 20 encloses the entire semiconductor chip
10 such that the semiconductor chip 10 is embedded therein, thereby
sealing the semiconductor chip 10. That is, the sealing part 20
encloses an outer portion of the semiconductor chip 10 and fixes
the semiconductor chip 10 to the substrate part 30, thereby
securely protecting the semiconductor chip 10 from external
impacts.
[0049] As a method of forming the sealing part 20, a molding method
may be used. In this case, an epoxy mold compound (EMC) may be used
as a material of the sealing part 20. However, the present
invention is not limited thereto. That is, various methods such as
a printing method, a spin coating method, a jetting method, and the
like, may be used for forming the sealing part 20 as necessary.
[0050] The substrate part 30 may be formed on at least one surface
of the sealing part 20 having the semiconductor chip 10 embedded
therein. The present embodiment describes a case in which the
substrate part 30 includes each of upper and lower substrates 30a
and 30b formed on both surfaces (upper and lower surfaces) of the
sealing part 20 by way of example. As the substrate part 30,
various kinds of substrates (for example, a silicon substrate, a
ceramic substrate, a printed circuit board (PCB), a flexible
substrate, a circuit pattern layer by a semiconductor circuit
process, and the like) known in the art may be used.
[0051] Electrode patterns 32 electrically connected to the
semiconductor chip 10 and circuit patterns 36 electrically
connecting the electrode patterns 32 to each other may be formed on
one surface of the substrate part 30, that is, a bonding surface
between the substrate part 30 and the sealing part 20.
[0052] In addition, the substrate part 30 according to the present
embodiment may be a multi-layer substrate configured of a plurality
of layers. The circuit patterns 36 for forming an electrical
connection may be formed between the respective layers. The
substrate part 30 may have external electrodes 38 formed on an
outer surface thereof, and the external electrodes 38 electrically
connect the semiconductor package 100 to the outside.
[0053] In addition, the substrate part 30 according to the present
embodiment may include the external electrodes 38, the electrode
patterns 32 and conductive vias 34 electrically connecting the
circuit patterns 36 to each other.
[0054] Here, the substrate part 30 according to the present
embodiment may be formed through a semiconductor manufacturing
process. Therefore, the external electrode 38, the electrode
pattern 32, the circuit pattern 36, the conductive via 34, and the
like, formed in the substrate part 30 may be formed as fine circuit
patterns by the semiconductor manufacturing process.
[0055] The antenna part 40 is formed by disposing a radiator on the
outer surface of the substrate part 30, that is, a top portion. The
form of the radiator may be varied, having a liner, polygonal,
circular, or other shape, and may be a dipole or monopole form.
[0056] The antenna part 40 according to the present embodiment may
be formed to have a single radiator or be formed by complexly
disposing a plurality of radiators on several layers as necessary.
FIG. 2 shows a case in which the radiators are formed in parallel
with each other on the outer surface of the substrate part 30 and
an inner portion of the substrate part 30.
[0057] In addition, the antenna part 40 may be electrically
connected to the semiconductor chip 10 through the circuit pattern
36, the via 34, a via connection part 25, and the like.
[0058] Meanwhile, although the present embodiment describes a case
in which the antenna part 40 is formed in the upper substrate 30a
by way of example, the present invention is not limited thereto.
That is, the antenna part 40 may also be disposed on an outer
surface of the lower substrate 30b, that is, a bottom surface of
the lower substrate 30b in order to minimize an electrical
connection distance between the antenna part 40 and the
semiconductor chip 10.
[0059] In the case of the semiconductor package 100 configured as
described above, the antenna part 40 is formed on the outer surface
of the substrate part 30 and an electrical connection distance
between the antenna part 40 and the semiconductor chip 10 is
significantly short, whereby radiation characteristics and
electrical loss of the antenna part 40 may be improved.
[0060] Next, a method of manufacturing a semiconductor package
according to an embodiment of the present invention will be
described.
[0061] FIGS. 3A through 3I are views describing a method of
manufacturing a semiconductor package according to an embodiment of
the present invention; and FIG. 4 is a flowchart showing a method
of manufacturing a semiconductor package according to an embodiment
of the present invention.
[0062] With reference to FIGS. 3A through 4, a method of
manufacturing a semiconductor package according to an embodiment of
the present invention in initiated in preparing the semiconductor
chip 10 in operation S10.
[0063] A plurality of semiconductor chips formed on a wafer may be
cut into individual chips through a known semiconductor
manufacturing process and then the individual chips may be sorted
into a good product or a bad product.
[0064] Then, as shown in FIGS. 3A and 3B, the plurality of
semiconductor chips 10 are disposed in operation S11. Here, FIG. 3B
shows a cross-sectional view taken along line B-B' of FIG. 3A.
[0065] The semiconductor chips 10 may be disposed such that they
are uniformly arranged on a carrier 60 having various shapes.
[0066] The carrier 60 includes an adhesive layer 70 formed on one
surface thereof, and the semiconductor chips 10 are mounted on the
adhesive layer 70. Here, the semiconductor chips 10 are mounted
such that active areas thereof having the connection pads 12 formed
therein may be attached to the adhesive layer 70 of the carrier
60.
[0067] The adhesive layer 70 may have adhesion changed by light or
heat. As an example, adhesive tape may be used. However, the
present invention is not limited thereto but may be variously
applied. The adhesive layer 70 may be formed by applying an
adhesive resin, or the like, to one surface of the carrier 60.
[0068] The carrier 60 may be formed of a flat, hard wafer disk.
However, this configuration in which the carrier 60 uses the wafer
was deduced because the method of manufacturing the semiconductor
package 100 according to the present embodiment utilizes a
semiconductor manufacturing process using a wafer. Therefore, the
carrier 60 according to the present embodiment is not limited to
having a circular shape but may be variously shaped according to
embodiments of the semiconductor manufacturing process. Although
FIG. 3A shows a good chip carrier having the circular shape, the
carrier 60 may have various forms including a rectangular
substrate.
[0069] After the plurality of semiconductor chips 10 are mounted on
the carrier 60, the sealing part 20 is formed in operation S12 as
shown in FIG. 3C.
[0070] The sealing part 20 according to the present embodiment
covers the entire carrier 60. That is, the sealing part 20 fills
spaces between the individual semiconductor chips 10. Therefore,
when the forming of the sealing part 20 is completed, all of the
semiconductor chips 10 are formed integrally with each other by the
sealing part 20.
[0071] After the carrier 60 on which the semiconductor chips 10 are
mounted is disposed within a mold (not shown), the sealing part 20
according to the present embodiment may be formed by injecting a
mold resin into the mold and hardening it.
[0072] Next, as shown in FIG. 3D, one surface of the sealing part
20 is ground using a grinder 50 in operation S13. Therefore, an
unnecessary portion of the sealing part 20 is removed, whereby the
thickness of the semiconductor package 100 may be reduced.
[0073] In addition, in the semiconductor package 100 according to
the present embodiment, a distance between the antenna part 40 and
the semiconductor chips 10, permittivity according to the distance,
and the like, may be adjusted through the grinding of the sealing
part 20. Therefore, characteristics of the antenna part 40, that
is, signal matching characteristics may be optimally adjusted
through this operation S13.
[0074] Accordingly, the unnecessary portion of the sealing part 20
may be removed corresponding to optimal signal matching.
[0075] Meanwhile, when the adjustment of a thickness of the sealing
part 20 or signal matching is not required to be performed, this
operation may be omitted.
[0076] Thereafter, as shown in FIG. 3E, the removing of the
adhesive layer 70 is performed in operation S14. This may be easily
undertaken by applying heat to the adhesive layer 70 or irradiating
the adhesive layer 70 with light to weaken the adhesion thereof.
The adhesive layer 70, attached to the other surface of the sealing
part 20, is removed, such that the connection pads 12 of the
semiconductor chips 10 that have been attached to the adhesive
layer 70 are exposed to the outside on the other surface of the
sealing part 20.
[0077] Meanwhile, a lower surface of the sealing part 20 in which
the adhesive layer is removed may be continuously supported by the
carrier 60. However, hereinafter, for convenience of description,
the carrier 60 may be omitted in the drawings.
[0078] Then, at least one substrate part 30 may be formed on any
one surface of the sealing part 20. The present embodiment
describes a case in which the lower substrate 30b is first formed
in operation S15 by way of example as shown in FIG. 3F.
[0079] The sealing part 20 is disposed in a form in which upper and
lower surfaces thereof are inverted. That is, the sealing part 20
is mounted on the carrier such that the connection pad 12 of the
semiconductor chip 10 is exposed upwardly.
[0080] The lower substrate 30b may be formed by repeatedly
performing a process of forming the circuit patterns 36, the
electrode patterns 32, or the like, on the upper surface of the
sealing part 20, on which the connection pad 12 is exposed, and
forming an insulating layer 31 thereon again. At this time, the
electrode patterns 32 or the circuit patterns 36 may be formed to
be electrically connected to the connection pads 12 exposed on the
sealing part 20.
[0081] In addition, the vias 34 penetrating through the insulating
layers 31 may be formed as necessary to thereby electrically
connect the respective insulating layers 31, and the external
electrodes 38 for connection to the outside may be formed on an
outer surface of the insulating layer 31.
[0082] Here, as a method of forming the circuit pattern 36, the
insulating layer 31, the via 34, or the like, a semiconductor
manufacturing process known in the art, or the like, may be used.
Therefore, a detailed description thereof will be omitted.
[0083] When the substrate part 30 is formed using the semiconductor
manufacturing process as in the present embodiment, fine circuit
patterns may be formed on the substrate part 30. In addition, the
substrate part may have a significantly reduced thickness as
compared to a general printed circuit board (PCB). Therefore, the
semiconductor chip 100 according to the present embodiment may be a
chip scale package (CSP).
[0084] After the lower substrate 30b is formed, the via connection
part 25 penetrating through the sealing part 20 is formed in
operation S16 as shown in FIG. 3G. At this time, the via connection
part 25 is formed at a position corresponding to that of the
circuit pattern 36 formed on the lower substrate 30b. Therefore,
the via connection part 25 may be electrically connected to the
semiconductor chip 10 through the circuit pattern 36.
[0085] The via connection part 25 may be formed by drilling a
through hole 23 in the sealing part 20, so that the circuit pattern
36 of the lower substrate 30b is exposed, filling the through hole
23 with a conductive material (for example, copper, solder, or the
like) and hardening the conductive material. The through hole 23
may be formed using a method such as laser drilling. However, the
through hole 23 is not limited to being formed using laser
drilling, but may also be formed using other methods as
required.
[0086] Meanwhile, the present embodiment describes a case in which
the via connection part 25 is formed after the forming of the lower
substrate 30b by way of example. However, the present invention is
not limited thereto. That is, after the sealing part 20 is formed
in operation S12 or S13, the via connection part 25 is first formed
in the sealing part 20 before the forming of the lower substrate
30b.
[0087] Next, as shown in FIG. 3H, the upper substrate 30a is formed
on one surface of the sealing part 20 in operation S17. The upper
substrate 30a may be formed to have a shape similar to that of the
above-mentioned lower substrate 30b through the same process as
that of forming the lower substrate 30b.
[0088] First, the sealing part 20 is reinverted such that the
connection pad 12 of the semiconductor chip 10 is directed
downwardly. Then, the upper substrate 30a may be formed by
repeatedly performing a process of forming the circuit patterns 36,
the electrode patterns 32, or the like, on the upper surface of the
sealing part 20 and forming the insulating layer 31 thereon
again.
[0089] In this operation, the antenna part 40 may be formed on the
upper substrate 30a.
[0090] The antenna part 40 may have the form of the circuit pattern
36 in a process of forming the circuit pattern 36 of the upper
substrate 30a. In addition, the antenna part 40 may be electrically
connected to the semiconductor chip 10 through the via 34 formed in
the upper substrate 30a, the via connection part 25 formed in the
sealing part 20, or the like.
[0091] Since the antenna part 40 as well as the substrate part 30
may be formed during the process of forming the substrate part 30
as described above, a manufacturing process may be facilitated as
compared to the case of the related art in which the antenna part
40 is separately manufactured and then coupled to the substrate
part 30.
[0092] Further, in the antenna part 40 according to the present
embodiment, at least one radiator may have the form of the circuit
pattern 36 in the inner portion of the upper substrate 30a as well
as on the outer surface of the upper substrate 30a in order to
secure radiation characteristics and impedance bandwidth required
for wireless communications.
[0093] After the upper substrate 30a is formed, the individual
semiconductor packages 100 are formed in operation S18 as shown in
FIG. 3I. The semiconductor chips 10 are separated by being cut
therebetween using a cutting blade 80, a laser beam, or the like,
such that the semiconductor chips 10 formed integrally by the
sealing part 20 are individually separated. As a result, the
individual semiconductor packages 100 as shown in FIG. 1 are
formed.
[0094] With the semiconductor package and the method of
manufacturing the same according to the present embodiment
configured as described above, only good semiconductor chips are
sorted from the individual semiconductor chips 10 and are
rearranged to manufacture the semiconductor package, whereby
reliability may be secured.
[0095] In addition, the substrate part 30 formed on both surfaces
(that is, upper and lower surfaces) of the semiconductor package
100 is utilized, whereby the semiconductor package may be
miniaturized and system in package may be implemented.
[0096] Further, the sealing of the semiconductor chip 10 is used to
thereby protect the semiconductor chip 10 from the outside, whereby
the semiconductor chips 10 having various forms such as a flip
chip, a chip using a wire bonding scheme, or the like, may be
utilized.
[0097] Furthermore, in the semiconductor package 100 according to
the present embodiment, the antenna part 40 and the semiconductor
chip 10 are disposed adjacent to each other to be formed
integrally, whereby an electrical connection distance between the
semiconductor chip 10 and the antenna part 40 may be minimized.
Therefore, when the semiconductor package 100 according to the
present embodiment is used in the millimeter wave band
(particularly, 60 GHz band), loss generated between the antenna
part 40 and the semiconductor chip 10 may be minimized.
[0098] In addition, the method of manufacturing a semiconductor
package according to the present embodiment forms the antenna part
40 during the process of forming the substrate part 30, whereby the
number of manufacturing processes and a manufacturing costs may be
reduced as compared to the case of the related art in which the
antenna part is separately manufactured and then coupled to the
substrate part.
[0099] Further, the method of manufacturing a semiconductor package
according to the present embodiment uses a semiconductor
manufacturing process. Therefore, the semiconductor manufacturing
equipment according to the related art may be utilized, whereby a
requirement for investment in new equipment for manufacturing the
semiconductor package may be minimized. In addition, fine circuit
patterns are formed on a substrate through the semiconductor
manufacturing process, whereby the semiconductor package 100 may be
miniaturized and thinned. Further, a general semiconductor
manufacturing process is utilized, whereby the semiconductor
package may be easily manufactured.
[0100] In addition, a sealing technology having high reliability is
used, whereby reliability for packaging of the semiconductor chip
10 may be secured.
[0101] Furthermore, the sealing part 20 is ground to adjust a
thickness thereof and the antenna part 40 is then formed, whereby
characteristics of the antenna part 40 may be adjusted. Therefore,
the signal matching of the antenna part 40 may be performed during
a manufacturing process.
[0102] Meanwhile, although the present embodiment describes the
substrate part 30 as being formed on both surfaces with respect to
a single semiconductor chip 10, the present invention is not
limited thereto. In the case in which a plurality of semiconductor
chips 10 are embedded such as the case in which the semiconductor
chips 10 are stacked, or the like, a ratio of a system in package
may be increased.
[0103] The semiconductor package and the method of manufacturing
the same according to the present invention may be variously
applied.
[0104] FIGS. 5 and 6 are cross-sectional views schematically
showing a semiconductor package according to other embodiments of
the present invention.
[0105] First, referring to FIG. 5, a semiconductor package 200
according to the present embodiment is different from the
semiconductor package 100 according to the above-mentioned
embodiment in terms of a configuration in which a plurality of
semiconductor chips 10 and 11 are mounted while being stacked, a
configuration in which the semiconductor chip 10 is electrically
connected to the substrate part 30 through a wire bonding scheme,
and a configuration in which the antenna part 40 is directly formed
on the sealing part 20 rather than the upper substrate 30a (See
FIG. 2).
[0106] Particularly, in the semiconductor package 200 according to
the present embodiment, after the thickness of the sealing part 20
may be adjusted using a grinder, or the like, and a groove 27 may
be formed using a laser beam, or the like, a radiator of the
antenna part 40 may be then formed to have a circuit pattern form
in the groove 27.
[0107] Meanwhile, when a depth of the groove 27 is variously formed
using the laser beam, or the like, and the antenna part 40 is then
formed in an inner portion of the groove 27 as shown in FIG. 5, the
radiator of the antenna part 40 may have various thicknesses.
[0108] The above-mentioned configuration may be realized by adding
the forming of the groove 27 in one surface of the sealing part 20.
The forming of the groove 27 may be undertaken after operation S13
of grinding one surface of the sealing part 20 as described above
or may be performed without operation S13.
[0109] As described above, the semiconductor package 200 according
to the present embodiment may utilize the semiconductor chips 10
having various shapes, and the substrate part 30 having various
shapes.
[0110] In the case in which the antenna part 40 is formed as
described above, the depth of the groove 27 in which the antenna
part 40 is formed is adjusted, whereby characteristics of the
antenna part 40 may be adjusted.
[0111] However, the present invention is not limited thereto. For
example, the antenna part 40 may also be formed without forming the
groove 27 in the sealing part 20. In this case, the number of
manufacturing processes may be reduced.
[0112] Referring to FIG. 6, a semiconductor package 300 according
to the present embodiment is different from the semiconductor
package 100 (See FIG. 2) according to the above-mentioned
embodiment only in that an active area of the semiconductor chip 10
in which the connection pad 12 is formed is disposed to face the
upper substrate 30a. In the case in which the semiconductor package
300 is configured as described above, an electrical distance
between the semiconductor chip 10 and the antenna part 40 is
shorter than that of the above-mentioned semiconductor package 100
shown in FIG. 2.
[0113] In addition, the via connection part 25 that has been used
to electrically connect the semiconductor chip 10 and the antenna
part 40 to each other is not used, whereby electrical loss may be
further reduced.
[0114] The semiconductor package and the method of manufacturing
the same according to the present invention as described above are
not limited to the above-mentioned embodiments but may be variously
applied. For example, although the above-mentioned embodiments
describe a case in which the substrate part is formed through the
semiconductor manufacturing process by way of example, various
methods may be applied thereto. For example, the substrate part may
also be formed using a general method of manufacturing a printed
circuit board.
[0115] In addition, although the above-mentioned embodiments
describe a case in which the semiconductor package is manufactured
by disposing the semiconductor chips on the carrier by way of
example, the present invention is not limited thereto.
[0116] That is, a separate substrate (hereinafter, referred to as a
support substrate) rather than the carrier may also be used. A
detailed description thereof will be provided below.
[0117] The semiconductor chips may be mounted on the support
substrate, on which electrode patterns are formed, instead of the
carrier. In this case, the separate adhesive layer 70 (See FIG. 3B)
is not used unlike in the case of the above-mentioned embodiment,
and the respective semiconductor chips may be mounted on the
support substrate while having separate connection pads directly
bonded to the electrode patterns formed on the support
substrate.
[0118] In addition, a support substrate on which circuit patterns
or electrode patterns are not formed may also be formed. In this
case, the semiconductor chips are mounted on and fixed to one
surface of the support substrate, through holes are formed in the
support substrate at positions corresponding to positions at which
the connection pads of the semiconductor chips are disposed, and
circuit patterns formed on the other surface of the support
substrate are electrically connected to the connection pads through
the through holes.
[0119] Therefore, when the support substrate is used as described
above, the process of removing the adhesive layer in the
above-mentioned embodiment may be omitted, and the support
substrate may be directly formed as the substrate part. In
addition, the substrate part may be formed as a multi-layer
substrate by repeatedly forming new insulating layers and circuit
patterns on the outer surface of the support substrate as
necessary.
[0120] As set forth above, with the semiconductor package and the
method of manufacturing the same according to the embodiments of
the present invention, only good semiconductor chips are sorted
among the individual semiconductor chips and then rearranged to
manufacture the semiconductor package, whereby reliability of a
product may be secured.
[0121] In addition, a scheme of sealing the semiconductor chip to
thereby protect the semiconductor chip from the outside is used,
whereby all of semiconductor chips having various forms such as a
form of a flip chip, a form of a chip using a wire bonding scheme,
or the like, may be utilized.
[0122] Further, the antenna part and the semiconductor chip are
disposed at a position adjacent to each other to be formed
integrally with each other, whereby an electrical connection
distance between the semiconductor chip and the antenna part may be
minimized. Therefore, when the semiconductor package is used in the
millimeter wave band (particularly, 60 GHz band), loss generated
between the antenna part and the semiconductor chip may be
minimized.
[0123] Furthermore, the method of manufacturing a semiconductor
package according to the present embodiment forms the antenna part
as well as the substrate part during the process of forming the
substrate part, whereby the number of manufacturing processes and a
manufacturing cost may be reduced as compared to the case of the
related art in which the antenna is separately manufactured and
then coupled to the substrate part.
[0124] Further, the semiconductor manufacturing equipment according
to the related art is utilized, whereby new equipment investment
for manufacturing the semiconductor package may be minimized. In
addition, fine circuit patterns are formed on a substrate through
the semiconductor manufacturing process, whereby the semiconductor
package may be miniaturized and thinned.
[0125] Furthermore, the sealing part is grinded to adjust a
thickness of the sealing part, whereby characteristics of the
antenna part may be adjusted. Therefore, signal matching of the
antenna part may be performed during a manufacturing process.
[0126] While the present invention has been shown and described in
connection with the embodiments, it will be apparent to those
skilled in the art that modifications and variations can be made
without departing from the spirit and scope of the invention as
defined by the appended claims.
* * * * *