U.S. patent application number 13/166144 was filed with the patent office on 2012-12-27 for memory structure and fabricating method thereof.
This patent application is currently assigned to MACRONIX INTERNATIONAL CO., LTD.. Invention is credited to Cheng-Hsien Cheng, Chih-Chieh Cheng, Jyun-Siang Huang, Wen-Jer Tsai, Shih-Guei Yan.
Application Number | 20120326222 13/166144 |
Document ID | / |
Family ID | 47361041 |
Filed Date | 2012-12-27 |
![](/patent/app/20120326222/US20120326222A1-20121227-D00000.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00001.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00002.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00003.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00004.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00005.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00006.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00007.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00008.png)
![](/patent/app/20120326222/US20120326222A1-20121227-D00009.png)
United States Patent
Application |
20120326222 |
Kind Code |
A1 |
Cheng; Cheng-Hsien ; et
al. |
December 27, 2012 |
MEMORY STRUCTURE AND FABRICATING METHOD THEREOF
Abstract
A memory structure including a memory cell is provided, and the
memory cell includes following elements. A first gate is disposed
on a substrate. A stacked structure includes a first dielectric
structure, a channel layer, a second dielectric structure and a
second gate disposed on the first gate, a first charge storage
structure disposed in the first dielectric structure and a second
charge storage structure disposed in the second dielectric
structure. At least one of the first charge storage structure and
the second charge storage structure includes two charge storage
units which are physically separated. A first dielectric layer is
disposed on the first gate at two sides of the stacked structure. A
first source and drain and a second source and drain are disposed
on the first dielectric layer and located at two sides of the
channel layer.
Inventors: |
Cheng; Cheng-Hsien;
(Hsinchu, TW) ; Tsai; Wen-Jer; (Hsinchu, TW)
; Yan; Shih-Guei; (Hsinchu, TW) ; Cheng;
Chih-Chieh; (Hsinchu, TW) ; Huang; Jyun-Siang;
(Hsinchu, TW) |
Assignee: |
MACRONIX INTERNATIONAL CO.,
LTD.
Hsinchu
TW
|
Family ID: |
47361041 |
Appl. No.: |
13/166144 |
Filed: |
June 22, 2011 |
Current U.S.
Class: |
257/324 ;
257/E21.423; 257/E29.309; 438/287 |
Current CPC
Class: |
H01L 29/7923 20130101;
H01L 29/66825 20130101; H01L 27/11551 20130101; H01L 27/11578
20130101; H01L 29/7887 20130101; H01L 29/40114 20190801; H01L
29/792 20130101; H01L 29/42332 20130101 |
Class at
Publication: |
257/324 ;
438/287; 257/E29.309; 257/E21.423 |
International
Class: |
H01L 29/792 20060101
H01L029/792; H01L 21/336 20060101 H01L021/336 |
Claims
1. A memory structure including a memory cell, the memory cell
comprising: a first gate disposed on a substrate; a stacked
structure, comprising: a first dielectric structure, a channel
layer, a second dielectric structure and a second gate disposed on
the first gate; a first charge storage structure disposed in the
first dielectric structure; and a second charge storage structure
disposed in the second dielectric structure, wherein at least one
of the first charge storage structure and the second charge storage
structure comprises two charge storage units which are physically
separated; a first dielectric layer disposed on the first gate at
two sides of the stacked structure; and a first source and drain
and a second source and drain disposed on the first dielectric
layer and located at two sides of the channel layer.
2. The memory structure as claimed in claim 1, wherein the first
charge storage structure and the second charge storage structure
are both two charge storage units which are physically
separated.
3. The memory structure as claimed in claim 2, wherein the two
charge storage units in the first charge storage structure are
isolated from each other through the first dielectric structure and
the two charge storage units in the second charge storage structure
are isolated from each other through the second dielectric
structure.
4. The memory structure as claimed in claim 1, wherein the first
charge storage structure is a singular charge storage unit and the
second charge storage structure comprises two charge storage units
which are physically separated.
5. The memory structure as claimed in claim 4, wherein the two
charge storage units in the second charge storage structure are
isolated from each other through the second dielectric structure
and the first dielectric structure comprises a second dielectric
layer and a third dielectric layer, wherein the second dielectric
layer is disposed between the first gate and the first charge
storage structure and the third dielectric layer is disposed
between the first charge storage structure and the channel
layer.
6. The memory structure as claimed in claim 1, wherein the first
charge storage structure comprises two charge storage units which
are physically separated and the second charge storage structure is
a singular charge storage unit.
7. The memory structure as claimed in claim 6, wherein the two
charge storage units in the first charge storage structure are
isolated from each other through the first dielectric structure and
the second dielectric structure comprises a fourth dielectric layer
and a fifth dielectric layer, wherein the fourth dielectric layer
is disposed between the channel layer and the second charge storage
structure and the fifth dielectric layer is disposed between the
second charge storage structure and the second gate.
8. The memory structure as claimed in claim 1, wherein when the
memory structure comprises a plurality of memory cells, the memory
cells are stacked.
9. The memory structure as claimed in claim 1, further comprising a
channel pick-up connected to the channel layer.
10. The memory structure as claimed in claim 1, wherein the first
gate is a first word line and the second gate is a portion of a
second word line, and the second word line does not need to align
the first word line.
11. A method of fabricating a memory structure, comprising: forming
a first gate on a substrate; forming a stacked structure on the
first gate, and the stacked structure comprising: a first
dielectric structure, a channel layer, a second dielectric
structure and a second gate disposed on the first gate; a first
charge storage structure disposed in the first dielectric structure
and including two first charge storage units which are physically
separated; and a second charge storage structure disposed in the
second dielectric structure and including two second charge storage
units which are physically separated; forming a first dielectric
layer on the first gate at two sides of the stacked structure; and
forming a first source and drain and a second source and drain on
the first dielectric layer at two sides of the channel layer.
12. The method of fabricating the memory structure as claimed in
claim 11, wherein a method of forming the first gate comprises an
ion implantation method or a chemical vapor deposition method.
13. The method of fabricating the memory structure as claimed in
claim 11, wherein a method of forming the stacked structure
comprises: forming a second dielectric material layer, a
semiconductor material layer, a third dielectric layer, and a gate
material layer sequentially on the first gate; patterning the
second dielectric material layer, the semiconductor material layer,
the third dielectric material layer, and the gate material layer to
form a second dielectric layer, the channel layer, a third
dielectric layer and the second gate sequentially on the first
gate; removing two sides of the second dielectric layer and two
sides of the third dielectric layer to form two first openings
between the channel layer and the first gate and form two second
openings between the second gate and the channel layer; forming a
fourth dielectric layer on a plurality of surfaces of the first
openings and a plurality of surfaces of the second openings; and
forming the first charge storage units filling the first openings
and the second charge storage units filling the second openings on
the fourth dielectric layer.
14. The method of fabricating the memory structure as claimed in
claim 13, wherein a method of forming the fourth dielectric layer
comprises forming a fourth dielectric material layer on a plurality
of surfaces of the first gate, the second dielectric layer, the
channel layer, the third dielectric layer, and the second gate.
15. The method of fabricating the memory structure as claimed in
claim 14, wherein a method of forming the first charge storage
units and the second charge storage units comprises: after the
fourth dielectric material layer is formed, forming a charge
storage material layer filling the first openings and the second
openings on the fourth dielectric material layer; and removing the
charge storage material layer located outside of the first openings
and the second openings.
16. The method of fabricating the memory structure as claimed in
claim 15, wherein a method of removing a portion of the charge
storage material layer comprises a dry etching method, a wet
etching method, or a combination thereof.
17. The method of fabricating the memory structure as claimed in
claim 11, wherein a method of forming the first source and drain
and the second source and drain comprises: forming a conductor
layer covering the stacked structure on the first dielectric layer;
and removing a portion of the conductor layer to form the first
source and drain and the second source and drain located at the two
sides of the channel layer, wherein a plurality of thicknesses of
the first source and drain, the second source and drain, and the
channel layer are substantially the same.
18. The method of fabricating the memory structure as claimed in
claim 11, further comprising forming a fifth dielectric layer
located at the two sides of the second gate on the first source and
drain and the second source and drain.
19. The method of fabricating the memory structure as claimed in
claim 18, wherein a method of forming the fifth dielectric layer
comprises: forming a fifth dielectric material layer on the first
source and drain and the second source and drain and the fifth
dielectric material layer covering the stacked structure; and
removing a portion of the fifth dielectric material layer until the
second gate is exposed.
20. The method of fabricating the memory structure as claimed in
claim 11, further comprising forming a connecting lead on the
second gate and the second gate forming a word line with the
connecting lead.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention related to a memory structure and a
fabricating method thereof. More particularly, the invention
relates to a memory structure having a plurality of charge storage
units which is physically separated and a fabricating method
thereof
[0003] 2. Description of Related Art
[0004] A memory is a semiconductor device designed to store
information or data. As micro-processors become more functional,
the programs and operations performed by software increase as well.
Thus, the demand for high capacity memory becomes higher. In
various memory products, non-volatile memory such as electrically
erasable programmable read only memory (EEPROM) allows multiple
data programming, reading, and erasing operations. Here, the data
stored therein are saved even after the memory has been
disconnected. According to the advantages mentioned above, EEPROM
has become a memory widely adopted in personal computers and
electronic apparatuses.
[0005] In a typical EEPROM, a floating gate and a control gate are
fabricated using doped polysilicon. When the memory is being
programmed, electrons injected into the floating gate then
distribute evenly in the entire polysilicon floating gate. However,
when defects are present in a tunnel oxide layer disposed under the
polysilicon floating gate, current leakage of devices then occurs
easily, thereby affecting the reliability of devices.
[0006] As a result, in order to prevent current leakage in EEPROM,
a conventional method is to replace the polysilicon floating gate
with a gate structure having a non-conductive charge storage layer.
Another advantage of replacing the polysilicon floating gate with
the charge storage layer is that when the device is being
programmed, electrons are only stored locally in the charge storage
layer above a source or a drain. Therefore, a source region and a
control gate at one end of a stacked gate are applied with a
voltage respectively during the programming so as to generate
electrons with Gaussian distribution in the charge storage layer
close to the source region. Moreover, a drain region at one end of
the stacked gate and the control gate are also applied with a
voltage respectively to generate electrons with Gaussian
distribution in the charge storage layer close to the drain region.
Consequently, by changing the voltage applied in the control gate
and the source/drain regions at the two sides thereof, two groups
of electrons with Gaussian distribution, one group of electrons
with Gaussian distribution, or no electrons can be present in a
single charge storage layer. Accordingly, the flash memory
replacing the floating gate with the charge storage layer can be
written into a single memory cell in four states and is a flash
memory with a 2 bits/cell storage.
[0007] Nevertheless, along with the increasing integrity of the
semiconductor device, the dimension of the non-volatile memory is
miniaturized constantly. As the miniaturization of the gate length
leads to the approximation of two charge storage units located on
the left and right in the same memory cell, a severe second bit
effect then occurs and easily results in erroneous reading. In
addition, since the source region and the drain region are
miniaturized, the source region and the drain region fail to block
the secondary hot electrons generated when the selected memory cell
is programmed. The second hot electrode is thus injected into the
adjacent memory cell to generate program disturbance and thereby
lowering the reliability of memory device.
SUMMARY OF THE INVENTION
[0008] Accordingly, an embodiment of the invention provides a
memory structure capable of solving the reading error caused by the
second bit effect.
[0009] Another embodiment of the invention provides a method of
fabricating a memory structure capable of reducing the programming
disturbance caused by secondary hot electrode.
[0010] An embodiment of the invention provides a memory structure
including a memory, and the memory cell includes the following
elements. A first gate is disposed on a substrate. A stacked
structure includes a first dielectric structure, a channel layer, a
second dielectric structure and a second gate disposed on the first
gate, a first charge storage structure disposed in the first
dielectric structure, and a second charge storage structure
disposed in the second dielectric structure. At least one of the
first charge storage structure and the second charge storage
structure includes two charge storage units which are physically
separated. A first dielectric layer is disposed on the first gate
at two sides of the stacked structure. A first source and drain and
a second source and drain are disposed on the first dielectric
layer and located at two sides of the channel layer.
[0011] According to an embodiment of the invention, in the memory
structure aforementioned, the first charge storage structure and
the second charge storage structure are both two charge storage
units which are physically separated, for example.
[0012] According to an embodiment of the invention, in the memory
structure aforementioned, the two charge storage units in the first
charge storage structure are isolated from each other through the
first dielectric structure and the two charge storage units in the
second charge storage structure are isolated from each other
through the second dielectric structure, for example.
[0013] According to an embodiment of the invention, in the memory
structure aforementioned, the first charge storage structure is a
singular charge storage unit, for example, and the second charge
storage structure includes, for instance, two charge storage units
which are physically separated.
[0014] According to an embodiment of the invention, in the memory
structure aforementioned, the two charge storage units in the
second charge storage structure are isolated from each other
through the second dielectric structure and the first dielectric
structure includes a second dielectric layer and a third dielectric
layer, for example. The second dielectric layer is disposed between
the first gate and the first charge storage structure and the third
dielectric layer is disposed between the first charge storage
structure and the channel layer.
[0015] According to an embodiment of the invention, in the memory
structure aforementioned, the first charge storage structure
includes two charge storage units which are physically separated,
for instance, and the second charge storage structure is a singular
charge storage unit, for instance.
[0016] According to an embodiment of the invention, in the memory
structure aforementioned, the two charge storage units in the first
charge storage structure are isolated from each other through the
first dielectric structure and the second dielectric structure
includes a fourth dielectric layer and a fifth dielectric layer,
for example. The fourth dielectric layer is disposed between the
channel layer and the second charge storage structure and the fifth
dielectric layer is disposed between the second charge storage
structure and the second gate.
[0017] According to an embodiment of the invention, in the memory
structure aforementioned, when the memory structure includes a
plurality of memory cells, the memory cells are stacked.
[0018] According to an embodiment of the invention, the memory
structure aforementioned further includes a channel pick-up
connected to the channel layer.
[0019] According to an embodiment of the invention, in the memory
structure aforementioned, the first gate is, for example, a first
word line and the second gate is, for example, a portion of a
second word line, and the second word line does not need to align
the first word line.
[0020] Another embodiment of the invention provides a method of
fabricating a memory structure and the method includes the
following. A first gate is formed on a substrate. A stacked
structure is formed on the first gate. The stacked structure
includes a first dielectric structure, a channel layer, a second
dielectric structure and a second gate disposed on the first gate,
a first charge storage structure disposed in the first dielectric
structure, and a second charge storage structure disposed in the
second dielectric structure. Herein, the first charge storage
structure includes two first charge storage units which are
physically separated, and the second charge storage structure
includes two second charge storage units which are physically
separated. A first dielectric layer is formed on the first gate at
two sides of the stacked structure. A first source and drain and a
second source and drain are formed on the first dielectric layer at
two sides of the channel layer.
[0021] According to an embodiment of the invention, in the method
of fabricating the memory structure, a method of forming the first
gate includes an ion implantation method or a chemical vapor
deposition method, for example.
[0022] According to another embodiment of the invention, in the
method of fabricating the memory structure, a method of forming the
stacked structure may include the following. A second dielectric
material layer, a semiconductor material layer, a third dielectric
layer, and a gate material layer are sequentially formed on the
first gate. The second dielectric material layer, the semiconductor
material layer, the third dielectric material layer, and the gate
material layer are patterned to form a second dielectric layer, the
channel layer, a third dielectric layer and the second gate
sequentially on the first gate. Two sides of the second dielectric
layer and two sides of the third dielectric layer are removed to
form two first openings between the channel layer and the first
gate and form two second openings between the second gate and the
channel layer. A fourth dielectric layer is formed on a plurality
of surfaces of the first openings and the second openings. The
first charge storage units filling the first openings and the
second charge storage units filling the second openings are formed
on the fourth dielectric layer.
[0023] According to another embodiment of the invention, in the
method of fabricating the memory structure, a method of forming the
fourth dielectric layer may include forming a fourth dielectric
material layer on a plurality of surfaces of the first gate, the
second dielectric layer, the channel layer, the third dielectric
layer, and the second gate.
[0024] According to another embodiment of the invention, in the
method of fabricating the memory structure, a method of forming the
first charge storage units and the second charge storage units may
include the following. After the fourth dielectric material layer
is formed, a charge storage material layer filling the first
openings and the second openings is formed on the fourth dielectric
material layer. The charge storage material layer located outside
of the first openings and the second openings is removed.
[0025] According to another embodiment of the invention, in the
method of fabricating the memory structure, a method of removing a
portion of the charge storage material layer is, for example, a dry
etching method, a wet etching method, or a combination thereof.
[0026] According to another embodiment of the invention, in the
method of fabricating the memory structure, a method of forming the
first source and drain and the second source and drain may include
the following. A conductor layer covering the stacked structure is
formed on the first dielectric layer. A portion of the conductor
layer is removed to form the first source and drain and the second
source and drain located at the two sides of the channel layer.
Herein, the thicknesses of the first source and drain, the second
source and drain, and the channel layer are substantially the same,
for example.
[0027] According to another embodiment of the invention, in the
method of fabricating the memory structure, a fifth dielectric
layer located at the two sides of the second gate is formed on the
first source and drain and the second source and drain.
[0028] According to another embodiment of the invention, in the
method of fabricating the memory structure, a method of forming the
fifth dielectric layer may include the following. A fifth
dielectric material layer is formed on the first source and drain
and the second source and drain and the fifth dielectric material
layer covers the stacked structure. A portion of the fifth
dielectric material layer is removed until the second gate is
exposed.
[0029] According to another embodiment of the invention, the method
of fabricating the memory structure aforementioned further includes
forming a connecting lead on the second gate and the second gate
forms a word line with the connecting lead.
[0030] In light of the foregoing, in the memory structure disclosed
in one embodiment of the invention, as at least one of the first
charge storage structure and the second charge storage structure
includes two charge storage units which are physically separated,
the reading error caused by the second bit effect can be prevented
and the programming disturbance led by the secondary hot electrode
can be reduced.
[0031] Moreover, another embodiment of the invention disclosed a
fabricating method of a memory structure which can be integrated
with the conventional fabrication. As a consequence, the
fabrication complexity is decreased effectively.
[0032] In order to make the aforementioned and other features and
advantages of the invention more comprehensible, several
embodiments accompanied with figures are described in detail
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The accompanying drawings are included to provide further
understanding, and are incorporated in and constitute a part of
this specification. The drawings illustrate embodiments and,
together with the description, serve to explain the principles of
the invention.
[0034] FIGS. 1A to 1H are cross-sectional diagrams illustrating a
flow chart for fabricating a memory structure according to a first
embodiment of the invention.
[0035] FIG. 2 shows a top view of FIG. 1H.
[0036] FIGS. 3 and 4 respectively depict cross-sectional views of
memory structures shown in a second embodiment and a third
embodiment of the invention.
[0037] FIG. 5 illustrates a cross-sectional view of a memory
structure according to a fourth embodiment of the invention.
DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
[0038] FIGS. 1A to 1H are cross-sectional diagrams illustrating a
flow chart for fabricating a memory structure according to a first
embodiment of the invention.
[0039] Referring to FIG. 1A, a gate 102 is first formed on a
substrate 100. The gate 102 is, for example, an N-type doped region
and the substrate 100 is, for example, a P-type doped substrate.
The N-type gate 102 and the P-type substrate 100 have contrary
doping types and can therefore block charges from communicating
therebetween. In another embodiment, the substrate 100 can also be
a P-type well region (not shown) located in an N-type well region
(not shown), so that the gate 102 is formed on the P-type well
region on the substrate 100. When the gate 102 is the N-type doped
region, a method of forming the gate 102 includes implanting a
dopant in the substrate 100 using an ion implantation method, for
instance.
[0040] In another embodiment, the gate 102 is a doped polysilicon
gate. When the gate 102 is a doped polysilicon gate, an isolation
dielectric layer is further formed between the substrate 100 and
the gate 102 to separate the substrate 100 and the gate 102.
[0041] Thereafter, a dielectric material layer 104, a semiconductor
material layer 106, a dielectric material layer 108, and a gate
material layer 110 are sequentially formed on the gate 102. The
dielectric material layer 104 is fabricated using silicon oxide,
for instance. The semiconductor material layer 106 is fabricated
with, for example, epitaxy silicon, polysilicon, or amorphous
silicon. The dielectric material layer 108 is fabricated using
silicon oxide, for instance. The gate material layer 110 is
fabricated using conductive material such as doped polysilicon,
metal, or so on, for example. The dielectric material layer 104,
the semiconductor material layer 106, the dielectric material layer
108, and the gate material layer 110 are formed using, for example,
a chemical vapor deposition (CVD) method or a physical vapor
deposition method (PVD).
[0042] Referring to FIG. 1B, the dielectric material layer 104, the
semiconductor material layer 106, the dielectric material layer
108, and the gate material layer 110 are patterned to form a
dielectric layer 112, a channel layer 114, a dielectric layer 116,
and a gate 118 on the gate 102 sequentially. The dielectric
material layer 104, the semiconductor material layer 106, the
dielectric material layer 108, and the gate material layer 110 are
patterned by performing a photolithography process and an etching
process to the layer aforementioned, for example.
[0043] Referring to FIG. 1 C, two sides of the dielectric layer 112
and two sides of the dielectric layer 116 are removed to form an
opening 120 between the channel layer 114 and the gate 102 and an
opening 122 between the gate 118 and the channel layer 114. A
portion of the dielectric layer 112 and a portion of the dielectric
layer 116 are removed using, for example, a wet etching method.
[0044] Afterwards, referring to FIG. 1D, a dielectric material
layer 124 is formed on surfaces of the gate 102, the dielectric
layer 112, the channel layer 114, the dielectric layer 116, and the
gate 118. The dielectric material layer 124 is fabricated using
silicon oxide, for instance. The dielectric material layer 124 is
formed, for example, with a thermal oxidation method.
[0045] A charge storage material layer 126 filling the opening 120
and the opening 122 is then formed on the dielectric material layer
124. The charge storage material layer 126 is fabricated using
silicon nitride, doped polysilicon, or nano grain, for example. The
charge storage material layer 126 is formed using a CVD method, for
example.
[0046] Subsequently, referring to FIG. 1E, the charge storage
material layer 126 located outside of the opening 120 and the
opening 122 is removed to form a plurality of charge storage units
128, 130 filling the opening 120 and a plurality of charge storage
units 132, 134 filling the opening 122. In the present embodiment,
the charge storage units 128, 130 which are physically separated
form a charge storage structure 136, and the charge storage units
132, 134 which are physically separated form a charge storage
structure 138. A portion of the charge storage material layer 126
is removed using, for example, a dry etching method, a wet etching
method, or a combination thereof.
[0047] Next, a dielectric material layer 140 is formed on a surface
of the dielectric material layer 124. The dielectric material layer
140 is fabricated using silicon oxide, for instance. The dielectric
material layer 140 is formed using a CVD method, for example.
[0048] Referring to FIG. 1F, the dielectric material layer 140 and
the dielectric material layer 124 located outside of the opening
120 and the opening 122 are removed. The dielectric material layer
124 and the dielectric material layer 140 located above the gate
102 are left outside of the opening 120 and the opening 122 to form
a dielectric layer 148. Consequently, a dielectric layer 142 is
formed by the dielectric material layer 124 located on surfaces of
the opening 120 and the opening 122. A portion of the dielectric
material layer 140 and a portion of the dielectric material layer
124 are removed using, for example, a dry etching method. At this
time, a portion of the dielectric material layer 124 and a portion
of the dielectric material layer 140 may remain above the gate
118.
[0049] Here, the dielectric layer 142 and the dielectric layer 112
located on the surface of the opening 120 form a dielectric
structure 144 for separating the charge storage units 128, 130 in
the charge storage structure 136. The charge storage structure 136,
the channel layer 114, and the gate 102 are thus separated. The
dielectric layer 142 and the dielectric layer 116 located on the
surface of the opening 122 form a dielectric structure 146 for
separating the charge storage units 132, 134 in the charge storage
structure 136. As a result, the charge storage structure 138, the
channel layer 114, and the gate 118 are separated.
[0050] In addition, a stacked structure 150 disposed on the gate
102 is formed by the dielectric structure 144, the channel layer
114, the dielectric structure 146, and the gate 118, the charge
storage structure 136 disposed in the dielectric structure 144, and
the charge storage structure 138 disposed in the dielectric
structure 146. Although the stacked structure 150 is fabricated
with the method above-mentioned, the methods of fabricating the
stacked structure 150 and the elements therein are not limited
thereto.
[0051] Moreover, the dielectric layer 148 located on the gate 102
at two sides of the stacked structure 150 is configured to isolate
the gate 102 from a source and drain subsequently formed on the
dielectric layer 148. The thickness of the dielectric layer 148
should be sufficient for isolating the gate 102 from the source and
drain subsequently formed on the dielectric layer 148. For example,
the thickness of the dielectric layer 148 is about the thickness of
the dielectric structure 144, for instance.
[0052] A conductor layer 152 is then formed on the dielectric layer
148 and the conductor layer 152 covers the stacked structure 150.
The conductor layer 152 is fabricated using doped polysilicon or
metal, for example. The conductor layer 152 is formed using a CVD
method, for example.
[0053] Referring to FIG. 1G, a portion of the conductor layer 152
is removed to form a source and drain 154 and a source and drain
156 located at two sides of the channel layer 114. Herein, the
thicknesses of the source and drain 154, the source and drain 156,
and the channel layer 114 are substantially the same, for instance.
A portion of the conductor layer 152 is removed using a dry etching
method, for example. At this time, the conductor layer 152 located
on a side wall of the channel layer 114 is removed to prevent the
gate 118 from electrically connecting with the source and drain 154
and the source and drain 156. Additionally, a portion of the
conductor layer 152 can be remained on the dielectric material
layer 140.
[0054] Further, the dielectric material layer 158 is formed on the
source and drain 154 and the source and drain 156, and the
dielectric material layer 158 covers the stacked structure 150. The
dielectric material layer 158 is fabricated using silicon oxide,
for instance. The dielectric material layer 158 is formed using a
CVD method, for example.
[0055] Referring to FIG. 1H, a portion of the dielectric material
layer 158 is removed until the gate 118 is exposed so as to form a
dielectric layer 160 located at two sides of the gate 118 on the
source and drain 154 and the source and drain 156. While removing a
portion of the dielectric material layer 158, the dielectric
material layer 124, the dielectric material layer 140 located above
the gate 118, and the conductor layer 152 remained on the
dielectric material layer 140 are removed simultaneously. A portion
of the dielectric material layer 158, the dielectric material layer
140, the dielectric material layer 124, and a portion of the
conductor layer 152 remained on the dielectric material layer 140
are removed with a chemical mechanical polishing method, for
instance.
[0056] Subsequently, a connecting lead 162 is formed on the gate
118, and the gate 118 forms a word line 164 with the connecting
lead 162. The connecting lead 162 is formed by, for example,
forming a conductor layer (not shown) on the gate 118 using a CVD
method and then patterning the conductor layer. The conductor layer
is fabricated using doped polysilicon or metal, for example.
[0057] Accordingly, the fabricating method of a memory structure
illustrated in the above embodiment can be integrated with the
conventional fabrication. As a consequence, the fabrication
complexity can be decreased effectively.
[0058] In the following, a memory structure disclosed in a first
embodiment is illustrated with FIG. 1H. FIG. 2 shows a top view of
FIG. 1H. FIG. 1H is a cross-sectional view taken along line I-I' in
FIG. 2.
[0059] Referring to FIGS. 1H and 2 simultaneously, a memory
structure includes a plurality of memory cells 166. Each of the
memory cells 166 includes a gate 102, a stacked structure 150, a
dielectric layer 148, a source and drain 154, and a source and
drain 156. Additionally, the memory structure further includes a
dielectric layer 160, a connecting lead 162, and a channel output
line 170. The connecting lead 162 is configured to connect the gate
118 in the stacked structure 150 to form a word line 164. The word
lines 164 are separated using an isolation structure 168. Herein,
each of the word lines 164 corresponds to a word line formed by the
gate 102, and the word lines formed by the gate 102 are separated
using the isolation structure (not shown). The word lines 164 do
not need to align the word lines formed by the gate 102. The
channel output line 170 is connected to the channel layer 114 for
outputting holes accumulated in the channel layer 114 so as to
prevent the floating-body effect, thereby preventing difficult
programming due to increasing potential of the channel layer. The
channel output line 170 is fabricated with conductive material such
as metal and so on, for example. In addition, the disposition,
material, fabricating method, and function of other elements in the
memory structure have been fully described in the above embodiment
and the details are thus omitted hereinafter.
[0060] Accordingly, as the charge storage units 128, 130 in the
charge storage structure 136 are physically separated and the
charge storage units 132, 134 in the charge storage structure 138
are physically separated, when the length of the gate is
miniaturized, the second bit effect between the two charge storage
units 128, 130 (or 132, 134) on the left and right sides of the
memory cell 166 is prevented, and reading errors caused therefrom
are thus prevented. Furthermore, as the charge storage units 128,
130 in the charge storage structure 136 are physically separated
and the charge storage units 132, 134 in the charge storage
structure 138 are physically separated, when the source and drain
154 and the source and drain 156 are miniaturized, the number of
secondary hot electrodes injected into the adjacent memory cell 166
is decreased. Consequently, the programming disturbance is reduced
so as to enhance the reliability of the memory device.
[0061] In the following, a memory structure disclosed in a first
embodiment is illustrated with FIG. 1H.
[0062] When a programming operation is performed to the charge
storage unit 134 in the memory cell 166, a first voltage is applied
at the gate 118, a second voltage is applied at the gate 102, a
third voltage is applied at the source and drain 154, and a fourth
voltage is applied at the source and drain 156. Herein, the first
voltage is higher than the second voltage, and the fourth voltage
is higher than the third voltage. The first voltage is, for
example, 11 V, the second voltage is, for example, 0 V, the third
voltage is, for example, 0 V, and the fourth voltage is, for
instance, 4 V. However, the operation voltages of the programming
operation in the invention are not limited thereto.
[0063] When a reading operation is performed to the charge storage
unit 134 in the memory cell 166, a fifth voltage is applied at the
gate 118, a sixth voltage is applied at the gate 102, a seventh
voltage is applied at the source and drain 154, and an eighth
voltage is applied at the source and drain 156. Herein, the fifth
voltage is higher than the sixth voltage, and the seventh voltage
is higher than the eighth voltage. The fifth voltage is, for
example, 3 V, the sixth voltage is, for example, 0 V, the seventh
voltage is, for example, 1.6 V, and the eighth voltage is, for
instance, 0 V. However, the operation voltages of the reading
operation in the invention are not limited thereto.
[0064] When an erasing operation is performed to the charge storage
unit 134 in the memory cell 166, a ninth voltage is applied at the
gate 118, a tenth voltage is applied at the gate 102, an eleventh
voltage is applied at the source and drain 154, and a twelfth
voltage is applied at the source and drain 156. Herein, the tenth
voltage is higher than the ninth voltage, the twelfth voltage is
higher than the eleventh voltage, and the ninth voltage and the
twelfth voltage are electrically opposite. The ninth voltage is,
for example, -6 V, the tenth voltage is, for example, 0 V, the
eleventh voltage is, for example, 0 V, and the twelfth voltage is,
for instance, 4 V. However, the operation voltages of the erasing
operation in the invention are not limited thereto.
[0065] Additionally, those with common knowledge in the art should
be able to operate the charge storage units 128, 130, 134 in the
memory cell 166 according to the operation method disclosed in the
above embodiment, and the details are thus omitted hereinafter.
[0066] FIGS. 3 and 4 respectively depict cross-sectional views of
memory structures shown in a second embodiment and a third
embodiment of the invention.
[0067] In the first embodiment, the memory structure is illustrated
with the two charge storage structures 136, 138 respectively
including two charge storage units 128, 130 and 132, 134 which are
physically separated in the memory cell 166. However, the scope of
the invention is not limited thereto, the protection scope of the
invention applies as long as at least one of the charge storage
structures 136, 138 includes the two charge storage units which are
physically separated.
[0068] For example, referring to FIGS. 1H and 3 simultaneously, the
difference between the memory structures in the first embodiment
and the second embodiment is that in the memory structure of the
second embodiment, a charge storage structure 136' is a singular
charge storage unit and a dielectric structure 144' includes a
dielectric layer 172 and a dielectric layer 174. Herein, the
dielectric layer 172 is disposed between the gate 102 and the
charge storage structure 136', and the dielectric layer 174 is
disposed between the charge storage structure 136' and the channel
layer 114. The charge storage structure 136' is fabricated using
silicon nitride, doped polysilicon, or nano grain, for example. The
dielectric layer 172 and the dielectric layer 174 are fabricated
with silicon oxide respectively, for instance. Other elements in
the second embodiment are similar to those in the first embodiment
and the descriptions are thus omitted hereinafter.
[0069] Referring to FIGS. 1H and 4 simultaneously, the difference
between the memory structures in the first embodiment and the third
embodiment is that in the memory structure of the third embodiment,
a charge storage structure 138' is a singular charge storage unit
and a dielectric structure 146' includes a dielectric layer 176 and
a dielectric layer 178. Herein, the dielectric layer 176 is
disposed between the channel layer 114 and the charge storage
structure 138', and the dielectric layer 178 is disposed between
the charge storage structure 138' and the gate 118. The charge
storage structure 138' is fabricated using silicon nitride, doped
polysilicon, or nano grain, for example. The dielectric layer 176
and the dielectric layer 178 are fabricated with silicon oxide
respectively, for instance. Other elements in the third embodiment
are similar to those in the first embodiment and the descriptions
are thus omitted hereinafter.
[0070] FIG. 5 illustrates a cross-sectional view of a memory
structure according to a fourth embodiment of the invention.
[0071] The difference between the memory structures in the first
embodiment and the fourth embodiment is that the memory structure
in the fourth embodiment has a plurality of memory cells 166
stacked together, where every two memory cells 166 that are
perpendicularly adjacent to each other share a common word line.
Other elements in the fourth embodiment are similar to those in the
first embodiment and the descriptions are thus omitted
hereinafter.
[0072] In the fourth embodiment, since the memory structure has a
plurality of memory cells 166 which is stacked together, the
integrity of the memory device can further be increased.
[0073] In summary, the embodiments aforementioned include at least
the following advantages.
[0074] The memory structure provided in the embodiments
aforementioned is capable of solving the reading error caused by
the second bit effect and reducing the programming disturbance led
by the secondary hot electrode.
[0075] The method of fabricating the memory structure illustrated
in the above embodiments can be integrated with the conventional
fabrication, thereby reducing the fabrication complexity
effectively.
[0076] The memory structure provided in the embodiments mentioned
above can further enhance the integrity of the memory device.
[0077] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
disclosed embodiments without departing from the scope or spirit of
the invention. In view of the foregoing, it is intended that the
invention cover modifications and variations of this invention
provided they fall within the scope of the following claims and
their equivalents.
* * * * *