U.S. patent application number 13/591281 was filed with the patent office on 2012-12-13 for semiconductor device manufacturing apparatus.
This patent application is currently assigned to TOKYO ELECTRON LIMITED. Invention is credited to Satoru Shimura, Hidetami Yaegashi.
Application Number | 20120312472 13/591281 |
Document ID | / |
Family ID | 40955521 |
Filed Date | 2012-12-13 |
United States Patent
Application |
20120312472 |
Kind Code |
A1 |
Yaegashi; Hidetami ; et
al. |
December 13, 2012 |
SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS
Abstract
A semiconductor device manufacturing apparatus includes: a first
pattern forming unit for forming a first pattern by patterning a
first mask material layer; a boundary layer forming unit for
forming a boundary layer at sidewall portions and top portions of
the first pattern; a second mask material layer forming unit for
forming a second mask material layer so as to cover a surface of
the boundary layer; a second mask material removing unit for
removing a part of the second mask material layer to expose top
portions of the boundary layer; a boundary layer etching unit for
forming a second pattern by etching and removing the boundary layer
and forming a void between the sidewall portions of the first
pattern and the second mask material layer; and a trimming unit for
reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
Inventors: |
Yaegashi; Hidetami;
(Yamanashi, JP) ; Shimura; Satoru; (Yamanashi,
JP) |
Assignee: |
TOKYO ELECTRON LIMITED
Tokyo
JP
|
Family ID: |
40955521 |
Appl. No.: |
13/591281 |
Filed: |
August 22, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12370768 |
Feb 13, 2009 |
8273661 |
|
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13591281 |
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Current U.S.
Class: |
156/345.1 |
Current CPC
Class: |
H01L 21/0337 20130101;
H01L 27/105 20130101; H01L 27/1052 20130101 |
Class at
Publication: |
156/345.1 |
International
Class: |
H01L 21/308 20060101
H01L021/308 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 15, 2008 |
JP |
2008-034230 |
Jan 9, 2009 |
JP |
2009-003910 |
Claims
1. A semiconductor device manufacturing apparatus for forming a
mask for etching an etching target layer on a substrate, the
apparatus comprising: a first pattern forming unit for forming a
first pattern by patterning a first mask material layer made of a
photoresist; a boundary layer forming unit for forming a boundary
layer, which is made of a material selectively removable with
respect to the photoresist, at sidewall portions and top portions
of the first pattern; a second mask material layer forming unit for
forming a second mask material layer, which is made of a material
that allows the boundary layer to be selectively removed, so as to
cover a surface of the boundary layer; a second mask material
removing unit for removing a part of the second mask material layer
to expose top portions of the boundary layer; a boundary layer
etching unit for forming a second pattern made of the second mask
material layer by etching and removing the boundary layer and
forming a void between the sidewall portions of the first pattern
and the second mask material layer; and a trimming unit for
reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
2. A semiconductor device manufacturing apparatus for forming a
mask for etching an etching target layer on a substrate, the
apparatus comprising: a first pattern forming unit for forming a
first pattern by patterning a first mask material layer made of a
photoresist; a boundary layer forming unit for forming a boundary
layer, which is made of a material selectively removable with
respect to the photoresist, at sidewall portions and top portions
of the first pattern; a second mask material layer forming unit for
forming a second mask material layer, which is made of a material
that allows the boundary layer to be selectively removed, while top
portions of the boundary layer are exposed; a boundary layer
etching unit for forming a second pattern made of the second mask
material layer by etching and removing the boundary layer and
forming a void between the sidewall portions of the first pattern
and the second mask material layer; and a trimming unit for
reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
Description
FIELD OF THE INVENTION
[0001] The present disclosure relates to a pattern forming method
for forming a mask used in performing an etching process such as a
plasma etching process or the like on a substrate such as a
semiconductor wafer or the like; and also relates to a
semiconductor device manufacturing method and a semiconductor
device manufacturing apparatus.
BACKGROUND OF THE INVENTION
[0002] Conventionally, in a manufacturing process for a
semiconductor device or the like, a microscopic circuit pattern has
been formed by performing an etching process, e.g., a plasma
etching process on a substrate such as a semiconductor wafer. In
this etching process, a mask is formed by a photolithography
process employing a photoresist.
[0003] With respect to this photolithography process, there have
been developed various techniques so as to keep up with the
miniaturization of a pattern to be formed. One example is so-called
a double patterning. In the double patterning, a two-step
patterning is performed. In one step, a first pattern is formed by
a first lithography process of performing coating, exposure and
development processes on a photoresist; and in the other step, a
second pattern is formed by a second lithography process of
performing coating, exposure and development processes again on a
photoresist after the first lithography process. By performing the
two-step patterning, it is possible to form a mask having a finer
gap in comparison to a mask formed by performing the patterning
only once (for example, see Patent Document 1).
Patent Document 1: U.S. Pat. No. 7,064,078
BRIEF SUMMARY OF THE INVENTION
[0004] As stated above, in the double patterning technique,
exposure processes are performed two times while lithography
processes are performed two times. As a result, there have been
problems that the process becomes complicated and the manufacturing
cost of a semiconductor device increases; and there have been other
problems that it is difficult to accurately perform an alignment
with respect to a first exposure process in a second exposure
process and it is difficult to accurately perform the
patterning.
[0005] In view of the foregoing, the present disclosure provides a
pattern forming method capable of accurately forming a microscopic
pattern without performing the second exposure process, thereby
simplifying the process in comparison to the conventional process
and reducing the manufacturing cost of the semiconductor device;
and also provides a semiconductor device manufacturing method and a
semiconductor device manufacturing apparatus.
[0006] In accordance with one aspect of the present disclosure,
there is provided a pattern forming method for forming a pattern of
a predetermined shape which serves as a mask for etching an etching
target layer on a substrate, the method including: a first pattern
forming process for forming a first pattern by patterning a first
mask material layer made of a photoresist; a boundary layer forming
process for forming a boundary layer, which is made of a material
selectively removable with respect to the photoresist, at sidewall
portions and top portions of the first pattern; a second mask
material layer forming process for forming a second mask material
layer, which is made of a material that allows the boundary layer
to be selectively removed, so as to cover a surface of the boundary
layer; a second mask material removing process for removing a part
of the second mask material layer to expose top portions of the
boundary layer; a boundary layer etching process for forming a
second pattern made of the second mask material layer by etching
and removing the boundary layer and forming a void between the
sidewall portions of the first pattern and the second mask material
layer; and a trimming process for reducing a width of the first
pattern and a width of the second pattern to predetermined
widths.
[0007] In accordance with another aspect of the present disclosure,
there is provided a pattern forming method for forming a pattern of
a predetermined shape which serves as a mask for etching an etching
target layer on a substrate, the method including: a first pattern
forming process for forming a first pattern by patterning a first
mask material layer made of a photoresist; a boundary layer forming
process for forming a boundary layer, which is made of a material
selectively removable with respect to the photoresist, at sidewall
portions and top portions of the first pattern; a second mask
material layer forming process for forming a second mask material
layer, which is made of a material that allows the boundary layer
to be selectively removed, while top portions of the boundary layer
are exposed; a boundary layer etching process for forming a second
pattern made of the second mask material layer by etching and
removing the boundary layer and forming a void between the sidewall
portions of the first pattern and the second mask material layer;
and a trimming process for reducing a width of the first pattern
and a width of the second pattern to predetermined widths.
[0008] In accordance with still another aspect of the present
disclosure, there is provided a semiconductor device manufacturing
method including a process for etching an etching target layer on a
substrate through a mask, wherein the mask is formed by a pattern
forming method including: a first pattern forming process for
forming a first pattern by patterning a first mask material layer
made of a photoresist; a boundary layer forming process for forming
a boundary layer, which is made of a material selectively removable
with respect to the photoresist, at sidewall portions and top
portions of the first pattern; a second mask material layer forming
process for forming a second mask material layer, which is made of
a material that allows the boundary layer to be selectively
removed, so as to cover a surface of the boundary layer; a second
mask material removing process for removing a part of the second
mask material layer to expose top portions of the boundary layer; a
boundary layer etching process for forming a second pattern made of
the second mask material layer by etching and removing the boundary
layer and forming a void between the sidewall portions of the first
pattern and the second mask material layer; and a trimming process
for reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
[0009] In accordance with still another aspect of the present
disclosure, there is provided a semiconductor device manufacturing
method including a process for etching an etching target layer on a
substrate through a mask, wherein the mask is formed by a pattern
forming method including: a first pattern forming process for
forming a first pattern by patterning a first mask material layer
made of a photoresist; a boundary layer forming process for forming
a boundary layer, which is made of a material selectively removable
with respect to the photoresist, at sidewall portions and top
portions of the first pattern; a second mask material layer forming
process for forming a second mask material layer, which is made of
a material that allows the boundary layer to be selectively
removed, while top portions of the boundary layer are exposed; a
boundary layer etching process for forming a second pattern made of
the second mask material layer by etching and removing the boundary
layer and forming a void between the sidewall portions of the first
pattern and the second mask material layer; and a trimming process
for reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
[0010] In accordance with still another aspect of the present
disclosure, there is provided a semiconductor device manufacturing
apparatus for forming a mask for etching an etching target layer on
a substrate, the apparatus including: a first pattern forming unit
for forming a first pattern by patterning a first mask material
layer made of a photoresist; a boundary layer forming unit for
forming a boundary layer, which is made of a material selectively
removable with respect to the photoresist, at sidewall portions and
top portions of the first pattern; a second mask material layer
forming unit for forming a second mask material layer, which is
made of a material that allows the boundary layer to be selectively
removed, so as to cover a surface of the boundary layer; a second
mask material removing unit for removing a part of the second mask
material layer to expose top portions of the boundary layer; a
boundary layer etching unit for forming a second pattern made of
the second mask material layer by etching and removing the boundary
layer and forming a void between the sidewall portions of the first
pattern and the second mask material layer; and a trimming unit for
reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
[0011] In accordance with still another aspect of the present
disclosure, there is provided a semiconductor device manufacturing
apparatus for forming a mask for etching an etching target layer on
a substrate, the apparatus including: a first pattern forming unit
for forming a first pattern by patterning a first mask material
layer made of a photoresist; a boundary layer forming unit for
forming a boundary layer, which is made of a material selectively
removable with respect to the photoresist, at sidewall portions and
top portions of the first pattern; a second mask material layer
forming unit for forming a second mask material layer, which is
made of a material that allows the boundary layer to be selectively
removed, while top portions of the boundary layer are exposed; a
boundary layer etching unit for forming a second pattern made of
the second mask material layer by etching and removing the boundary
layer and forming a void between the sidewall portions of the first
pattern and the second mask material layer; and a trimming unit for
reducing a width of the first pattern and a width of the second
pattern to predetermined widths.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The disclosure may best be understood by reference to the
following description taken in conjunction with the following
figures:
[0013] FIGS. 1A to 1G are views for explaining a pattern forming
method and a semiconductor device manufacturing method in
accordance with an embodiment of the present disclosure;
[0014] FIG. 2 is a flowchart showing a process of the method of
FIGS. 1A to 1G;
[0015] FIG. 3 is a block diagram showing a configuration of a
semiconductor device manufacturing apparatus in accordance with the
embodiment of the present disclosure;
[0016] FIGS. 4A to 4F are views for explaining a pattern forming
method and a semiconductor device manufacturing method in
accordance with a second embodiment of the present disclosure;
[0017] FIG. 5 is a flowchart showing a process of the method of
FIGS. 4A to 4F;
[0018] FIG. 6 is a diagram showing a configuration of a
semiconductor device manufacturing apparatus in accordance with the
second embodiment of the present disclosure;
[0019] FIGS. 7A to 7K are views for explaining a pattern forming
method and a semiconductor device manufacturing method in
accordance with a third embodiment of the present disclosure;
[0020] FIGS. 8A to 8J are views for explaining a pattern forming
method and a semiconductor device manufacturing method in
accordance with a fourth embodiment of the present disclosure;
and
[0021] FIGS. 9A to 9C are views for explaining a pattern forming
process by a sidewall transfer process.
EXPLANATION OF CODES
[0022] 101: substrate [0023] 102: first layer [0024] 103: second
layer [0025] 104: third layer [0026] 105: first pattern [0027] 106:
boundary layer [0028] 107: second mask material layer
DETAILED DESCRIPTION OF THE INVENTION
[0029] Hereinafter, embodiments of the present disclosure will be
described in detail with reference to the accompanying
drawings.
[0030] FIGS. 1A to 1G show enlarged schematic views of a part of a
substrate in accordance with an embodiment of the present
disclosure so as to illustrate a process of the present embodiment,
and FIG. 2 is a flowchart showing the process of the present
embodiment. As illustrated in FIGS. 1A to 1G, formed on a substrate
101 is a multilayer of a first layer 102, a second layer 103 and a
third layer 104 which are made of different materials. Among these
layers, at least one layer (the third layer 104) becomes an etching
target layer.
[0031] First, as illustrated in FIG. 1A, performed is a first
pattern forming process for forming a first pattern 105, which is
made of a photoresist patterned in a predetermined pattern, by
performing coating, exposure and development processes on the third
layer 104 (Step 201 of FIG. 2). As the photoresist (first mask
material) for forming the first pattern 105, it is desirable to use
an ArF resist so as to form a finer pattern, and a positive type
chemically amplified resist may be used, for example.
[0032] Subsequently, as illustrated in FIG. 1B, performed is a
boundary layer forming process for forming a boundary layer 106 at
sidewall portions and top portions of the first pattern 105 (Step
202 of FIG. 2). The boundary layer 106 can be formed by a film
forming process or by modifying surfaces of the sidewall portions
and the top portions of the first pattern 105 (FIG. 1B shows a case
of the film forming process). The boundary layer 106 needs to be
made of a material which can be selectively removed with respect to
the photoresist constituting the first pattern 105. In case that
the boundary layer 106 is formed by the film forming process,
SiO.sub.2 can be appropriately used as the material, for example.
In case of forming the boundary layer 106 by using SiO.sub.2, it is
necessary to perform the film forming process at a temperature
lower than a heat resistant temperature of the first pattern 105,
and for example, a low temperature CVD (Chemical Vapor Deposition)
or an ALD (Atomic Layer Deposition) is performed. A thickness of
the boundary layer 106 is set to be, for example, about 5 to 20 nm.
Meanwhile, in case of forming the boundary layer 106 by modifying
the surfaces of the sidewall portions and the top portions of the
first pattern 105, it is possible to employ a method of silylating
by using an HMDS or the like, or a method of oxidizing by supplying
acid to the photoresist.
[0033] Thereafter, as illustrated in FIG. 1C, performed is a second
mask material layer forming process for forming a second mask
material layer 107 so as to cover surfaces of the boundary layer
106 (Step 203 of FIG. 2). The second mask material layer 107 needs
to be made of a material which allows the boundary layer 106 to be
selectively removed, and a photoresist or an organic film can be
used, for example. In case of using the photoresist, it may be
possible to use the same photoresist as the photoresist
constituting the first pattern 105 or use a different kind of
photoresist (e.g., a KrF resist if the first pattern 105 is made of
an ArF resist). In this case, the second mask material layer 107
can be formed through a coating process by a spin coating apparatus
or through a film forming process by a CVD apparatus.
[0034] Further, as illustrated in FIG. 1D, performed is a second
mask material removing process for removing a part (surface layer)
of the second mask material layer 107 till top portions of the
boundary layer 106 are exposed (Step 204 of FIG. 2). In this second
mask material removing process, there may be used a removing method
by melting with liquid chemical, a removing method by a dry etching
or a chemical and physical removing method by a CMP.
[0035] Subsequently, as illustrated in FIG. 1E, performed is a
boundary layer etching process for forming a second pattern made of
the second mask material layer 107 by selectively etching and
removing the boundary layer 106 with respect to the first pattern
105 and the second mask material layer 107 (Step 205 of FIG. 2). In
this case, since the boundary layer 106 is formed by modifying, for
example, SiO.sub.2 or the photoresist, it is easy to selectively
etch the boundary layer 106 with respect to the first pattern 105
made of the photoresist and the second mask material layer 107 made
of the photoresist or the organic film. The boundary layer etching
process can be performed by, e.g., a dry etching or a wet etching
using dilute hydrofluoric acid.
[0036] Thereafter, as illustrated in FIG. 1F, performed is a
trimming process for reducing a width of the first pattern 105 and
a width of the second pattern made of the second mask material
layer 107 to predetermined widths (Step 206 of FIG. 2). The
trimming process can be performed by, for example, an immersion
method in a developing solution having a high temperature or a high
concentration for a long period of time; a developing method after
a coating process with an acid material or an exposing process to
an acid vapor atmosphere; a method of performing a pre-processing
of an immersion process in a developing solution having a high
temperature or a high concentration for a long period of time and
then performing a developing process after a coating process with
an acid material or an exposing process to an acid vapor
atmosphere; or a method of performing a coating process with an
acid material or an exposing process to an acid vapor atmosphere
and then performing a developing process after coating a top
portion of a pattern with an amine-based material neutralizing the
acid or exposing it to a vapor atmosphere.
[0037] Through performing the above-stated process, a pattern
serving as an etching mask is formed. Further, by using this
pattern as a mask, performed is an etching process on the third
layer 104 as a lower layer or the like, as illustrated in FIG.
1G.
[0038] As stated above, in the pattern forming method in accordance
with the present embodiment, it is possible to form a pattern as
fine as that of the conventional double patterning by performing
only the first exposure process for forming the first pattern 105
without requiring a second exposure process. Therefore, there is no
need for an alignment to be performed in the second exposure
process and there occurs no misalignment during the alignment.
Accordingly, it is possible to accurately form a pattern and to
simplify the process in comparison to the conventional process,
thereby reducing a manufacturing cost of a semiconductor
device.
[0039] FIG. 3 shows a configuration of a semiconductor device
manufacturing apparatus for performing the above-stated pattern
forming method. As illustrated in FIG. 3, a semiconductor device
manufacturing apparatus 300 includes a first pattern forming unit
301, a boundary layer forming unit 302, a second mask material
layer forming unit 303, a second mask material removing unit 304, a
boundary layer etching unit 305 and a trimming unit 306. Further,
each of these units is connected to each other by a substrate
transfer path 310 for transferring a substrate such as a
semiconductor wafer or the like.
[0040] The first pattern forming unit 301 is used for forming the
first pattern 105, and includes a coating device, an exposure
device, a developing device and the like. The boundary layer
forming unit 302 is used for forming the boundary layer 106, and
includes a film forming apparatus such as a CVD apparatus or a
surface modifying apparatus for modifying the surfaces of the
sidewall portions and the top portions of the first pattern 105.
The second mask material layer forming unit 303 is used for forming
the second mask material layer 107, and includes a coating device
for coating a photoresist or a film forming apparatus for forming
an organic film. The second mask material removing unit 304 is used
for performing the second mask material removing process which
removes a part of the second mask material layer 107 till the top
portion of the boundary layer 106 is exposed, and includes a wet or
dry etching apparatus, or a CMP apparatus. The boundary layer
etching unit 305 is used for performing the boundary layer etching
process in which the boundary layer 106 is selectively etched and
removed with respect to the first pattern 105 and the second mask
material layer 107, and includes a wet or dry etching apparatus.
The trimming unit 306 is used for performing the trimming process,
and includes an apparatus for immersing a semiconductor wafer into
liquid chemical such as a developing solution or for exposing the
semiconductor wafer to a vapor atmosphere. With the semiconductor
device manufacturing apparatus 300 configured as stated above, it
is possible to perform a series of the processes in the
above-stated embodiment.
[0041] Hereinafter, a second embodiment will be described with
reference to FIGS. 4A to 6. FIGS. 4A to 4F are enlarged schematic
views of a part of a substrate in accordance with the second
embodiment so as to illustrate a process of the second embodiment,
and FIG. 5 is a flowchart showing the process of the second
embodiment. In the second embodiment, as illustrated in FIG. 4C, a
second mask material layer 107 is formed so that a top portion of a
boundary layer 106 is exposed in a second mask material layer
forming process (Step 403 of FIG. 5). Therefore, the second
embodiment does not include a process corresponding to the second
mask material removing process (Step 204 of FIG. 2) performed in
the first embodiment. In this manner, in order to form the second
mask material layer 107 so that the top portion of the boundary
layer 106 is exposed, these materials are selected so that a
wettability of the boundary layer 106 is lower with respect to the
second mask material (for example, different materials having
polarity), and a liquid phase second mask material may be coated
onto the boundary layer 106 to realize this process.
[0042] In addition, the other processes are performed in the same
manner as in the first embodiment so that the explanation thereof
is omitted. In the second embodiment, it is possible to obtain the
same effect as that of the first embodiment and also, as stated
above, it is possible to omit the second mask material removing
process so that the process can be more simplified.
[0043] FIG. 6 illustrates a configuration of a semiconductor device
manufacturing apparatus for performing the pattern forming method
in accordance with the second embodiment. As illustrated in FIG. 6,
a semiconductor device manufacturing apparatus 300a includes a
first pattern forming unit 301, a boundary layer forming unit 302,
a second mask material layer forming unit 303, a boundary layer
etching unit 305 and a trimming unit 306. Further, each of these
units is connected to each other by a substrate transfer path 310
for transferring a substrate such as a semiconductor wafer or the
like. That is, the semiconductor device manufacturing apparatus
300a is different from the semiconductor device manufacturing
apparatus 300 illustrated in FIG. 3 only in that it does not
include the second mask material removing unit 304. With the
semiconductor device manufacturing apparatus 300a configured as
stated above, it is possible to perform a series of the processes
in the second embodiment.
[0044] A repeated pattern of a narrow pitch formed by the
above-stated process can be used in a semiconductor device such as
a NAND-type flash memory. As a method for forming the repeated
pattern of a narrow pitch, there has been conventionally known a
method employing, for example, a so-called sidewall transfer
process.
[0045] In the sidewall transfer process, as illustrated in FIGS. 9A
to 9C, a film 602 serving as a mask is formed at sidewalls of a
first pattern 601 formed by a lithography process using a
photoresist, and by removing the first pattern 601 formed first,
two patterns are formed from one pattern, thereby forming a pattern
of a narrow pitch.
[0046] In this case, as illustrated in FIG. 9A, a pattern formed at
the sidewalls of the first pattern 601 is formed in a loop shape
throughout the entire periphery of the sidewalls. For this reason,
as illustrated in FIG. 9B, performed is a second photolithography
process so as to remove an unnecessary part of this loop (end
loop). Subsequently, the first pattern 601 is removed from a state
illustrated in FIG. 9C, and the pattern at the sidewalls is used as
a mask. If a pattern of a peripheral circuit or the like is formed
at the periphery of the repeated pattern described above, a third
photolithography process is performed to form the pattern of the
peripheral circuit or the like.
[0047] This is because that in case of forming the pattern of the
peripheral circuit partially connected with the repeated pattern,
since the repeated pattern is formed at the sidewalls of the first
pattern 601 as described above, the pattern of the peripheral
circuit connected with the repeated pattern can not be formed
during the first photolithography process. Further, since the
second photolithography process is performed to remove the end
loop, the pattern connected with the repeated pattern can not be
formed without performing this process.
[0048] Contrary to this, in the aforementioned embodiments, since
the part of the first pattern 105 made of the photoresist formed in
the first pattern forming process remains as a part of the repeated
pattern in the end, it is possible to form a pattern of a
peripheral circuit partially connected with the repeated pattern
during the photolithography process of the first pattern forming
process.
[0049] FIGS. 7A to 7K illustrate a process of a third embodiment of
forming a memory cell unit having a repeated pattern of a narrow
pitch such as a NAND-type flash memory and a peripheral circuit
electrically connected with this memory cell unit, and
schematically illustrate cross-sectional configurations thereof in
upper sides and plane configurations thereof in lower sides.
[0050] In the third embodiment, as illustrated in FIG. 7A, during a
process corresponding to the first pattern forming process
illustrated in FIG. 1A, formed are a repeated pattern portion 501
in which a plurality of same patterns is formed at a predetermined
distance and a peripheral circuit pattern portion 502 formed at a
periphery of the repeated pattern portion 501. A part of the
peripheral circuit pattern portion 502 may be connected with the
repeated pattern portion 501.
[0051] Subsequently, as illustrated in FIGS. 7B to 7D, performed
are a boundary layer forming process (FIG. 7B) for forming a
boundary layer 106 as illustrated in FIG. 1B, a second mask
material layer forming process (FIG. 7C) for forming a second mask
material layer 107 to cover a surface of the boundary layer 106,
and a second mask material removing process (FIG. 7D) for removing
a part (surface layer) of the second mask material layer 107 till
top portions of the boundary layer 106 are exposed.
[0052] Thereafter, there is performed a second boundary layer
forming process (FIG. 7E) for forming a second boundary layer 120
made of a material (e.g., SiO.sub.2 or the like), which can be
selectively removed with respect to a photoresist, on the second
mask material layer 107 and the boundary layer 106.
[0053] Then, performed is a third mask material layer forming
process (FIG. 7F) for forming a third mask material layer 121,
which is made of a photoresist and formed in a predetermined
pattern, on the second boundary layer 120. The third mask material
layer 121 is formed in a pattern capable of removing unnecessary
parts of the second mask material layer 107.
[0054] Subsequently, there are performed a process (FIG. 7G) of
etching the second boundary layer 120 into a predetermined pattern
by using the third mask material layer 121 as a mask, and an
etching process (FIG. 7H) of etching the unnecessary parts of the
second mask material layer 107 by using the second boundary layer
120 of the predetermined pattern as a mask.
[0055] Thereafter, performed is a process (FIG. 7I), which
corresponds to the boundary layer etching process as illustrated in
FIG. 1E, for etching the boundary layer 106, and then performed is
a process (FIG. 7J) corresponding to the trimming process for
reducing a width of the first pattern 105 and a width of the second
pattern made of the second mask material layer 107 to predetermined
widths as illustrated in FIG. 1F. As a result, a pattern serving as
an etching mask is formed. Further, by using this pattern as a
mask, performed is a process (FIG. 7K), which corresponds to the
etching process as illustrated in FIG. 1G, for etching a third
layer 104 and the like as a lower layer.
[0056] As stated above, in the third embodiment, by performing the
photolithography processes two times, it is possible to form the
repeated pattern and the pattern of the peripheral circuit or the
like.
[0057] Hereinafter, by a process corresponding to the
above-described second embodiment, explained with reference to
FIGS. 8A to 8J is a fourth embodiment of forming a memory cell unit
having a repeated pattern of a narrow pitch such as a NAND-type
flash memory and a peripheral circuit electrically connected with
this memory cell unit. Further, FIGS. 8A to 8J schematically
illustrate cross-sectional configurations thereof in the upper side
and plane configurations thereof in the lower side.
[0058] In the fourth embodiment, as illustrated in FIG. 8A, during
a process corresponding to the first pattern forming process
illustrated in FIG. 4A, formed are a repeated pattern portion 501
in which a plurality of same patterns is formed at a predetermined
distance and a peripheral circuit pattern portion 502 formed at a
periphery of the repeated pattern portion 501. A part of the
peripheral circuit pattern portion 502 may be connected with the
repeated pattern portion 501.
[0059] Subsequently, as illustrated in FIGS. 8B and 8C, performed
are a boundary layer forming process (FIG. 8B) for forming a
boundary layer 106 as illustrated in FIG. 4B, and a second mask
material layer forming process (FIG. 8C) for forming a second mask
material layer 107 so that top portions of the boundary layer 106
are exposed.
[0060] Thereafter, there is performed a second boundary layer
forming process (FIG. 8D) for forming a second boundary layer 120
made of a material (e.g., SiO.sub.2 or the like), which can be
selectively removed with respect to the photoresist, on the second
mask material layer 107 and the boundary layer 106.
[0061] Then, performed is a third mask material layer forming
process (FIG. 8E) for forming a third mask material layer 121,
which is made of a photoresist formed in a predetermined pattern,
on the second boundary layer 120. The third mask material layer 121
is formed in a pattern capable of removing unnecessary parts of the
second mask material layer 107.
[0062] Subsequently, there are performed a process (FIG. 8F) of
etching the second boundary layer 120 into a predetermined pattern
by using the third mask material layer 121 as a mask, and an
etching process (FIG. 8G) of etching the unnecessary parts of the
second mask material layer 107 by using the second boundary layer
120 of the predetermined pattern as a mask.
[0063] Thereafter, performed is a process (FIG. 8H), which
corresponds to the boundary layer etching process as illustrated in
FIG. 4D, for etching the boundary layer 106, and then performed is
a process (FIG. 8I) corresponding to the trimming process for
reducing a width of the first pattern 105 and a width of the second
pattern made of the second mask material layer 107 to predetermined
widths as illustrated in FIG. 4E. As a result, a pattern serving as
an etching mask is formed. Further, by using this pattern as a
mask, performed is a process (FIG. 8J), which corresponds to the
etching process as illustrated in FIG. 4F, for etching a third
layer 104 and the like as a lower layer.
[0064] As stated above, in the fourth embodiment, by performing the
photolithography processes two times, it is possible to form the
repeated pattern and the pattern of the peripheral circuit or the
like.
[0065] The above description of the present invention is provided
for the purpose of illustration, and it would be understood by
those skilled in the art that various changes and modifications may
be made without changing technical conception and essential
features of the present invention. Thus, it is clear that the
above-described embodiments are illustrative in all aspects and do
not limit the present invention.
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