U.S. patent application number 13/288972 was filed with the patent office on 2012-11-22 for package structure and manufacturing method thereof.
This patent application is currently assigned to SUBTRON TECHNOLOGY CO. LTD.. Invention is credited to Shih-Hao Sun.
Application Number | 20120293977 13/288972 |
Document ID | / |
Family ID | 47155363 |
Filed Date | 2012-11-22 |
United States Patent
Application |
20120293977 |
Kind Code |
A1 |
Sun; Shih-Hao |
November 22, 2012 |
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Abstract
A manufacturing method of a package structure is provided. A
substrate having an upper surface and a lower surface opposite to
each other and an opening communicating the surfaces is provided.
An electronic device is configured in the opening. An adhesive
layer and a patterned metal layer located on the adhesive layer are
laminated on the lower surface and expose a bottom surface of the
electronic device. A heat-dissipating column is formed on the
bottom surface exposed by the adhesive layer and the patterned
metal layer and connects the patterned metal layer and the bottom
surface. A first and a second laminated structures are laminated on
the upper surface of the substrate and the patterned metal layer,
respectively. The first laminated structure covers the upper
surface of the substrate and a top surface of the electronic
device. The second laminated structure covers the heat-dissipating
column and the patterned metal layer.
Inventors: |
Sun; Shih-Hao; (Hsinchu
County, TW) |
Assignee: |
SUBTRON TECHNOLOGY CO. LTD.
Hsinchu
TW
|
Family ID: |
47155363 |
Appl. No.: |
13/288972 |
Filed: |
November 4, 2011 |
Current U.S.
Class: |
361/820 ;
29/592.1 |
Current CPC
Class: |
H05K 1/185 20130101;
H01L 23/13 20130101; H01L 2224/16227 20130101; H01L 24/19 20130101;
Y10T 29/49126 20150115; H01L 2924/12041 20130101; H05K 13/00
20130101; H01L 2224/16225 20130101; H01L 24/20 20130101; H01L
2924/15788 20130101; H01L 2924/15788 20130101; H01L 23/5389
20130101; Y10T 29/49002 20150115; Y10T 29/49146 20150115; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2924/12041 20130101;
H05K 1/0207 20130101 |
Class at
Publication: |
361/820 ;
29/592.1 |
International
Class: |
H05K 7/00 20060101
H05K007/00; H05K 13/00 20060101 H05K013/00 |
Foreign Application Data
Date |
Code |
Application Number |
May 20, 2011 |
TW |
100117788 |
Claims
1. A manufacturing method of a package structure, comprising:
providing a substrate, the substrate having an upper surface, a
lower surface, and an opening, the upper surface and the lower
surface being opposite to each other, the opening communicating the
upper surface and the lower surface; configuring an electronic
device in the opening of the substrate; laminating an adhesive
layer and a patterned metal layer located on the adhesive layer on
the lower surface of the substrate, the adhesive layer and the
patterned metal layer exposing a bottom surface of the electronic
device; forming a heat-dissipating column on the bottom surface of
the electronic device exposed by the adhesive layer and the
patterned metal layer, the heat-dissipating column connecting the
patterned metal layer and the bottom surface of the electronic
device; and respectively laminating a first laminated structure and
a second laminated structure on the upper surface of the substrate
and the patterned metal layer, the first laminated structure
covering the upper surface of the substrate and a top surface of
the electronic device, the second laminated structure covering the
heat-dissipating column and the patterned metal layer.
2. The manufacturing method of the package structure as recited in
claim 1, wherein the electronic device comprises a radio frequency
device, an active device, or a passive device.
3. The manufacturing method of the package structure as recited in
claim 1, wherein the first laminated structure comprises at least
one first dielectric layer, at least one first patterned metal
layer, and at least one conductive via penetrating the at least one
first dielectric layer, the at least one first dielectric layer and
the at least one first patterned metal layer are sequentially
stacked on the upper surface of the substrate, the opening is
filled with the at least one first dielectric layer, and the at
least one first patterned metal layer is electrically connected to
the electronic device through the at least one conductive via.
4. The manufacturing method of the package structure as recited in
claim 1, wherein the second laminated structure comprises at least
one second dielectric layer and at least one second patterned metal
layer, the at least one second dielectric layer and the at least
one second patterned metal layer are stacked on the patterned metal
layer and the heat-dissipating column, and the heat-dissipating
column is in physical contact with the at least one second
patterned metal layer.
5. The manufacturing method of the package structure as recited in
claim 1, after laminating the first laminated structure and the
second laminated structure on the upper surface of the substrate
and the patterned metal layer, further comprising: forming a first
solder mask layer on the first laminated structure; and forming a
second solder mask layer on the second laminated structure.
6. The manufacturing method of the package structure as recited in
claim 1, wherein a method of laminating the first laminated
structure and the second laminated structure on the upper surface
of the substrate and the patterned metal layer comprises thermal
lamination.
7. The manufacturing method of the package structure as recited in
claim 1, wherein a method of forming the heat-dissipating column on
the bottom surface of the electronic device exposed by the adhesive
layer and the patterned metal layer comprises plating.
8. A package structure, comprising: a substrate having an upper
surface, a lower surface, and an opening, the upper surface and the
lower surface being opposite to each other, the opening
communicating the upper surface and the lower surface; an
electronic device configured in the opening of the substrate and
having a top surface and a bottom surface, the top surface and the
bottom surface being opposite to each other; an adhesive layer
configured on the lower surface of the substrate and exposing the
bottom surface of the electronic device; a patterned metal layer
adhered to the lower surface of the substrate through the adhesive
layer and exposing the bottom surface of the electronic device; a
heat-dissipating column configured on the bottom surface of the
electronic device exposed by the adhesive layer and the patterned
metal layer, the heat-dissipating column connecting the patterned
metal layer and the bottom surface of the electronic device; a
first laminated structure configured on the upper surface of the
substrate and covering the upper surface of the substrate and the
top surface of the electronic device; and a second laminated
structure configured on the patterned metal layer and covering the
heat-dissipating column and the patterned metal layer.
9. The package structure as recited in claim 8, wherein the
electronic device comprises a radio frequency device, an active
device, or a passive device.
10. The package structure as recited in claim 8, wherein the first
laminated structure comprises at least one first dielectric layer,
at least one first patterned metal layer, and at least one
conductive via penetrating the at least one first dielectric layer,
the at least one first dielectric layer and the at least one first
patterned metal layer are sequentially stacked on the upper surface
of the substrate, the opening is filled with the at least one first
dielectric layer, and the at least one first patterned metal layer
is electrically connected to the electronic device through the at
least one conductive via.
11. The package structure as recited in claim 8, wherein the second
laminated structure comprises at least one second dielectric layer
and at least one second patterned metal layer, the at least one
second dielectric layer and the at least one second patterned metal
layer are stacked on the patterned metal layer and the
heat-dissipating column, and the heat-dissipating column is in
physical contact with the at least one second patterned metal
layer.
12. The package structure as recited in claim 8, further
comprising: a first solder mask layer configured on the first
laminated structure; and a second solder mask layer configured on
the second laminated structure.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application serial no. 100117788, filed on May 20, 2011. The
entirety of the above-mentioned patent application is hereby
incorporated by reference herein and made a part of this
specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to a package structure and a
manufacturing method thereof. More particularly, the invention
relates to a package structure with an embedded device and a
manufacturing method of the package structure.
[0004] 2. Description of Related Art
[0005] In recent years, electronic devices are frequently installed
in a circuit board for improving electrical properties of the
electronic devices, which is known as a system-in-package (SIP)
structure. The SIP structure is referred to as a system integration
package. Namely, the electronic devices are integrated into a
single package in which passive devices, memories, electronic
connectors, and other embedded devices are included. A variety of
manufacturing methods can be applied to the SIP structure made of
various materials. After the electronic devices are configured
within the circuit board, conductive layers are stacked on the
circuit board by applying a build-up method, so as to assemble the
circuit board that has multiple layers.
[0006] Nevertheless, the SIP structure has a relatively complicated
structure notwithstanding the fact that the SIP structure can
effectively reduce package area and initially integrate the system.
Moreover, in comparison with a single chip package, the SIP
structure encounters more challenges with respect to its design for
heat dissipation and maintenance of electrical reliability. Since
the embedded devices are embedded in the multi-layer circuit board,
the heat generated by the embedded devices is required to be
dissipated out of the circuit board by means of a metal conductive
layer and an insulating layer. That is to say, the package
structure containing the conventional embedded devices can achieve
limited heat-dissipating effects. Thereby, other devices in the
package structure may not be normally functioned due to the
excessive operational temperature, and the electrical performance
or reliability of the package structure is further
deteriorated.
SUMMARY OF THE INVENTION
[0007] The invention is directed to a package structure that has an
embedded electronic device. The package structure can accomplish
favorable heat-dissipating effects and have small package
volume.
[0008] The invention is further directed to a manufacturing method
of a package structure. By applying the manufacturing method, the
aforesaid package structure can be formed.
[0009] In an embodiment of the invention, a manufacturing method of
a package structure is provided. In the manufacturing method, a
substrate is provided. The substrate has an upper surface, a lower
surface, and an opening. The upper surface and the lower surface
are opposite to each other, and the opening communicates the upper
surface and the lower surface. An electronic device is configured
in the opening. An adhesive layer and a patterned metal layer that
is located on the adhesive layer are laminated on the lower surface
of the substrate. Besides, the adhesive layer and the patterned
metal layer expose a bottom surface of the electronic device. A
heat-dissipating column is formed on the bottom surface of the
electronic device exposed by the adhesive layer and the patterned
metal layer. Here, the heat-dissipating column connects the
patterned metal layer and the bottom surface of the electronic
device. A first laminated structure and a second laminated
structure are respectively laminated on the upper surface of the
substrate and the patterned metal layer. The first laminated
structure covers the upper surface of the substrate and a top
surface of the electronic device, and the second laminated
structure covers the heat-dissipating column and the patterned
metal layer.
[0010] According to an embodiment of the invention, the electronic
device includes a radio frequency (RF) device, an active device, or
a passive device.
[0011] According to an embodiment of the invention, the first
laminated structure includes at least one first dielectric layer,
at least one first patterned metal layer, and at least one
conductive via that penetrates the first dielectric layer. The
first dielectric layer and the first patterned metal layer are
sequentially stacked on the upper surface of the substrate. The
opening is filled with the first dielectric layer. The first
patterned metal layer is electrically connected to the electronic
device through the conductive via.
[0012] According to an embodiment of the invention, the second
laminated structure includes at least one second dielectric layer
and at least one second patterned metal layer. The second
dielectric layer and the second patterned metal layer are stacked
on the patterned metal layer and the heat-dissipating column. The
heat-dissipating column is in physical contact with the second
patterned metal layer.
[0013] According to an embodiment of the invention, after the first
laminated structure and the second laminated structure are
laminated on the upper surface of the substrate and the patterned
metal layer, the manufacturing method further includes forming a
first solder mask layer on the first laminated structure and
forming a second solder mask layer on the second laminated
structure.
[0014] According to an embodiment of the invention, a method of
laminating the first laminated structure and the second laminated
structure on the upper surface of the substrate and the patterned
metal layer includes thermal lamination.
[0015] According to an embodiment of the invention, a method of
forming the heat-dissipating column on the bottom surface of the
electronic device exposed by the adhesive layer and the patterned
metal layer includes plating.
[0016] In an embodiment of the invention, a package structure that
includes a substrate, an electronic device, an adhesive layer, a
patterned metal layer, a heat-dissipating column, a first laminated
structure, and a second laminated structure is provided. The
substrate has an upper surface, a lower surface, and an opening.
The upper surface and the lower surface are opposite to each other,
and the opening communicates the upper surface and the lower
surface. The electronic device is configured in the opening of the
substrate and has a top surface and a bottom surface. The top
surface and the bottom surface are opposite to each other. The
adhesive layer is configured on the lower surface of the substrate
and exposes the bottom surface of the electronic device. The
patterned metal layer is adhered to the lower surface of the
substrate through the adhesive layer and exposes the bottom surface
of the electronic device. The heat-dissipating column is configured
on the bottom surface of the electronic device exposed by the
adhesive layer and the patterned metal layer. Here, the
heat-dissipating column connects the patterned metal layer and the
bottom surface of the electronic device. The first laminated
structure is configured on the upper surface of the substrate and
covers the upper surface of the substrate and the top surface of
the electronic device. The second laminated structure is configured
on the patterned metal layer and covers the heat-dissipating column
and the patterned metal layer.
[0017] According to an embodiment of the invention, the electronic
device includes an RF device, an active device, or a passive
device.
[0018] According to an embodiment of the invention, the first
laminated structure includes at least one first dielectric layer,
at least one first patterned metal layer, and at least one
conductive via that penetrates the first dielectric layer. The
first dielectric layer and the first patterned metal layer are
sequentially stacked on the upper surface of the substrate. The
opening is filled with the first dielectric layer. The first
patterned metal layer is electrically connected to the electronic
device through the conductive via.
[0019] According to an embodiment of the invention, the second
laminated structure includes at least one second dielectric layer
and at least one second patterned metal layer. The second
dielectric layer and the second patterned metal layer are stacked
on the patterned metal layer and the heat-dissipating column. The
heat-dissipating column is in physical contact with the second
patterned metal layer.
[0020] According to an embodiment of the invention, the package
structure further includes a first solder mask layer and a second
solder mask layer. The first solder mask layer is configured on the
first laminated structure. The second solder mask layer is
configured on the second laminated structure.
[0021] Based on the above, the electronic device described in the
embodiments of the invention is embedded in the substrate and the
laminated structures, and the bottom surface of the electronic
device is in physical contact with the heat-dissipating column.
Hence, the heat generated by the electronic device in use can be
dissipated by means of the underlying heat-dissipating column and
the patterned metal layer, such that the package structure can
accomplish favorable heat-dissipating effects. Moreover, since the
electronic device is embedded in the substrate and the laminated
structures, the package structure described in the embodiments of
the invention can have small package volume and thin thickness.
[0022] Several exemplary embodiments accompanied with figures are
described in detail below to further describe the invention in
details.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The accompanying drawings are included to provide a further
understanding of the disclosure, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the disclosure and, together with the description,
serve to explain the principles of the invention.
[0024] FIG. 1A to FIG. 1G are schematic cross-sectional views
illustrating a manufacturing method of a package structure
according to an embodiment of the invention.
[0025] FIG. 1H is a schematic cross-sectional view illustrating
that the package structure depicted in FIG. 1G carries a chip.
DESCRIPTION OF EMBODIMENTS
[0026] FIG. 1A to FIG. 1G are schematic cross-sectional views
illustrating a manufacturing method of a package structure
according to an embodiment of the invention. As indicated in FIG.
1A, according to the manufacturing method of a package structure in
this embodiment, a substrate 110 is provided. The substrate 110 has
an upper surface 111 and a lower surface 113 opposite to the upper
surface 111. The substrate 110 is constituted by an insulating
layer 112 and a copper foil layer 114, for instance, and the
insulating layer 112 is made of polyimide (PI) or epoxy resin, for
instance. In other embodiments that are not shown in the drawings,
the substrate can also be a double-sided board that is constituted
by one insulating layer and two copper foil layers that are located
at two respective sides of the insulating layer, or the substrate
can be a glass fiber (FR4) substrate, which should not be construed
as a limitation to the invention.
[0027] With reference to FIG. 1B, an opening 116 that communicates
the upper surface 111 and the lower surface 113 of the substrate
110 is formed by stamping or routing, for instance.
[0028] With reference to FIG. 1C, an electronic device 120 is
configured in the opening 116 of the substrate 110. The diameter of
the opening 116 of the substrate 110 is greater than the diameter
of the electronic device 120. The electronic device 120 has a top
surface 122 and a bottom surface 124 opposite to the top surface
122, and the electronic device 120 can be temporarily fixed into
the opening 116 through an adhesive (not shown) that is configured
on the upper surface 111 of the substrate 110. Here, the electronic
device 120 is an RF device, an active device, a passive device, a
memory, or an electronic connector, for instance.
[0029] With reference to FIG. 1D, an adhesive layer 130 and a metal
layer 140a that is located on the adhesive layer 130 are laminated
on the lower surface 113 of the substrate 110. Here, the adhesive
layer 130 and the metal layer 140a are laminated on the lower
surface 113 of the substrate 110 by thermal lamination, for
instance. At this time, the adhesive layer 130 and the metal layer
140a are conformally configured. A blind hole H that penetrates the
adhesive layer 130 and the metal layer 140a is formed by mechanical
drilling, such that the adhesive layer 130 and the metal layer 140a
expose a portion of the bottom surface 124 of the electronic device
120. The adhesive (not shown) located on the upper surface 111 of
the substrate 110 is removed to expose the copper foil layer
114a.
[0030] With reference to FIG. 1 E, the copper foil layer 114a of
the substrate 110 and the metal layer 140a are patterned to form a
patterned copper foil layer 114 and a patterned metal layer 140.
The patterned copper foil layer 114 exposes a portion of the
surface of the insulating layer 112, and the patterned metal layer
140 exposes a portion of the adhesive layer 130.
[0031] As indicated in FIG. 1E, a heat-dissipating column 150 is
formed in the blind hole H. Namely, the heat-dissipating column 150
is located on the portion of the bottom surface 124 of the
electronic device 120 exposed by the adhesive layer 130 and the
patterned metal layer 140. Here, the heat-dissipating column 150 is
formed by plating, for instance, and the plating process can
effectively enhance both the adhesion between the heat-dissipating
column 150 and the patterned metal layer 140 and the adhesion
between the heat-dissipating column 150 and the electronic device
120.
[0032] With reference to FIG. 1F, a first laminated structure 160
and a second laminated structure 170 are respectively laminated on
the upper surface 111 of the substrate 110 and the patterned metal
layer 140. The first laminated structure 160 covers the upper
surface 111 of the substrate 110 and the top surface 122 of the
electronic device 120, and the second laminated structure 170
covers the heat-dissipating column 150 and the patterned metal
layer 140. The first laminated structure 160 and the second
laminated structure 170 are respectively laminated on the upper
surface 111 of the substrate 110 and the patterned metal layer 140
by thermal lamination, for instance.
[0033] To be more specific, the first laminated structure 160
described in this embodiment includes at least one first dielectric
layer 162, at least one first metal layer 164a, and at least one
conductive via 166 that penetrates the first dielectric layer 162.
In FIG. 1F, one first dielectric layer 162, one first metal layer
164a, and two conductive vias 166 are schematically shown. The
first dielectric layer 162 and the first metal layer 164a are
sequentially stacked on the upper surface 111 of the substrate 110.
The opening 116 is filled with the first dielectric layer 162 that
is melted by heat, and thereby the electronic device 120 can be
fixed into the opening 116. The first metal layer 164a can be
electrically connected to the electrodes (not shown) located on the
top surface 122 of the electronic device 120 through the conductive
vias 166.
[0034] The second laminated structure 170 includes at least one
second dielectric layer 172, at least one second metal layer 174a,
and a second patterned metal layer 176. In FIG. 1F, one second
dielectric layer 172 and one second metal layer 174a are
schematically shown. The second dielectric layer 172, the second
metal layer 174a, and the second patterned metal layer 176 are
stacked on the patterned metal layer 140 and the heat-dissipating
column 150. Here, the second dielectric layer 172 is located
between the second metal layer 174a and the second patterned metal
layer 176, and the heat-dissipating column 150 is in physical
contact with the second patterned metal layer 176.
[0035] With reference to FIG. 1G, the first metal layer 164a of the
first laminated structure 160 and the second metal layer 174a of
the second laminated structure 170 are patterned to form a first
patterned metal layer 164 and a second patterned metal layer 174. A
first solder mask layer 180 is formed on the first laminated
structure 160, and a second solder mask layer 190 is formed on the
second laminated structure 170. Here, the first solder mask layer
180 exposes a portion of the first patterned metal layer 164, and
the second solder mask layer 190 exposes a portion of the second
patterned metal layer 174. So far, the fabrication of the package
structure 100 is substantially completed.
[0036] As indicated in FIG. 1G, the package structure 100 includes
the substrate 110, the electronic device 120, the adhesive layer
130, the patterned metal layer 140, the heat-dissipating column
150, the first laminated structure 160, the second laminated
structure 170, the first solder mask layer 180, and the second
solder mask layer 190. The substrate 110 has the upper surface 111,
the lower surface 113 opposite to the upper surface 111, and the
opening 116 that communicates the upper surface 111 and the lower
surface 113. Here, the substrate 110 is constituted by the
insulating layer 112 and the patterned copper foil layer 114, for
instance. The electronic device 120 is configured in the opening
116 of the substrate 110 and has the top surface 122 and the bottom
surface 124. The top surface 122 and the bottom surface 124 of the
electronic device 120 are opposite to each other. Here, the
electronic device 120 includes an RF device, an active device, a
passive device, a memory, or an electronic connector. The adhesive
layer 130 is configured on the lower surface 113 of the substrate
110 and exposes a portion of the bottom surface 124 of the
electronic device 120. The patterned metal layer 140 is adhered to
the lower surface 113 of the substrate 110 through the adhesive
layer 130 and exposes the portion of the bottom surface 124 of the
electronic device 120. The heat-dissipating column 150 is
configured on the portion of the bottom surface 124 of the
electronic device 120 exposed by the adhesive layer 130 and the
patterned metal layer 140. That is to say, the heat-dissipating
column 150 is configured in the blind hole H that penetrates the
adhesive layer 130 and the patterned metal layer 140. Here, the
heat-dissipating column 150 connects the patterned metal layer 140
and the bottom surface 124 of the electronic device 120.
[0037] The first laminated structure 160 is configured on the upper
surface 111 of the substrate 110 and covers the upper surface 111
of the substrate 110 and the top surface 122 of the electronic
device 120. Here, the first laminated structure 160 is constituted
by the first dielectric layer 162, the first patterned metal layer
164a, and the conductive vias 166 that penetrate the first
dielectric layer 162. The first dielectric layer 162 and the first
patterned metal layer 164 are sequentially stacked on the upper
surface 111 of the substrate 110. The opening 116 is filled with
the first dielectric layer 162. The first patterned metal layer 164
is electrically connected to the electronic device 120 through the
conductive vias 166. The second laminated structure 170 is
configured on the patterned metal layer 140 and covers the
heat-dissipating column 150 and the patterned metal layer 140.
Here, the second laminated structure 170 is constituted by the
second dielectric layer 172 and the second patterned metal layers
174 and 176. The second dielectric layer 172 and the second
patterned metal layers 174 and 176 are stacked on the patterned
metal layer 140 and the heat-dissipating column 150, and the
heat-dissipating column 150 is in physical contact with the second
patterned metal layer 176. The first solder mask layer 180 is
configured on the first laminated structure 160 and exposes a
portion of the first patterned metal layer 164. The second solder
mask layer 190 is configured on the second laminated structure 170
and exposes a portion of the second patterned metal layer 174.
[0038] The electronic device 120 described in this embodiment is
embedded in the substrate 110, the first laminated structure 160,
and the second laminated structure 170, and the bottom surface 124
of the electronic device 120 is in physical contact with the
heat-dissipating column 150. Therefore, the heat generated by the
electronic device 120 can be dissipated by the underlying
heat-dissipating column 150, the second patterned metal layer 176,
and the second patterned metal layer 174. As such, the package
structure 100 of this embodiment can achieve favorable
heat-dissipating effects. Besides, since the electronic device 120
is embedded in the substrate 110, the first laminated structure
160, and the second laminated structure 170, the package structure
100 can have small package volume and thin thickness. Further, the
diameter of the opening 116 of the substrate 110 is greater than
the diameter of the electronic device 120. Hence, when the
electronic device 120 is configured in the opening 116 of the
substrate 110, the favorable process window can be provided.
[0039] FIG. 1H is a schematic cross-sectional view illustrating
that the package structure depicted in FIG. 1G carries a chip. With
reference to FIG. 1H, the first patterned metal layer 164 and the
second patterned metal layer 174 are configured on the outer
surface of the package structure 100 in this embodiment.
Accordingly, the package structure 100 can be electrically
connected to a chip 10 through the first patterned metal layer 164,
and the second patterned metal layer 174 can be electrically
connected to an external circuit (not shown). Thereby, the
applicability of the package structure 100 can be improved. The
chip 10 is a semiconductor integrated circuit chip or a light
emitting diode (LED) chip, which should not be construed as a
limitation to the invention.
[0040] In particular, the chip 10 can be electrically connected to
the first patterned metal layer 164 of the package structure 100 by
flip-chip bonding, or the chip 10 and a portion of the package
structure 100 can be encapsulated by an encapsulant 20, so as to
protect the electrical connection between the chip 10 and the
package structure 100. Although the chip 10 in this embodiment is
electrically connected to the first patterned metal layer 164 of
the package structure 100 by flip-chip bonding, it should be
mentioned that the way to bond the chip 10 and the package
structure 100 and the type of the chip 10 are not limited in the
invention. However, in other embodiments that are not shown in the
drawings, the chip can be electrically connected to the first
patterned metal layer of the package structure by wire bonding
through a plurality of bonding wires. The way to bond the chip 10
and the package structure 100 and the type of the chip 10 are
exemplary and should not be construed as limitations to the
invention.
[0041] In light of the foregoing, the electronic device described
in the embodiments of the invention is embedded in the substrate
and the laminated structures, and the bottom surface of the
electronic device is in physical contact with the heat-dissipating
column. Hence, the heat generated by the electronic device in use
can be dissipated by means of the underlying heat-dissipating
column and the patterned metal layer, such that the package
structure can accomplish favorable heat-dissipating effects.
Moreover, since the electronic device is embedded in the substrate
and the laminated structures, the package structure described in
the embodiments of the invention can have small package volume and
thin thickness.
[0042] Further, the package metal layer is configured on the outer
surface of the package structure as described in the embodiments of
the invention, and thus the package structure discussed herein can
be electrically connected to an electronic device or an external
circuit through the patterned metal layer, thus improving the
applicability of the package structure. In addition, the diameter
of the opening of the substrate is greater than the diameter of the
electronic device. Hence, when the electronic device is configured
in the opening of the substrate, the favorable process window can
be provided.
[0043] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
disclosed embodiments without departing from the scope or spirit of
the invention. In view of the foregoing, it is intended that the
disclosure cover modifications and variations of this specification
provided they fall within the scope of the following claims and
their equivalents.
* * * * *