U.S. patent application number 13/112317 was filed with the patent office on 2012-11-22 for corner transistor suppression.
This patent application is currently assigned to GLOBALFOUNDRIES Singapore Pte.Ltd.. Invention is credited to Ying Keung Leung, Elgin Quek, Shyue Seng (Jason) Tan.
Application Number | 20120292735 13/112317 |
Document ID | / |
Family ID | 47174334 |
Filed Date | 2012-11-22 |
United States Patent
Application |
20120292735 |
Kind Code |
A1 |
Tan; Shyue Seng (Jason) ; et
al. |
November 22, 2012 |
CORNER TRANSISTOR SUPPRESSION
Abstract
The threshold voltage of parasitic transistors formed at corners
of shallow trench isolation regions is increased and mobility
decreased by employing a high-K dielectric material. Embodiments
include STI regions comprising a liner of a high-K dielectric
material extending proximate trench corners. Embodiments also
include STI regions having a recess formed in the trench, wherein
the recess contains a high-K dielectric material, in the form of a
layer or spacer, extending proximate trench corners.
Inventors: |
Tan; Shyue Seng (Jason);
(Singapore, SG) ; Leung; Ying Keung; (Singapore,
SG) ; Quek; Elgin; (Singapore, SG) |
Assignee: |
GLOBALFOUNDRIES Singapore
Pte.Ltd.
Singapore
SG
|
Family ID: |
47174334 |
Appl. No.: |
13/112317 |
Filed: |
May 20, 2011 |
Current U.S.
Class: |
257/506 ;
257/499; 257/E21.24; 257/E29.02; 257/E29.169; 438/435 |
Current CPC
Class: |
H01L 29/0653 20130101;
H01L 27/088 20130101; H01L 21/823481 20130101; H01L 21/76232
20130101; H01L 21/76224 20130101 |
Class at
Publication: |
257/506 ;
438/435; 257/499; 257/E21.24; 257/E29.02; 257/E29.169 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 29/68 20060101 H01L029/68; H01L 21/31 20060101
H01L021/31 |
Claims
1. A method comprising: forming a trench, having side surfaces and
a bottom surface, in a substrate; forming an oxide liner on the
side surfaces and bottom surface of the trench; and forming a layer
of high-K dielectric material on the oxide liner.
2. The method according to claim 1, further comprising filling the
trench with an insulating material.
3. The method according to claim 1, wherein the substrate comprises
a semiconductor material, the method further comprising: forming a
pad oxide layer on an upper surface of the substrate; and forming a
pad nitride layer on the pad oxide layer, both prior to forming the
trench in the substrate; filling the trench with insulating
material forming an overburden on the pad nitride layer subsequent
to forming the layer of high-K dielectric material; and planarizing
such that an upper surface of the insulating material is
substantially coplanar with an upper surface of the pad nitride
layer, wherein the layer of high-K dielectric material extends
proximate corners of the trench.
4. The method according to claim 3, further comprising: removing
the pad oxide and pad nitride layers from the upper surface of the
substrate, leaving the filled trench as a trench isolation region;
and forming transistors on the substrate separated by the trench
isolation region, wherein, the layer of high-K dielectric material
increases a threshold voltage of and lowers mobility of a parasitic
transistor formed at a trench corner.
5. A method comprising: forming a trench, having corners, side
surfaces, and a bottom surface, in a substrate having an upper
surface; filling the trench with an insulating material; removing
insulating material from the trench to form a recess therein
extending below the upper surface of the substrate; and providing a
high-K dielectric material in the recess.
6. The method according to claim 5, further comprising forming an
oxide liner on the side surfaces and bottom surface of the
trench.
7. The method according to claim 6, comprising providing the high-K
dielectric material in the form of a layer proximate a trench
corner.
8. The method according to claim 6, comprising providing the high-K
dielectric material in the form of a spacer proximate a trench
corner.
9. The method according to claim 6, wherein the substrate comprises
a semiconductor material, the method further comprising: forming a
pad oxide layer on the upper surface of the substrate; and forming
a pad nitride layer on the pad oxide layer, both prior to forming
the trench in the substrate; filling the trench with insulating
material forming an overburden of insulating material on the pad
nitride layer; and planarizing such that an upper surface of the
insulating material is substantially coplanar with an upper surface
of the pad nitride layer; providing a high-K dielectric material in
the recess by: forming a layer of the high-K dielectric material
over the pad nitride layer and filling the recess; and removing
portions of the high-K dielectric material from over the pad
nitride layer leaving the high-K dielectric material in the recess
with an upper surface which is substantially coplanar with the
upper surface of the substrate, wherein the high-K dielectric
material in the recess extends proximate corners of the trench.
10. The method according to claim 9, further comprising: removing
the pad oxide and pad nitride layers from the upper surface of the
substrate, leaving the filled trench as a trench isolation region;
and forming transistors on the substrate separated by the trench
isolation region, wherein, the high-K dielectric material in the
recess increases a threshold voltage of and lowers mobility of a
parasitic transistor formed at a trench corner.
11. The method according to claim 10, comprising providing the
high-K dielectric material in the recess in the form of a
layer.
12. The method according to claim 10, comprising providing the
high-K dielectric material in the recess in the form of a
spacer.
13. A semiconductor device comprising a trench isolation region
formed in a substrate, the trench isolation region comprising: a
trench having corners, side surfaces, and a bottom surface; an
oxide liner on the side surfaces and bottom surface of the trench;
a layer of high-K dielectric material on the oxide liner extending
proximate trench corners; and insulating material filling the
trench.
14. The semiconductor device according to claim 13, further
comprising transistors on the substrate separated by the trench
isolation region, wherein the layer of high-K dielectric material
increases a threshold voltage of and lowers mobility of a parasitic
transistor formed at a trench corner.
15. A semiconductor device comprising trench isolation region
formed in a substrate, the substrate having an upper surface, the
trench isolation region comprising: a trench having corners, side
surfaces, and a bottom surface; insulating material filling the
trench; a recess in the insulating material extending below the
upper surface of the substrate; and a high-K dielectric material in
the recess extending proximate trench corners.
16. The semiconductor device according to claim 15, further
comprising an oxide liner on the side surfaces and bottom surface
of the trench.
17. The semiconductor device according to claim 16, further
comprising transistors on the substrate separated by the trench
isolation region, wherein the high-K dielectric material in the
recess increases a threshold voltage of and lowers mobility of a
parasitic transistor formed at a trench corner.
18. The semiconductor device according to claim 17, wherein the
high-K dielectric material in the recess is in the form of a
layer.
19. The semiconductor device according to claim 17, wherein the
high-K dielectric material in the recess is in the form of a
spacer.
20. A semiconductor device comprising: transistors formed in a
substrate; and a trench isolation region formed between the
transistors, the trench isolation region containing means for
increasing a threshold voltage of and lowering mobility of a
parasitic transistor formed at a trench corner.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to semiconductor devices
containing trench isolation regions and exhibiting increased device
performance, yield, and reliability. The present disclosure is
particularly applicable to fabricating semiconductor devices with
reduced parasitic leakage and improved transistor on current to
transistor off current (Ion-Ioff) performance.
BACKGROUND
[0002] As technological advances plunge deeper into submicron
geometries, shallow trench isolation (STI) is replacing local
oxidation of silicon (LOCOS) processes for the formation of
isolation structures. STI processes advantageously allow for
planarization of the entire substrate and isolation structure,
thereby providing better control of a critical dimension (CD),
e.g., when defining the gate stack of a transistor.
[0003] Conventional STI processing includes forming a pad oxide
layer on a substrate, forming a pad nitride layer over the pad
oxide layer, and forming a trench through the pad oxide and nitride
layers in the substrate, as by reactive ion etching (RIE). A liner
oxide is then thermally grown to anneal out any damage to and to
passivate the substrate. The trench is then filled with an
insulating material, typically an oxide, followed by
chemical-mechanical polishing (CMP) such that the upper surface of
the filled trench is substantially coplanar with the upper surface
of the pad nitride layer. The pad nitride and oxide layers are then
stripped resulting in the STI structure. Subsequent conventional
processing includes forming transistors spaced apart by the
STI.
[0004] In implementing STI, sharp corners are typically formed
where the trench sidewall intersects the top surface of the
substrate, adversely impacting device performance, yield, and
liability. Typically, a parasitic transistor having a relatively
low threshold voltage is formed at the trench corner. Such
parasitic transistors result in a high leakage issues and degrade
Ion-Ioff performance, in addition to increasing linear threshold
voltage (Vtlin) mismatch. Conventional approaches to the parasitic
transistor issue involve rounding the transistor corner in
attempting to reduce the electric field, and additional field
implants to increase the threshold voltage of the parasitic
transistor. Such approaches have not met with complete success,
become increasingly more difficult as geometries plunge, and
adversely impact STI efficacy.
[0005] A need therefore exists for methodology enabling the
fabrication of semiconductor devices having STI structures with
reduced leakage current, reduced degradation of Ion-Ioff
performance, and reduced Vtlin mismatch. A particular need exists
for methodology enabling the fabrication of semiconductor devices
with CDs in the deep submicron range, wherein parasitic transistors
formed at trench corners exhibit an increased threshold voltage and
reduced mobility.
SUMMARY
[0006] An aspect of the present disclosure is a method of
fabricating a semiconductor device having STI regions, wherein
parasitic transistors formed at trench corners exhibit an increased
threshold voltage and reduced mobility.
[0007] Another aspect of the present disclosure is a semiconductor
device having STI regions wherein parasitic transistors formed at
trench corners exhibit an increased threshold voltage and reduced
mobility.
[0008] Additional aspects and other features of the present
disclosure will be set forth in the description which follows and
in part will be apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the present disclosure. The advantages of the present
disclosure may be realized and obtained as particularly pointed out
in the appended claims.
[0009] Aspects of the present disclosure include forming a trench,
having side surfaces and a bottom surface, in a substrate; forming
an oxide liner on the side surfaces and bottom surface of the
trench; and forming a layer of high-K dielectric material on the
oxide liner. Additional aspects include sequentially forming a pad
oxide layer on an upper surface of the substrate; forming a pad
nitride layer on the pad oxide layer; forming the trench in the
substrate; filling the trench with insulating material forming an
overburden on the pad nitride layer; and planarizing such that an
upper surface of the insulating material is substantially coplanar
with an upper surface of the pad nitride layer, wherein the layer
of high-K dielectric material extends proximate corners of the
trench. Further aspects include removing the pad oxide and pad
nitride layers from the upper surface of the substrate, leaving the
filled trench as a STI region; and forming transistors on the
substrate separated by the STI region, wherein, the layer of high-K
dielectric material increases the threshold voltage of and lowers
the mobility of a parasitic transistor formed at a trench
corner.
[0010] Other aspects of the present disclosure include forming a
trench, having corners, side surfaces, and a bottom surface, in a
substrate having an upper surface; filling the trench with an
insulating material; removing insulating material from the trench
to form a recess therein extending below the upper surface of the
substrate; and providing a high-K dielectric material in the
recess. Additional aspects include forming an oxide liner on the
side surfaces and bottom surface of the trench before filling the
trench with insulating material. Further aspects include providing
the high-K dielectric material in the form of a layer or a spacer
proximate a trench corner. Aspects also include sequentially
forming a pad oxide layer on the upper surface of the substrate;
forming a pad nitride layer on the pad oxide layer; forming the
trench in the substrate; forming an oxide liner in the trench
filling the trench with insulating material forming an overburden
on the pad nitride layer; planarizing such that an upper surface of
the insulating material is substantially coplanar with an upper
surface of the pad nitride layer; forming a layer of the high-K
dielectric material over the pad nitride layer and filling the
recess; and removing portions of the high-K dielectric material
from over the pad nitride layer leaving the high-K dielectric
material in the recess with an upper surface which is substantially
coplanar with the upper surface of the substrate, wherein the
high-K dielectric material in the recess extends proximate corners
of the trench. A further aspect includes etching the layer of
high-K dielectric material in the recess to form a high-K spacer
proximate the trench corners and a sub-recess, then refilling the
trench sub-recess with insulating material. Additional aspects
include removing the pad nitride and pad oxide layers from the
upper surface of the substrate, leaving the filled trench as a STI
region; and forming transistors on the substrate separated by the
STI region, wherein, the high-K dielectric material in the recess
increases the threshold voltage of and lowers the mobility of a
parasitic transistor formed at a trench corner.
[0011] Another aspect of the present disclosure includes a
semiconductor device comprising a trench isolation region formed in
a substrate, the trench isolation region comprising: a trench
having corners, side surfaces, and a bottom surface; an oxide liner
on the side surfaces and bottom surface of the trench; a layer of
high-K dielectric material on the oxide liner extending proximate
trench corners; and insulating material filling the trench. Aspects
include a semiconductor device comprising transistors on the
substrate separated by the trench isolation region, wherein the
layer of high-K dielectric material increases the threshold voltage
of and lowers the mobility of a parasitic transistor formed at a
trench corner.
[0012] A further aspect of the present disclosure includes a
semiconductor device comprising a trench isolation region formed in
a substrate, the substrate having an upper surface, the trench
isolation region comprising a trench having corners, side surfaces,
and a bottom surface; insulating material filling the trench; a
recess in the insulating material extending below the upper surface
of the substrate; and a high-K dielectric material in the recess
extending proximate trench corners, wherein the high-K dielectric
material in the recess is in the form of a layer or spacer
proximate trench corners and increases the threshold voltage of and
lowers the mobility of a parasitic transistor formed at a trench
corner.
[0013] Another further aspect of the present disclosure includes a
semiconductor device comprising transistors formed in a substrate;
and a trench isolation region formed between the transistors, the
trench isolation region containing means for increasing the
threshold voltage of and lowering the mobility of a parasitic
transistor formed at a trench corner.
[0014] Additional aspects and technical effects of the present
disclosure will become readily apparent to those skilled in the art
from the following detailed description wherein embodiments of the
present disclosure are described simply by way of illustration of
the best mode contemplated to carry out the present disclosure. As
will be realized, the present disclosure is capable of other and
different embodiments, and its several details are capable of
modifications in various obvious respects, all without departing
from the present disclosure. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The present disclosure is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawing and in which like reference numerals refer to similar
elements and in which:
[0016] FIGS. 1A through 1H illustrate sequential steps in
accordance with an embodiment of the present disclosure; and
[0017] FIGS. 2A through 2I schematically illustrate sequential
steps in accordance with another embodiment of the present
disclosure.
[0018] FIGS. 3A through 3E schematically illustrate sequential
steps in accordance with a further embodiment of the present
disclosure.
DETAILED DESCRIPTION
[0019] In the following description, for the purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of exemplary embodiments. It
should be apparent, however, that exemplary embodiments may be
practiced without these specific details or with an equivalent
arrangement. In other instances, well-known structures and devices
are not shown to avoid unnecessarily obscuring exemplary
embodiments. In addition, unless otherwise indicated, all numbers
expressing quantities, ratios, and numerical properties of
ingredients, reaction conditions, and so forth used in the
specification and claims are to be understood as being modified in
all instances by the term "about."
[0020] The present disclosure addresses and solves, inter alia,
problems attendant upon fabricating semiconductor devices with STI,
particularly the adverse impact of parasitic transistors formed at
the corners of the STI structures. Such trench corners are
relatively sharp causing high leakage, degrading Ion-Ioff
performance and increasing Vtlin mismatch. The present invention
addresses and solves such problems by providing means to increase
the threshold voltage of resulting parasitic transistors while
reducing mobility.
[0021] In accordance with embodiments of the present disclosure,
STI structures are formed with a high-K dielectric material
proximate trench corners. The formation of such a high-K dielectric
material proximate trench corners results in Fermi-level pinning as
well as degrading mobility from the high-K/semiconductor
interface.
[0022] Still other aspects, features, and technical effects will be
readily apparent to those skilled in this art from the following
detailed description, wherein preferred embodiments are shown and
described, simply by way of illustration of the best mode
contemplated. The disclosure is capable of other and different
embodiments, and its several details are capable of modifications
in various obvious respects. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
[0023] A method in accordance with an embodiment of the present
disclosure is schematically illustrated in FIGS. 1A through 1F.
Adverting to FIG. 1A, a trench 103 is formed in substrate 100 by
depositing a pad oxide layer 101, e.g., silicon dioxide, as at a
thickness of 20 angstroms (.ANG.) to 80 .ANG., e.g., 45 .ANG. to 55
.ANG., forming pad nitride layer 102, e.g., Si.sub.3N.sub.4, as at
a thickness of about 1000_.ANG. to 2000 .ANG., e.g., 1450 .ANG. to
1550 .ANG., on pad oxide layer 101. Substrate 100 may be any of
various substrates conventionally employed in the fabrication of
semiconductor devices, such as bulk silicon (as illustrated),
silicon-on insulator (SOI), and substrates based on strained
silicon or silicon-germanium. Etching is then conducted, such as
RIE, to form trench 103 having side surfaces 113 and a bottom
surface 123, as at a width of 500 .ANG. to 1000 .ANG., e.g., 790
.ANG. to 810 .ANG., and a depth of 1500 .ANG. to 4000 .ANG., e.g.,
2450 .ANG. to 2550 .ANG..
[0024] As illustrated in FIG. 1B, liner oxide 104 is then formed,
as by thermal oxidation, as at a thickness of 10 .ANG. to 40 .ANG.,
e.g., 19 .ANG. to 21 .ANG., lining the side surfaces 113 and bottom
surface 123 of trench 103. In accordance with embodiments of the
present disclosure, a layer of high-K dielectric material 105 is
then deposited over the pad nitride layer 102 and on the liner
oxide 104, as at a thickness of 20 .ANG. to 80 .ANG., e.g., 48
.ANG. to 52 .ANG.. As employed throughout the present disclosure, a
high-K dielectric material is intended to include dielectric
materials having a dielectric constant K equal to or greater than
4, relative to the dielectric constant K of 1 for a vacuum.
Suitable dielectric materials may include aluminum oxide
(Al.sub.2O.sub.3), zirconium silicate, hafnium silicate, hafnium
silicate oxynitride, hafnium silicon nitride, hafnium oxide
(HfO.sub.2), zirconium oxide (ZrO.sub.2), cerium oxide (CeO.sub.2),
titanium dioxide (TiO.sub.2), tantalum oxide (Ta.sub.2O.sub.5),
tungsten oxide (WO.sub.3), and yttrium (Y.sub.2O.sub.3).
[0025] Adverting to FIG. 1C, an insulating material 106, such as
silicon dioxide, is then deposited to fill the trench and form an
overburden on pad nitride layer 102. In accordance with embodiments
of the present invention, trench filling may be implemented by a
high aspect ratio process capable of filling gaps with an aspect
ratio of greater than 7:1 for 32 nm technology nodes and below,
e.g., 28 nm technology nodes and below. A suitable gap filling
technique is known as HARP.TM. and is available from Applied
Materials, Santa Clara, Calif. Subsequently planarization is
implemented in a conventional manner, as by CMP, such that the
upper surface of the insulating material filling the trench is
substantially coplanar with the upper surface of the pad nitride
layer 102, as illustrated in FIG. 1D. Pad nitride layer 102, pad
oxide layer 101, and the portions of high-K dielectric layer and
trench fill extending above the substrate are then removed, as by
etching, resulting in the structure illustrated in FIG. 1E, wherein
the trench is filled with insulating material 116.
[0026] Subsequent processing is conducted in accordance with
conventional practices and involves forming transistors on opposite
sides of the STI. Each transistor may typically comprise a gate
dielectric layer 108, gate electrode 109, source/drain regions 110,
and sidewall spacers 111. FIG. 1F illustrates the resulting
structure in the channel length direction, while FIG. 1G
illustrates the resulting structure in the channel width direction,
FIG. 1H illustrates a portion of area A with divot 126 unavoidably
formed in the trench fill after removing pad oxide and nitride
layers, noting a portion of gate electrode material 110 filling the
divot. The layer of high-K dielectric material 105 extends
proximate trench corners 107 resulting in Fermi-level pinning and
degradation of mobility from the high-K/substrate interface.
Consequently, any parasitic transistor formed at the trench corners
exhibits a higher threshold voltage and reduced mobility.
[0027] Another method in accordance with an embodiment of the
present disclosure is schematically illustrated in FIGS. 2A through
2G. As in the previous embodiment, a trench 203, having side
surfaces 213, bottom 223, as having a width of 500 .ANG. to 1000
.ANG., e.g., 790 .ANG. to 810 .ANG., and a depth of 1500 .ANG. to
4000 .ANG., e.g., 2450 .ANG. to 2550 .ANG., is formed in substrate
200 by initially forming a pad oxide layer 201 and a pad nitride
layer 202 on substrate 200, followed by etching, as by RIE. A liner
oxide 204 is then formed on side surfaces 213 and bottom surface
223 of trench 203, as shown in FIG. 2B. In accordance with this
embodiment, insulating material 205 is then deposited in trench 203
forming an overburden on pad nitride layer 202, e.g., by a high
aspect ratio process, as shown in FIG. 2C.
[0028] Subsequently, planarization is implemented, as by CMP, such
that the upper surface of the insulating material filling the
trench is substantially coplanar with the upper surface of pad
nitride layer 202, as illustrated in FIG. 2D.
[0029] In accordance with an embodiment of the present disclosure,
a portion of the insulating material filling trench 203 is removed
to form a recess 206 extending below the upper surface of the
substrate 200, as at a distance (X) of 20 .ANG. to 80 .ANG., e.g.,
48 .ANG. to 52 .ANG., leaving remaining insulating material 215 in
the trench, as illustrated in FIG. 2E. A layer of high-K dielectric
material 207 is then deposited filling the trench extending above
the recess and forming an overburden on the pad nitride layer 202,
as illustrated in FIG. 2F. High-K dielectric material layer 207 may
be deposited at a thickness of 50 .ANG. to 200 .ANG., e.g., 95
.ANG. to 105 .ANG..
[0030] Subsequently, planarization, as by CMP, is implemented to
remove the high-K dielectric material overburden from pad nitride
layer 202, followed by etching, as with a wet etch (HF-based 40
deg-80 deg) or a plasma etching Cl.sub.2/CO gas chemistry, to
remove the portion of high-K dielectric material above the recess,
such that the high-K dielectric material 217 filling the recess has
an upper surface substantially coplanar with the upper surface of
the substrate, as illustrated in FIG. 2G. In an alternative
embodiment, a portion of liner oxide 204 above insulating material
215 is removed before depositing the layer of high-K dielectric
material 207, resulting in direct contact between the high-K
dielectric layer 217 and substrate 200 in the upper portion of the
trench.
[0031] Subsequent processing comprises removing the pad oxide and
nitride layers 201 and 202, respectively, and forming transistors
spaced apart by the resulting STI. For example, each transistor may
comprise a gate dielectric layer 209, gate electrode 220,
source/drain regions 221, and sidewall spacers 222. The resulting
structure in the channel length direction is illustrated in FIG.
2H, and in the channel width direction in FIG. 2I. Advantageously,
the layer of high-K dielectric material 217 formed in the recess of
the insulating material in the trench extends proximate trench
corners 208, thereby effectively increasing the threshold voltage
of and reducing mobility of a parasitic transistor which may be
formed at the trench corners.
[0032] Another method in accordance with an embodiment of the
present disclosure is schematically illustrated in FIGS. 3A through
3D. This embodiment is similar to the previous embodiment
illustrated in FIGS. 2A through 2H up to the intermediate structure
illustrated in FIG. 2F, which is substantially the same as the
intermediate structure illustrated in FIG. 3A. In other words,
processing in this embodiment up to the intermediate structure
shown in FIG. 3A parallels the process flow of the previous
embodiment illustrated in FIGS. 2A through 2F. After forming the
intermediate structure shown in FIG. 3A, planarization, as by CMP,
is implemented to remove portions of the high-K dielectric material
layer 207 over the pad nitride layer 202, followed by an etch-back
process, as with plasma etch (anisotropic etch) in Cl2/CO gas
chemistry-to form high-K dielectric spacer 300 that extends
proximate trench corners 208, as illustrated in FIG. 3B. Spacer 300
may have a height (Y) of 20 .ANG. to 80 .ANG., e.g., 48 .ANG. to 52
.ANG., and a width (Z) of 20 .ANG. to 80 .ANG., e.g., 48 .ANG. to
52 .ANG.. This embodiment differs from the previous embodiment in
that a high-K dielectric spacer 300 is formed in a recess proximate
trench corners 208, instead of a high-K dielectric layer 217.
Subsequently, additional insulating material, for example
SiO.sub.2, is deposited to fill the sub-recess 301 that was etched
out when forming high-K dielectric spacer 300, resulting in the
structure illustrated in FIG. 3C including insulating material 302
filling the trench. In an alternative embodiment, a portion of
liner oxide 204 above insulating material 215 is removed before
depositing the layer of high-K dielectric layer 207, resulting in
direct contact between the high-K dielectric spacer 300 and
substrate 200 in the upper portion of the trench.
[0033] Subsequent processing comprises removing pad nitride 202 and
pad oxide 201 layers, and forming transistors on opposite sides of
the STI. For example, each transistor may comprise a gate
dielectric layer 209, gate electrode 220, source/drain regions 221,
and sidewall spacers 222. The resulting structure in illustrated in
the channel length direction in FIG. 3D and in the channel width
direction in FIG. 3E, noting a portion of gate electrode material
230 filling a divot in the insulating trench fill. As in previous
embodiments, high-K dielectric spacer 300 effectively increases the
threshold voltage and reduces mobility of any parasitic transistor
which may be formed at the trench corners.
[0034] The embodiments of the present disclosure achieve several
technical effects, particularly in fabricating semiconductor
devices with dimensions in the deep submicron range exhibiting
reduced leakage, thereby enhancing process flow while increasing
device performance, yield, and reliability. Embodiments of the
present disclosure enjoy utility in various industrial
applications, e.g., microprocessors, smart phones, mobile phones,
cellular handsets, set-top boxes, DVD recorders and players,
automotive navigation, printers and peripherals, networking and
telecom equipment, gaming systems, and digital cameras. The present
disclosure therefore enjoys industrial applicability in any of
various types of semiconductor devices.
[0035] In the preceding description, the present disclosure is
described with reference to specifically exemplary embodiments
thereof. It will, however, be evident that various modifications
and changes may be made thereto without departing from the broader
spirit and scope of the present disclosure, as set forth in the
claims. The specification and drawings are, accordingly, to be
regarded as illustrative and not as restrictive. It is understood
that the present disclosure is capable of using various other
combinations and embodiments and is capable of any changes or
modifications within the scope of the inventive concept as
expressed herein.
* * * * *