U.S. patent application number 13/552695 was filed with the patent office on 2012-11-08 for uniformly aligned well and isolation regions in a substrate and resulting structure.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, JR., Lilian Kamal, Jed H. Rankin, Robert R. Robison, William Tonti.
Application Number | 20120280356 13/552695 |
Document ID | / |
Family ID | 43779358 |
Filed Date | 2012-11-08 |
United States Patent
Application |
20120280356 |
Kind Code |
A1 |
Abadeer; Wagdi W. ; et
al. |
November 8, 2012 |
UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND
RESULTING STRUCTURE
Abstract
A solution for alleviating variable parasitic bipolar leakages
in scaled semiconductor technologies is described herein. Placement
variation is eliminated for edges of implants under shallow trench
isolation (STI) areas by creating a barrier to shield areas from
implantation more precisely than with only a standard
photolithographic mask. An annealing process expands the implanted
regions such their boundaries align within a predetermined distance
from the edge of a trench. The distances are proportionate for each
trench and each adjacent isolation region.
Inventors: |
Abadeer; Wagdi W.; (Jericho,
VT) ; Kamal; Lilian; (Saratoga, CA) ; Chatty;
Kiran V.; (Oviedo, FL) ; Gauthier, JR.; Robert
J.; (Hinesburg, VT) ; Rankin; Jed H.;
(Richmond, VT) ; Robison; Robert R.; (Colchester,
VT) ; Tonti; William; (Essex Junction, VT) |
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
43779358 |
Appl. No.: |
13/552695 |
Filed: |
July 19, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12570415 |
Sep 30, 2009 |
8232177 |
|
|
13552695 |
|
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Current U.S.
Class: |
257/509 ;
257/544; 257/E29.019; 257/E29.02 |
Current CPC
Class: |
H01L 21/76232
20130101 |
Class at
Publication: |
257/509 ;
257/544; 257/E29.019; 257/E29.02 |
International
Class: |
H01L 29/06 20060101
H01L029/06 |
Claims
1. A structure comprising: a substrate having a depression and at
least a first region; the depression having at least one first
edge; the first region having a boundary; and the first region
being coupled to at least a first portion of the depression such
that a portion of the boundary of the first region is at a
predetermined distance (W1) from the first edge.
2. The structure of claim 1, further comprising a second region,
the second region having a second boundary coupled to at least a
second portion of the depression such that the second boundary is
at a second predetermined distance (W2) from a second edge of the
depression.
3. The structure of claim 2, wherein the predetermined distance
from the first edge and the second predetermined distance, are
substantially similar.
4. The structure of claim 2, wherein the predetermined distance
from the first edge and the second predetermined distance, are
within 10 nm.
5. The structure of claim 2, wherein the first region and the
second region are doped with a first charge and a second charge
respectively.
6. A structure comprising: an isolation region having one or more
side edges, and a bottom edge; and a first diffusion region coupled
to at least a portion of the isolation region having a
predetermined distance (W1) from one of the side edges of the
isolation region.
7. The structure of claim 6, further comprising a second diffusion
region (810b) having substantially the same predetermined distance
(W2) from a second one of the side edges.
8. The structure of claim 7, wherein: the first diffusion region is
coupled to the second diffusion region at the bottom edge of the
isolation region; and the portion of the first diffusion region
along the bottom edge of the isolation region and the portion of
the second diffusion region along the bottom edge of the isolation
region are substantially similar.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional application of
co-pending U.S. application Ser. No. 12/570,415, filed on Sep. 30,
2009, the contents of which are incorporated by reference in their
entirety herein.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention generally relates to a semiconductor
structure, and more specifically to a semiconductor structure
having no edge placement variation of well implants relative to the
isolation structure.
[0004] 2. Background of the Invention
[0005] CMOS technologies continue scale smaller and smaller. As a
result parasitic bipolar leakages become harder to control. In
traditional process flows, well implants are defined using purely
lithographics definition done independently from lithographic steps
used for defining physical isolation structures. This independence
creates inherent variability.
BRIEF SUMMARY OF THE INVENTION
[0006] The following describes a structure and method for
alleviating parasitic bipolar leakages in scaled semiconductor
technologies. The structure has no edge (or boundary) placement
variation for edges of implants under shallow trench isolation
(STI) areas, in other words, the distance between the edges of the
STI and the corresponding edges or boundaries of implanted wells
beneath a given STI are substantially equal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a diagram showing the problem to be solved;
[0008] FIG. 2 is demonstrates the various types of parasitic
devices which are inadvertently formed;
[0009] FIG. 3 is an illustration of the problem and shows
advantages offered by the solution;
[0010] FIGS. 4A and 4B are each a view of simulation of electrical
properties using the prior art solution;
[0011] FIG. 5A is a view of an embodiment at a step in a process
where a second layer is deposited onto a first substrate. FIG. 5B
is a top view of an embodiment of the invention at that step in the
process, showing second layer after deposition;
[0012] FIG. 6A is a view of an embodiment at another step in the
process where a third layer is deposited over the second layer on
the substrate. FIG. 6B is a top view of this embodiment of the
invention and shows the third layer overlaying the second layer on
the substrate;
[0013] FIG. 7A illustrates a side view of a structure which has had
portions of the top substrate removed using a chemical etch process
or other process which provides similar results; FIG. 7B
illustrates the result from the top view;
[0014] FIG. 8A illustrates a side view of a structure having
implants (e.g. n-well, p-well) and an annealing process. The edges
or boundaries of the implants are located at a predetermined
distances from the planned STI placement; FIG. 8B shows a top view
of the structure;
[0015] FIG. 9A illustrates a step of depositing a fourth substrate
(e.g. nitride) over the second substrate and adjacent to the third
substrate and performing a polishing process. FIG. 9B illustrates
an example top view of the results of the depositing step;
[0016] FIG. 10A illustrates a side view of the structure after
removing the third substrate (e.g. Polysilicon). FIG. 10B
illustrates a top view of the structure.
[0017] FIG. 11A shows the structure after an etch process to remove
a portion of the first and second substrates (e.g. silicon and
oxide); FIG. 11B shows a top view of the structure;
[0018] FIG. 12A shows the structure having a fifth film deposited
in the shallow trench isolation (STI) areas. FIG. 12B shows a top
view of the structure at this step in the process;
[0019] FIG. 13A illustrates an example of the structure having a
similar distance between a first implant (or doped) region and an
STI and a second implant (or doped) region on the other side of the
STI; FIG. 13B shows a top view of the structure shown in FIG.
13A;
[0020] FIG. 14 illustrates a flow diagram of an example process
used to make the structure; and
[0021] FIG. 15A illustrates an example of the structure having a
similar distance and coupled between a first implant (or doped)
region and an STI and a second implant (or doped) region on the
other side of the STI; FIG. 15B shows a top view of the structure
shown in FIG. 15A.
DETAILED DESCRIPTION
[0022] FIG. 1 illustrates a problematic parasitic effect shown as
NPN device 130 in structure 100. NPN device 130 represents a
function that occurs when the boundaries between two (or more)
implanted (or doped) regions (e.g. Pwell 125, Nwell 120, and N+
region 115) are touching or very nearly touching. The parasitic
effect varies depending on the distance between the adjacent doped
regions. In this example, a parasitic effect is created beneath a
shallow trench isolation (STI) region 105 at the Nwell 120 and
Pwell 125 junction.
[0023] FIG. 2 represents the growing complexity of the problem as
more devices are manufactured within smaller areas on a wafer (e.g.
scaling semiconductor technologies to become smaller and smaller).
Structure 200 shows two parasitic devices (npn and pnp) created
between an N+ region 225, Pwell 205 and Nwell 210; and P+ region
230, Nwell 210 and Pwell 205 respectively.
[0024] FIG. 3 shows a prior art solution to the parasitics problem
as structure 300. Structure 300 is a hyper-abrupt junction varactor
having p+-n junctions 315, cathode contact 335, anode contact 330,
an N cathode implant region 320, Nwells 325a and 325b, n+ regions
310a and 310b, and STIs 305a-d. This figure demonstrates the size
of the structure required to avoid generation of the variable
parasitic devices.
[0025] In conventional processing, STI is defined prior to well
implants. In some cases, the implants penetrate the side walls of
one or more of STIs 305. FIG. 3A shows "n+ii", "P&Nii", and
"n+ii" ion implants, which extend into the STI walls 305 for each
device. The small geometries result in narrow anode widths as shown
in FIG. 3A. Degradation of an ideality factor is significant for
small geometry diodes such as P-n diodes bounded by STIs having
implant penetration. An ideality factor is a constant adjustment
factor used to correct for discrepancies between an ideal PN
junction equation and a measured device.
[0026] FIG. 4A shows a simulated degradation of the ideality factor
as a function of width. Simulated device 1 shown in FIG. 3 has a
width of 1 um resulting in an ideality factor of 1.16 or greater.
Device 2 has a width of 0.5 um and a corresponding ideality factor
of between 1.13 and 1.15. Likewise, device 3 has a width of 0.25 um
and an ideality factor of less than 1.13. The decreasing widths
directly correlate with decreasing ideality factors.
[0027] FIG. 4B shows a simulation plot for a percent capacitance
degradation after 25 hours of stress (reverse bias mode) at 4.5V
and 140.degree. C. As the varactor width (in um) increases the
percent capacitance change approaches 0% after 25 hours of stress.
The reliability degradation of the varactor capacitance is directly
proportional to the degradation of the ideality factor.
[0028] FIG. 5A shows a side view of a structure 500 having a
substrate 510 (for example a layer of silicon such as one used for
a wafer), and a film 505 is deposited over substrate 510 (for
example a layer of oxide); FIG. 5B shows a top view of structure
500, which shows film 505 deposited over substrate 510.
[0029] FIG. 6A shows a side view of a structure 600 having a third
film 610 (for example a Polysilicon layer) deposited over substrate
510; FIG. 6B shows the top view of structure 600 having the top
layer of film 610.
[0030] FIG. 7A shows a structure 700 after patterning. The process
may include, for example a photolithography step and a subsequent
etching step. The process generates structure 700 which shows a
patterned film 610; FIG. 7B illustrates an example of a top view of
structure 700 having the patterned film 610 and the exposed film
505 beneath.
[0031] FIG. 8A shows a side view of a structure 800 having been
through processing that includes, for example, a well implant step
(e.g. ion implant or doping step) and an annealing step. Wells 810a
and 810b are formed in substrate 510 through, for example, the use
of a photomask (not shown) followed by ion implantation, thermal
activation, and annealing, and may be, for example, n-wells (810a)
or p-wells (810b). Substrate 510, directly beneath film 610 (and
corresponding photomasks) is shielded from the implants. The
implanting step is followed by an annealing process. In this
example implant areas 810 expand during the annealing process such
that their edges (or boundaries) are located a predetermined
distance from the edges of film 610; FIG. 8B shows a top view of
structure 800, which shows films 610 and 505. Implants 810 are
beneath film 505 and their boundaries are shown as dotted lines
810a and 810b. The boundaries reside at predetermined distances
from the edges of film 610 shown by way of illustration as W1, W2,
W3, and W4.
[0032] FIG. 9A shows structure 900 after several processing steps,
for example, a nitride deposition step, and a planarization step
such as by chemical mechanical planarization (CMP). Structures 910
(e.g. a nitride) is deposited over film 505 then a step such as a
planarization step for example, is used to polish structures 910 to
be nearly even with the top of film 610; FIG. 9B shows a top view
of structure 900 having structures 910 and film 610 visible.
[0033] FIG. 10A shows structure 1000 after film 610 has been
removed. The patterned film 610 may be removed using a stripping
process, for example; FIG. 10B shows a top view of structure 1000
having structures 910 and film 505.
[0034] FIG. 11A shows a side view of structure 1100 where film 505
and substrate 510 have undergone a stripping and/or etching process
(for example a reactive ion etching (RIE) process known to those of
ordinary skill in the semiconductor manufacturing field) to
generate trenches 1110a and 1110b (or depressions, channels, etc.).
Optionally, additional processing may be implemented at this stage,
for example additional ion implant processes; FIG. 11B shows a top
view of structure 1100 with exposed substrate 510, implant areas
810, and structures 910.
[0035] FIG. 12A shows a side view of a structure 1200 having a
material 1210a and 1210b, such as an isolation material (e.g.
oxide) for example, deposited over structure 1200 to fill-in
trenches 1110a and 1110b respectively, thereby creating a shallow
trench isolation area. A subsequent polishing step (e.g. a CMP)
step is used after deposition. FIG. 12B shows a top view of
structure 1200 having structures 910 and the isolation materials
1210 in trenches 1110 visible from the top. One edge of trench
1110b is shown as edge or boundary 1220, a second boundary of
trench 1110b is shown as boundary 1230. A first and second boundary
of trench 1110a is shown as boundaries 1240 and 1250
respectively.
[0036] FIG. 13B shows a top view of structure 1300 which includes a
substrate 510 having the material 1210a and b (e.g. oxide to create
an STI) and at least a first region (e.g. a doped or ion implanted
region 810a); the trench 1110a having the first edge or first
boundary 1220 (e.g. the side wall or bottom of the trench 1110b or
material 1210b); the first region 810a having a boundary 1320 (e.g.
the edge or boundary of the doped region 810a where it connects to
an adjacent substance such as oxide material of 1210b); the first
region (e.g. the doped region 810a) being coupled to (e.g.
touching) at least a first portion of the trench 1110b (e.g. the
bottom and/or side of the trench 1110b or material 1210b) such that
a portion of the boundary 1320 of the first region 810a is at a
predetermined distance W1 from the first edge 1220 of trench 1110b
(e.g. with respect to the side of the trench and doped regions as
shown as W1 between elements 810a and 1210).
[0037] FIGS. 13A and 13B also show the structure 1300, having a
second region 810b (e.g. another doped region); the second region
810b having a second boundary 1330 (e.g. edge) coupled to at least
a second portion 1230 of the material 1210b (e.g. a sidewall and/or
bottom of trench 1110b) such that a second portion of the second
boundary 1330 (e.g. a portion of the boundary around second region
801b) is at a second predetermined distance (W2) from a second edge
boundary 1230 of trench 1110b. The predetermined distance, W1, and
the second predetermined distance W2, are substantially similar
(e.g. W1 is about equal to W2).
[0038] Likewise, FIGS. 13A and 13B show: the second trench 1110a
having a material 1210a, a boundary 1240 of trench 1110a, and a
doped region 810b having a boundary 1340 and adjacent to material
1210a. The distance between boundaries 1240 and 1340 is shown as
W3. Region 810a further has a second boundary 1350 adjacent to a
second boundary 1350 of material 1210a. The distance between
boundary 1250 and boundary 1350 is shown as W4. Where W3 and W4 are
substantially equal.
[0039] The predetermined distance from the first edge (W1) and the
second predetermined distance (W2), may be within, for example,
about 10 nm, 10 nm should not be construed as a limitation however.
Likewise, the predetermined distance (W3) is equivalent to within
10 nm of the distance (W4).
[0040] FIG. 14 shows a flow diagram of a method 1400 of making
structure 1300. Step 1410: deposit a material film 505 such as a
thin oxide for example, over a substrate 510 such as a silicon
wafer.
[0041] Step 1415: deposit a second film 610, such as Polysilicon,
adjacent to film 505;
[0042] Step 1420: perform photolithography using a reticle and
photoresist, which will shield substrate 510 from unwanted
implantation and guide self-alignment of the wells 810 to the STIs
1210;
[0043] Step 1425: perform an etch process to remove film 610 where
any implants 810 are desired;
[0044] Step 1430: implant in the exposed film 505 to generate
implant areas or wells 810;
[0045] Step 1435: anneal the subsequent structure to evenly expand
areas 810 under film 610;
[0046] Step 1440: deposit a structure 910 (e.g. nitride) over film
505;
[0047] Step 1445: perform a CMP process to even the thickness of
structure 910 with film 610;
[0048] Step 1450: remove film 610 (e.g. Polysilicon) using a
stripping process;
[0049] Step 1455: perform an RIE step on the exposed substrate 510
and film 505 (e.g. oxide and silicon);
[0050] Step 1460: optionally, perform additional implants into
exposed substrate 510;
[0051] Step 1465: deposit a film such as an oxide to generate
isolation regions (STIs) 1210;
[0052] Step 1470: perform a CMP process to remove overfill of
trenches;
[0053] Step 1475: remove structures 910 (e.g. nitride); and
[0054] Step 1480: perform the process of record (POR). For example,
forming FETs and wires to create a functional IC.
[0055] FIGS. 15A and 15B show a side and top view of structure
1500, respectively. Structure 1500 includes a substrate 510 having
the material 1210a and b (e.g. oxide to create an STI) and at least
a first region (e.g. a doped or ion implanted region 810a); the
trench 1110b having the first edge or first boundary 1220 (e.g. the
side wall or bottom of the trench 1110b or material 1210b); the
first region 810a having a boundary 1530 (e.g. the edge or boundary
of the doped region 810a where it connects to an adjacent substance
such as oxide material of 1210b); the first region (e.g. the doped
region 810a) being coupled to (e.g. touching) at least a first
portion of the trench 1110b (e.g. the bottom and/or side of the
trench 1110b or material 1210b) such that a portion of the boundary
1530 of the first region 810a is at a predetermined distance W8
from the first edge 1220 of trench 1110b (e.g. with respect to the
side of the trench and doped regions as shown as W8 between
elements 810a and 1210).
[0056] FIGS. 15A and 15B also show the structure 1500, having a
second region 810b (e.g. another doped region); the second region
810b having the same boundary 1530 (e.g. edge) as doped region 810a
and coupled to at least a second portion 1230 of the material 1210b
(e.g. a sidewall and/or bottom of trench 1110b) such that a second
portion of the boundary 1530 (e.g. a portion of the boundary around
second region 801b) is at a second predetermined distance (W7) from
a second edge boundary 1230 of trench 1110b. The predetermined
distance, W7, and the second predetermined distance W8, are
substantially similar and coupled (e.g. W7 is about equal to
W8).
[0057] Likewise, FIGS. 15A and 15B show the second trench 1110a
having a material 1210a, a boundary 1240 of trench 1110a, and a
doped region 810b having a boundary 1550 and adjacent to material
1210a. The distance between boundaries 1240 and 1550 is shown as
W6. Region 810a further has boundary 1550 adjacent and coupled to a
boundary 1250 of material 1210a. The distance between boundary 1250
and boundary 1550 is shown as W5. Where W5 and W6 are substantially
equal.
[0058] It should be apparent to one of ordinary skill in the art
that the foregoing description and drawings are meant to provide an
illustrative example of developing regions that are self-aligned
with edges such as edges of shallow trenches and changes to the
structure and process may be modified without departing from the
spirit and scope of the invention.
* * * * *