U.S. patent application number 13/430439 was filed with the patent office on 2012-10-25 for semiconductor package.
This patent application is currently assigned to MEDIATEK INC.. Invention is credited to Tai-Yu CHEN, Wen-Sung HSU, Tzu-Hung LIN.
Application Number | 20120267779 13/430439 |
Document ID | / |
Family ID | 47020662 |
Filed Date | 2012-10-25 |
United States Patent
Application |
20120267779 |
Kind Code |
A1 |
LIN; Tzu-Hung ; et
al. |
October 25, 2012 |
SEMICONDUCTOR PACKAGE
Abstract
The invention provides a semiconductor package. The
semiconductor package includes a semiconductor die having a central
area and a peripheral area surrounding the central area. A first
conductive bump is disposed on the semiconductor die in the central
area. A second conductive bump is disposed on the semiconductor die
in the peripheral area. An area ratio of the first conductive bump
to the second conductive bump from a top view is larger than 1, and
less than or equal to 3.
Inventors: |
LIN; Tzu-Hung; (Zhubei City,
TW) ; HSU; Wen-Sung; (Zhubei City, TW) ; CHEN;
Tai-Yu; (Taipei City, TW) |
Assignee: |
MEDIATEK INC.
Hsin-Chu
TW
|
Family ID: |
47020662 |
Appl. No.: |
13/430439 |
Filed: |
March 26, 2012 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
61478791 |
Apr 25, 2011 |
|
|
|
Current U.S.
Class: |
257/737 ;
257/E23.068 |
Current CPC
Class: |
H01L 24/17 20130101;
H01L 2224/131 20130101; H01L 2224/05572 20130101; H01L 2224/13016
20130101; H01L 2224/131 20130101; H01L 2224/02181 20130101; H01L
2224/02166 20130101; H01L 2224/14515 20130101; H01L 2224/13147
20130101; H01L 2924/00014 20130101; H01L 2924/18161 20130101; H01L
24/05 20130101; H01L 24/04 20130101; H01L 2224/0401 20130101; H01L
2224/11462 20130101; H01L 2224/1308 20130101; H01L 2224/02125
20130101; H01L 23/49838 20130101; H01L 24/14 20130101; H01L
2224/1403 20130101; H01L 2224/16238 20130101; H01L 2224/13083
20130101; H01L 2224/02165 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101; H01L 2224/13155 20130101; H01L 2224/0219
20130101; H01L 2224/73204 20130101; H01L 2924/01033 20130101; H01L
2224/13155 20130101; H01L 2224/73204 20130101; H01L 23/3192
20130101; H01L 24/11 20130101; H01L 2224/11462 20130101; H01L
2224/13006 20130101; H01L 2924/00014 20130101; H01L 2224/16225
20130101; H01L 2924/014 20130101; H01L 2224/05552 20130101; H01L
24/13 20130101; H01L 2224/32225 20130101; H01L 2924/07025 20130101;
H01L 2224/27013 20130101; H01L 2924/00012 20130101; H01L 2224/32225
20130101; H01L 2924/00014 20130101; H01L 24/16 20130101; H01L
2924/01029 20130101; H01L 2924/01075 20130101 |
Class at
Publication: |
257/737 ;
257/E23.068 |
International
Class: |
H01L 23/498 20060101
H01L023/498 |
Claims
1. A semiconductor package, comprising: a semiconductor die; and a
first conductive bump and a second conductive bump respectively
disposed on the semiconductor die, wherein an area ratio of the
first conductive bump to the second conductive bump from a top view
is larger than 1, and less than or equal to 3.
2. The semiconductor package as claimed in claim 1, wherein the
semiconductor die has a central area and a peripheral area
surrounding the central area, and wherein the first conductive bump
is disposed on the semiconductor die in the central area, and the
second conductive bump is disposed on the semiconductor die in the
peripheral area.
3. The semiconductor package as claimed in claim 1, wherein the
semiconductor die has a central area and a peripheral area
surrounding the central area, and wherein the first conductive bump
is disposed on the semiconductor die in the peripheral area, and
the second conductive bump is disposed on the semiconductor die in
the central area.
4. The semiconductor package as claimed in claim 1, wherein the
first conductive bump and the second conductive bump are
alternatively disposed on the semiconductor die.
5. The semiconductor package as claimed in claim 1, wherein the
first conductive bump and the second conductive bump are randomly
disposed on the semiconductor die.
6. The semiconductor package as claimed in claim 1, wherein the
first conductive bump is a circular shape from the top view.
7. The semiconductor package as claimed in claim 1, wherein the
second conductive bump is an oblong shape from the top view.
8. The semiconductor package as claimed in claim 1, wherein the
first conductive bump connects to a power pad or ground pad of the
semiconductor die.
9. The semiconductor package as claimed in claim 1, wherein the
second conductive bump connects to a signal pad of the
semiconductor die.
10. The semiconductor package as claimed in claim 1, further
comprising: a first under bump metallurgy layer pattern disposed
between the semiconductor die and the first conductive bump; and a
second under bump metallurgy layer pattern disposed between the
semiconductor die and the second conductive bump.
11. The semiconductor package as claimed in claim 10, wherein the
first under bump metallurgy layer pattern is a circular shape from
the top view.
12. The semiconductor package as claimed in claim 10, wherein the
second under bump metallurgy layer pattern is a rectangular shape
from the top view.
13. The semiconductor package as claimed in claim 10, further
comprising: a first conductive pillar connecting to and between the
first under bump metallurgy layer pattern and the first conductive
bump; and a second conductive pillar connecting to and between the
second under bump metallurgy layer pattern and the second
conductive bump.
14. The semiconductor package as claimed in claim 13, wherein the
first conductive pillar is a circular shape.
15. The semiconductor package as claimed in claim 13, wherein the
second conductive pillar is an oblong shape from the top view.
16. The semiconductor package as claimed in claim 13, wherein an
area ratio the first conductive pillar to the second conductive
pillar from a top view is larger than 1, and less than or equal to
3.
17. The semiconductor package as claimed in claim 1, further
comprising a substrate having a plurality of conductive traces
thereon, wherein the first conductive bump and the second
conductive bump are bonded onto the conductive traces,
respectively.
18. The semiconductor package as claimed in claim 1, further
comprising: a solder resistance layer disposed on the substrate,
away from an overlap region between the substrate and the
semiconductor die; and an underfill material filling a gap between
the substrate and the semiconductor
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 61/498,791 filed Apr. 25, 2011, the entirety of
which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor package,
and in particular, to a conductive bump design for a semiconductor
package.
[0004] 2. Description of the Related Art
[0005] For a semiconductor chip package design, an increased amount
of input/output (I/O) connections for multi-functional chips is
required. The impact of this will be pressure on printed circuit
board (PCB) fabricators to minimize linewidth and space or to
develop direct chip attach (DCA) semiconductors. However, the
increased amount of input/output connections of a multi-functional
chip package may induce thermal electrical problems, for example,
problems with heat dissipation, cross talk, signal propagation
delay, electromagnetic interference for RF circuits, etc. The
thermal electrical problems may affect the reliability and quality
of products.
[0006] Thus, a novel semiconductor package with better thermal and
electrical properties is desirable.
BRIEF SUMMARY OF INVENTION
[0007] A semiconductor package is provided. An exemplary embodiment
of a semiconductor package comprises a semiconductor die having a
central area and a peripheral area surrounding the central area. A
first conductive bump is disposed on the semiconductor die in the
central area. A second conductive bump is disposed on the
semiconductor die in the peripheral area, wherein an area ratio of
the first conductive bump to the second conductive bump from a top
view is larger than 1, and less than or equal to 3.
[0008] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
[0009] The invention can be more fully understood by reading the
subsequent detailed description and examples with references made
to the accompanying drawings, wherein:
[0010] FIG. 1a shows a cross section view of one exemplary
embodiment of a semiconductor package of the invention.
[0011] FIG. 1b shows a schematic view of a layout of conductive
bumps of one exemplary embodiment of a semiconductor package of the
invention.
[0012] FIG. 2a shows a cross section view of another exemplary
embodiment of a semiconductor package of the invention.
[0013] FIG. 2b shows a schematic view of a layout of conductive
bumps of another exemplary embodiment of a semiconductor package of
the invention.
[0014] FIG. 3a shows a cross section view of yet another exemplary
embodiment of a semiconductor package of the invention.
[0015] FIG. 3b shows a schematic view of a layout of conductive
bumps of yet another exemplary embodiment of a semiconductor
package of the invention.
[0016] FIG. 4a shows a cross section view of still yet another
exemplary embodiment of a semiconductor package of the
invention.
[0017] FIG. 4b shows a schematic view of a layout of conductive
bumps of still yet another exemplary embodiment of a semiconductor
package of the invention.
DETAILED DESCRIPTION OF INVENTION
[0018] The following description is a mode for carrying out the
invention. This description is made for the purpose of illustrating
the general principles of the invention and should not be taken in
a limiting sense. The scope of the invention is best determined by
reference to the appended claims. Wherever possible, the same
reference numbers are used in the drawings and the descriptions to
refer the same or like parts.
[0019] The present invention will be described with respect to
particular embodiments and with reference to certain drawings, but
the invention is not limited thereto and is only limited by the
claims. The drawings described are only schematic and are
non-limiting. In the drawings, the size of some of the elements may
be exaggerated and not drawn to scale for illustrative purposes.
The dimensions and the relative dimensions do not correspond to
actual dimensions to practice the invention.
[0020] FIG. 1a shows a cross section view of one exemplary
embodiment of a semiconductor package 500a of the invention. One
exemplary embodiment of a semiconductor package 500a is a flip chip
package using copper pillars connecting to a semiconductor die and
a substrate. As shown in FIG. 1a, one exemplary embodiment of a
semiconductor package 500a comprises a semiconductor die 310 having
a central area 302 and a peripheral area 304 surrounding the
central area 310. The metal pads 202 and 204 belong to the
uppermost metal layer of the interconnection structure (not shown)
of the semiconductor die 310. In this embodiment, the metal pads
204 arranged in the central area 302 are used to transmit ground or
power signals of the semiconductor die 310, and the metal pads 202
arranged in the peripheral area 304 are used to transmit signals of
the semiconductor die 310. Therefore, the metal pads 204 may serve
as ground or power pads, and the metal pads 202 may serve as signal
pads. In one embodiment, a minimum pitch of the metal pads 204 in
the central area 302 may be designed larger than a minimum pitch
designed for the metal pads 202 in the peripheral area 304, which
also serves as the minimum pitch for the metal pads of the design
rule of the semiconductor package 500a.
[0021] As shown in FIG. 1a, a first passivation layer 206 is
conformably formed covering the metal pads 202 and 204 by a
deposition and patterning processes. In one embodiment, the first
passivation layer 206 may comprise oxide, nitride, or oxynitride.
The first passivation layer 206 has openings on the metal pads 202
and 204, so that a portion of the metal pads 202 and 204 are
respectively exposed from the openings. Also, a second passivation
layer 208 is formed by a coating patterning and curing process. In
one embodiment, the second passivation layer 208 with openings
therethrough may comprise polyimide for providing reliable
insulation when the semiconductor die 310 is subjected to various
types of environmental stresses. A portion of the metal pads 202
and 204 are respectively exposed from the openings of the second
passivation layer 208. In this embodiment, the metal pads 204 are
arranged in the central area 302, and the metal pads 202 are
arranged in the peripheral area 304.
[0022] As shown in FIG. 1a, under bump metallurgy (UBM) layer
patterns 210a and 210b are formed on the passivation layer 208 by a
deposition method such as a sputtering or plating method and a
subsequent anisotropic etching process. The anisotropic etching
process is performed after forming conductive pillars. Meanwhile,
the UBM layer patterns 210a and 210b line sidewalls and bottom
surfaces of the openings of the passivation layer 208. In this
embodiment, the UBM layer patterns 210a are arranged in the central
area 302, and the UBM layer patterns 210b are arranged in the
peripheral area 304. Also, the UBM layer patterns 210a and 210b
extend over a top surface of the passivation layer 208. In one
embodiment, the UBM layer patterns 210a and 210b are composed of a
Ti layer and a Cu layer on the Ti layer. In one embodiment, the UBM
layer patterns 210a arranged in the central area 302 are designed
in a shape different from that of the UBM layer patterns 210b
arranged in the peripheral area 304 from the top view. For example,
the UBM layer patterns 210a arranged in the central area 302 are
designed in a circular shape and the UBM layer patterns 210b
arranged in the peripheral area 304 are designed in a rectangular
shape from the top view.
[0023] As shown in FIG. 1a, the conductive pillars 212a and 212b
are respectively formed on the UBM layer patterns 210a and 210b,
filling the openings of the passivation layer 208. In this
embodiment, the conductive pillars 212a are arranged in the central
area 302, and the conductive pillars 212b are arranged in the
peripheral area 304. Formation positions of the conductive pillars
212a and 212b are defined by a dry film photoresist or liquid
photoresist patterns (not shown). In one embodiment, the conductive
pillars 212a and 212b are used as a solder joint for subsequent
conductive bumps, which are used to transmit input/output (I/O),
ground or power signals of the semiconductor die 310, disposed
thereon. Therefore, the conductive pillars 212a and 212b may help
to increase the mechanical strength of the bump structure. In one
embodiment, the conductive pillars 212a and 212b may be formed of
copper, so that deformation may be prevented during a subsequent
solder re-flow process.
[0024] As shown in FIG. 1a, conductive buffer layers 214a and 214b
are formed on the conductive pillars 212a and 212b by an
electroplating method. In this embodiment, the conductive buffer
layers 214a are arranged in the central area 302, and the
conductive buffer layers 214b are arranged in the peripheral area
304. In one embodiment, the conductive buffer layer 240 is an
optional element serving as a seed layer, an adhesion layer and a
barrier layer for a subsequent conductive bump formed thereon. In
one embodiment, the conductive buffer layers 214a and 214b may
comprise Ni.
[0025] As shown in FIG. 1a, conductive bumps 216a and 216b are
respectively formed on the conductive buffer layers 214a and 214b
by electroplating a solder with a patterned photoresist layer or by
a screen printing process and a subsequent solder re-flow process.
In this embodiment, the conductive bumps 216a are arranged in the
central area 302, and the conductive bumps 216b are arranged in the
peripheral area 304. In one embodiment, the conductive bumps 216a
electrically connect to the metal pads 204, which are used to
transmit ground or power signals of the semiconductor die 310, and
the conductive bumps 216b electrically connect to the metal pads
202, which are used to transmit signals of the semiconductor die
310. In one embodiment of the invention, the conductive pillars
212a/212b, the overlying conductive bumps 216a/216b and the
conductive buffer layers 214a/214b (optional) therebetween,
collectively form bump structures. Additionally, the semiconductor
die 310 and the bump structures collectively form a semiconductor
package 500a.
[0026] FIG. 1b shows a schematic view of a layout 600a of
conductive bumps 216a and 216b of one exemplary embodiment of the
semiconductor package 500a of the invention. As shown in FIGS. 1a
and 1b, it is noted that an area A1 of each of the conductive bumps
216a arranged in the central area 302 is designed to be larger than
an area A2 of the conductive bumps 216b arranged in the peripheral
area 304 to increase thermal conductivity and reduce electrical
resistively, thereby improving thermal and electrical properties of
the semiconductor package 500. In one embodiment as shown in FIGS.
1 and 2, an area ratio A1/A2 of each of the conductive bumps 216a
to each of the conductive bumps 216b from a top view is larger than
1, and less than or equal to 3. In this embodiment, the area ratio
A1/A2 of each of the conductive bumps 216a to each of the
conductive bumps 216b from a top view is substantially equal to
1.5. In one embodiment, the conductive bumps 216a arranged in the
central area 302 are designed in a shape different from that of the
conductive bumps 216b arranged in the peripheral area 304 from the
top view. For example, the conductive bumps 216a are designed in a
circular shape and the conductive bumps 216b are designed in an
oblong shape from the top view. Further, the conductive pillars
212a arranged in the central area 302 are designed in a shape
substantially the same at that of the conductive bumps 216a. The
conductive pillars 212b arranged in the peripheral area 304 are
designed in a shape substantially the same at that of the
conductive bumps 216b from the top view. Accordingly, the
conductive pillars 212a are designed in a circular shape and the
conductive pillars 212b are designed in an oblong shape from the
top view. Moreover, an area of each of the conductive pillars 212a
arranged in the central area 302 is designed substantially the same
at that of the area A1 of each the conductive bumps 216a. An area
of each of the conductive pillars 212b arranged in the peripheral
area 304 is designed substantially the same at that of the area A2
of each of the conductive bumps 216b from the top view. Therefore,
in one embodiment as shown in FIGS. 1 and 2, an area ratio A1/A2 of
each of the conductive pillars 212a to each of the conductive
pillars 212b from a top view is larger than 1, and less than or
equal to 3. In this embodiment, the area ratio A1/A2 of each of the
conductive pillars 212a to each of the conductive pillars 212b from
a top view is substantially equal to 1.5.
[0027] Additionally, the semiconductor package 500a can be bonded
to a substrate 300, for example, a print circuit board (PCB), as
shown in FIG. 1a. In one embodiment, an underfill material 224 may
optionally fill a space between the semiconductor package 500a and
the substrate 300. In one embodiment, the substrate 300 has
conductive traces 230a and 230b disposed thereon. In this
embodiment, the conductive traces 230a are arranged in the central
area 302, and the conductive traces 230b are arranged in the
peripheral area 304. In one embodiment, the substrate 200 may be
formed of by semiconductor materials such as silicon, or organic
materials such as bismaleimide triacine, (BT), polyimide or
ajinomoto build-up film (ABF). In one embodiment, the conductive
traces 230a arranged in the central area 302 may be designed as
ground/power trace segments, and the second conductive traces 230b
arranged in the peripheral area 304 may be designed as signal trace
segments for routing. Also, the conductive traces 230a and 230b are
used for input/output (I/O) connections of a semiconductor die 310
mounted directly onto the substrate 200. Therefore, each of the
conductive traces 230a and 230b has a portion serving as a pad
region of the substrate 200. FIG. 1b also shows a relationship
between the conductive traces 230a/230b and the conductive bumps
216a/216b of one exemplary embodiment of the semiconductor package
500 of the invention. Terminal portions of the conductive traces
230a overlap with the conductive bumps 216a in the central area
302, and terminal portions of the conductive traces 230b overlap
with the conductive bumps 216b in the peripheral area 304.
[0028] In another embodiment, positions of the metal pads 202 and
204 can be exchanged. FIG. 2a shows a cross section view of another
exemplary embodiment of a semiconductor package 500b of the
invention. FIG. 2b shows a schematic view of a layout 600b of
conductive bumps of another exemplary embodiment of a semiconductor
package 500b of the invention. Elements of this embodiment which
are the same as those previously described in FIGS. 1a and 1b, are
not repeated for brevity. Differences between the semiconductor
packages 500a and 500b (the layouts 600a and 600b) are that the
metal pads 204 of the semiconductor package 500b for power/ground
connections are arranged in the peripheral area 304. Also, the
metal pads 202 of the semiconductor package 500b for power/ground
connections are arranged in the central area 302.
[0029] In yet another embodiment, the metal pads 202 and 204 can be
arranged both in the the central area 302 and the peripheral area
304. Also, the metal pads 202 and 204 can be alternatively arranged
in the central area 302 or the peripheral area 304. FIG. 3a shows a
cross section view of yet another exemplary embodiment of a
semiconductor package 500c of the invention. FIG. 3b shows a
schematic view of a layout 600c of conductive bumps of yet another
exemplary embodiment of a semiconductor package 500c of the
invention. Elements of this embodiment which are the same as those
previously described in FIGS. 1a and 1b, are not repeated for
brevity. As shown in FIGS. 3a and 3b, the metal pads adjacent to
any one of the metal pads 202 are the metal pads 204. Also, the
metal pads adjacent to any one of the metal pads 204 are the metal
pads 202.
[0030] In still yet another embodiment, the metal pads 202 and 204
can be arranged both in the central area 302 and the peripheral
area 304. Also, the metal pads 202 and 204 can be randomly arranged
in the central area 302 or the peripheral area 304. FIG. 4a shows a
cross section view of still yet another exemplary embodiment of a
semiconductor package 500d of the invention. FIG. 4b shows a
schematic view of a layout 600d of conductive bumps of still yet
another exemplary embodiment of a semiconductor package 500d of the
invention. Elements of this embodiment which are the same as those
previously described in FIGS. 1a and 1b, are not repeated for
brevity. As shown in FIGS. 4a and 4b, any one of the metal pads 202
can be adjacent to the metal pads 202 or 204. Also, any one of the
metal pads 204 can be adjacent to the metal pads 202 or 204.
[0031] Exemplary embodiments provide a semiconductor package. The
semiconductor package is designed to arrange conductive bumps with
two different areas (sizes) in one semiconductor package. Because
the power/ground connections of the semiconductor chip 301 has a
number much less than the signal connections, a minimum pitch of
the metal pads 204 for power/ground connections may be designed
larger than a minimum pitch designed for the metal pads 202 for
signal connections. An area A1 of each of the conductive bumps 216a
connecting the metal pads 204 is designed to be larger than an area
A2 of the conductive bumps 216b connecting the metal pads 202 to
increase thermal conductivity and reduce electrical resistively,
thereby improving thermal and electrical properties of the
semiconductor package 500. In one embodiment as shown in FIGS. 1a
and 1b, an area ratio A1/A2 of each of the conductive bumps 216a to
each of the conductive bumps 216b from a top view is larger than 1,
and less than or equal to 3. In this embodiment, the area ratio
A1/A2 of each of the conductive bumps 216a to each of the
conductive bumps 216b from a top view is substantially equal to
1.5. In one embodiment, the conductive bumps 216a arranged in the
central area 302 are designed in a shape different from that of the
conductive bumps 216b arranged in the peripheral area 304 from the
top view.
[0032] While the invention has been described by way of example and
in terms of the preferred embodiments, it is to be understood that
the invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *