U.S. patent application number 13/325047 was filed with the patent office on 2012-06-21 for method of forming a field effect transistor and schottky diode.
This patent application is currently assigned to Fairchild Semiconductor Corporation. Invention is credited to Daniel Calafut, Robert Herrick, Christopher Boguslaw Kocon, Becky Losee, Dean Probst, Christopher Lawrence Rexer, Steven Sapp, Paul Thorup, Hamza Yilmaz.
Application Number | 20120156845 13/325047 |
Document ID | / |
Family ID | 37074054 |
Filed Date | 2012-06-21 |
United States Patent
Application |
20120156845 |
Kind Code |
A1 |
Kocon; Christopher Boguslaw ;
et al. |
June 21, 2012 |
METHOD OF FORMING A FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE
Abstract
A method for forming a field effect transistor and Schottky
diode includes forming a well region in a first portion of a
silicon region where the field effect transistor is to be formed
but not in a second portion of the silicon region where the
Schottky diode is to be formed. Gate trenches are formed extending
into the silicon region. A recessed gate is formed in each gate
trench. A dielectric cap is formed over each recessed gate. Exposed
surfaces of the well region are recessed to form a recess between
every two adjacent trenches. Without masking any portion of the
active area, a zero-degree blanket implant is performed to form a
heavy body region of the second conductivity type in the well
region between every two adjacent trenches.
Inventors: |
Kocon; Christopher Boguslaw;
(Mountaintop, PA) ; Sapp; Steven; (Felton, CA)
; Thorup; Paul; (West Jordan, UT) ; Probst;
Dean; (West Jordan, UT) ; Herrick; Robert;
(Lehi, UT) ; Losee; Becky; (Orem, UT) ;
Yilmaz; Hamza; (Saratoga, CA) ; Rexer; Christopher
Lawrence; (Mountaintop, PA) ; Calafut; Daniel;
(San Jose, CA) |
Assignee: |
Fairchild Semiconductor
Corporation
South Portland
ME
|
Family ID: |
37074054 |
Appl. No.: |
13/325047 |
Filed: |
December 13, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12346626 |
Dec 30, 2008 |
8084327 |
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13325047 |
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11398467 |
Apr 4, 2006 |
7504306 |
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12346626 |
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60669063 |
Apr 6, 2005 |
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Current U.S.
Class: |
438/270 ;
257/E21.41 |
Current CPC
Class: |
H01L 21/26586 20130101;
H01L 29/42368 20130101; H01L 29/7811 20130101; H01L 29/66727
20130101; H01L 2924/13091 20130101; H01L 29/7813 20130101; H01L
29/41766 20130101; H01L 29/0619 20130101; H01L 29/0869 20130101;
H01L 29/66666 20130101; H01L 29/0847 20130101; H01L 29/66734
20130101; H01L 27/0629 20130101; H01L 29/66719 20130101; H01L
29/7806 20130101; H01L 29/407 20130101; H01L 29/1095 20130101; H01L
29/872 20130101; H01L 29/7827 20130101; H01L 29/7828 20130101 |
Class at
Publication: |
438/270 ;
257/E21.41 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1.-86. (canceled)
87. A method of forming a field effect transistor and Schottky
diode integrated in a die comprising an active area and a
termination region surrounding the active area, the method
comprising: forming a well region in a first portion of a silicon
region where the field effect transistor is to be formed but not in
a second portion of the silicon region where the Schottky diode is
to be formed, the silicon region and well region being of opposite
conductivity type; forming gate trenches extending into the silicon
region; forming a recessed gate in each gate trench; forming a
dielectric cap over each gate; recessing all exposed surfaces of
the well region to form a recess in the well region between every
two adjacent trenches such that the recess has sloped walls and a
bottom located between a top surface of the dielectric cap and a
top surface of the recessed gate; and without masking any portion
of the active area, performing a zero-degree blanket implant to
form a heavy body region of the second conductivity type in the
well region between every two adjacent trenches whereby the heavy
body region is self-aligned to the gate trenches.
88. The method of claim 87 further comprising performing a two-pass
angled implant into the sloped walls of each recess to thereby form
source regions of the first conductivity type adjacent the
dielectric cap, the sloped walls of the recess forming an outer
wall of each source region, the source regions being self-aligned
to the trenches.
89. The method of claim 88 further comprising forming a source
conductor contacting the outer wall of each source region and
contacting the heavy body region along the bottom of the recess,
the source conductor also contacting a top surface of the second
portion of the silicon region to thereby form a Schottky contact
therebetween.
90. The method of claim 87 further comprising: forming a wide
trench in the termination region; and filling the wide trench with
LOCOS.
91. The method of claim 87 further comprising forming a surface
gate in the termination region simultaneously with forming the
recessed gate in the gate trenches.
92. The method of claim 91 further comprising: forming an opening
over the surface gate; and forming a gate conductor contacting the
surface gate through the opening.
93. The method of claim 87 further comprising: forming a
termination trench in the termination region simultaneously with
forming the gate trenches; forming a recessed gate in the
termination trench simultaneously with forming the recessed gate in
the gate trenches; forming an opening over the recessed gate in the
termination trench; and forming a gate conductor contacting the
recessed gate in the termination trench through the opening.
94. The method of claim 91 further comprising: forming an opening
over the surface gate; and simultaneously with recessing all
exposed surfaces of the well region, recessing the surface gate
through the opening to thereby expose sidewalls of the surface gate
through the opening; and filling the opening with a gate conductor,
the gate conductor contacting the surface gate along the exposed
sidewalls of the surface gate.
95. The method of claim 87 further comprising: simultaneously with
forming the gate trenches, forming a wide trench in the termination
region; and filling a bottom portion of the wide trench and each
gate trench with LOCOS.
96. The method of claim 95 further comprising forming a termination
gate simultaneously with forming the recessed gate in the gate
trenches, the termination gate extending in part inside the wide
trench and in part over a mesa region adjacent the wide trench.
97. The method of claim 96 further comprising: forming a contact
opening over the termination gate in the wide trench; and
simultaneously with recessing all exposed surfaces of the well
region, recessing the termination gate through the opening to
thereby expose sidewalls of the termination gate through the
opening; and filling the opening with a gate conductor, the gate
conductor contacting the exposed sidewalls of the termination
gate.
98. The method of claim 87 wherein the second portion of the
silicon region is blocked during the recessing step so that no
recess is formed in the second portion of the silicon region.
99. The method of claim 87 further comprising: prior to forming the
recessed gate, forming a thick bottom dielectric along a bottom
portion of each gate trench; and prior to forming the recessed
gate, forming a gate dielectric lining the sidewalls of each gate
trench, wherein the thick bottom dielectric is thicker than the
gate dielectric.
100. The method of claim 87 further comprising: prior to forming
the recessed gate, forming a shield electrode along a bottom
portion of each gate trench; and prior to forming the recessed
gate, forming a dielectric layer over each shield electrode.
101.-108. (canceled)
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 12/346,626, filed Dec. 30, 2008, which is a continuation U.S.
application Ser. No. 11/398,467, filed Apr. 4, 2006, which claims
the benefit of U.S. Provisional Application No. 60/669,063, filed
Apr. 6, 2005, all of which are incorporated herein by reference in
their entirety for all purposes.
[0002] The following patent applications are also incorporated
herein by reference in their entirety for all purposes: U.S.
Provisional Application No. 60/588,845, filed Jul. 15, 2004, U.S.
application Ser. No. 11/026,276, filed Dec. 29, 2004, and U.S.
application Ser. No. 09/844,347, filed Apr. 27, 2001 (Publication
No. US 2002/0008284).
BACKGROUND OF THE INVENTION
[0003] The present invention relates in general to power
semiconductor technology, and more particularly to
accumulation-mode and enhancement-mode trenched-gate field effect
transistors (FETs) and their methods of manufacture.
[0004] The key component in power electronic applications is the
solid state switch. From ignition control in automotive
applications to battery-operated consumer electronic devices, to
power converters in industrial applications, there is a need for a
power switch that optimally meets the demands of the particular
application. Solid state switches including, for example, the power
metal-oxide-semiconductor field effect transistor (power MOSFET),
the insulated-gate bipolar transistor (IGBT) and various types of
thyristors have continued to evolve to meet this demand. In the
case of the power MOSFET, for example, double-diffused structures
(DMOS) with lateral channel (e.g., U.S. Pat. No. 4,682,405 to
Blanchard et al.), trenched gate structures (e.g., U.S. Pat. No.
6,429,481 to Mo et al.), and various techniques for charge
balancing in the transistor drift region (e.g., U.S. Pat. Nos.
4,941,026 to Temple, 5,216,275 to Chen, and 6,081,009 to Neilson)
have been developed, among many other technologies, to address the
differing and often competing performance requirements.
[0005] Some of the defining performance characteristics for the
power switch are its on-resistance, breakdown voltage and switching
speed. Depending on the requirements of a particular application, a
different emphasis is placed on each of these performance criteria.
For example, for power applications greater than about 300-400
volts, the IGBT exhibits an inherently lower on-resistance as
compared to the power MOSFET, but its switching speed is lower due
to its slower turn off characteristics. Therefore, for applications
greater than 400 volts with low switching frequencies requiring low
on-resistance, the IGBT is the preferred switch while the power
MOSFET is often the device of choice for relatively higher
frequency applications. If the frequency requirements of a given
application dictate the type of switch that is used, the voltage
requirements determine the structural makeup of the particular
switch. For example, in the case of the power MOSFET, because of
the proportional relationship between the drain-to-source
on-resistance RDSon and the breakdown voltage, improving the
voltage performance of the transistor while maintaining a low RDSon
poses a challenge. Various charge balancing structures in the
transistor drift region have been developed to address this
challenge with differing degrees of success.
[0006] Two varieties of field effect transistors are accumulation
mode FET and enhancement mode FET. In conventional accumulation
FETs because no inversion channel is formed, the channel resistance
is eliminated thus improving the transistor power handling
capability and its efficiency. Further, with no pn body diode, the
losses in synchronous rectification circuits attributable to the pn
diode are reduced. A drawback of conventional accumulation
transistors is that the drift region needs to be lightly doped to
support a high enough reverse bias voltage. However, a lightly
doped drift region results in a higher on-resistance and lower
efficiency. Similarly, in enhancement mode FETs, improving the
transistor break down voltage often comes at the price of higher
on-resistance or vice versa.
[0007] Device performance parameters are also impacted by the
fabrication process. Attempts have been made to address some of
these challenges by developing a variety of improved processing
techniques. Whether it is in ultra-portable consumer electronic
devices or routers and hubs in communication systems, the varieties
of applications for the power switch continue to grow with the
expansion of the electronic industry. The power switch therefore
remains a semiconductor device with high development potential.
BRIEF SUMMARY OF THE INVENTION
[0008] In accordance with an embodiment of the invention, a method
for forming a field effect transistor and Schottky diode integrated
in a die having an active area and a termination region surrounding
the active area includes forming a well region in a first portion
of a silicon region where the field effect transistor is to be
formed but not in a second portion of the silicon region where the
Schottky diode is to be formed. The silicon region and the well
region are of opposite conductivity type. Gate trenches are formed
extending into the silicon region. A recessed gate is formed in
each gate trench. A dielectric cap is formed over each recessed
gate. Exposed surfaces of the well region are recessed to form a
recess in the well region between every two adjacent trenches such
that the recess has sloped walls and a bottom located between a top
surface of the dielectric cap and a top surface of the recessed
gate. Without masking any portion of the active area, a zero-degree
blanket implant is performed to form a heavy body region of the
second conductivity type in the well region between every two
adjacent trenches. The heavy body region is self-aligned to the
gate trenches.
[0009] In one embodiment, a two-pass angled implant is performed
into the sloped walls of each recess to thereby form source regions
of the first conductivity type adjacent the dielectric cap. The
sloped walls of the recess form an outer wall of each source
region, and the source regions are self-aligned to the trenches. A
source conductor may be formed contacting the outer wall of each
source region and contacting the heavy body region along the bottom
of the recess. The source conductor may also contacts a top surface
of the second portion of the silicon region to thereby form a
Schottky contact therebetween
[0010] In another embodiment, a wide trench is formed in the
termination region and filled with LOCOS.
[0011] In another embodiment, a surface gate is formed in the
termination region simultaneously with forming the recessed gate in
the gate trenches. An opening may be formed over the surface gate,
and a gate conductor may be formed contacting the surface gate
through the opening. An opening may also be formed over the surface
gate and, simultaneously with recessing all exposed surfaces of the
well region, the surface gate may be recessed through the opening
to thereby expose sidewalls of the surface gate through the
opening. The opening may be filled with a gate conductor that
contacts the surface gate along the exposed sidewalls of the
surface gate.
[0012] In another embodiment, a termination trench is formed in the
termination region simultaneously with forming the gate trenches, a
recessed gate is formed in the termination trench simultaneously
with forming the recessed gate in the gate trenches, an opening is
formed over the recessed gate in the termination trench, and a gate
conductor is formed contacting the recessed gate in the termination
trench through the opening
[0013] In another embodiment, simultaneously with forming the gate
trenches, a wide trench is formed in the termination region, and a
bottom portion of the wide trench and each gate trench is filled
with LOCOS. A termination gate may be formed simultaneously with
forming the recessed gate in the gate trenches, where the
termination gate extends in part inside the wide trench and in part
over a mesa region adjacent the wide trench. A contact opening may
also be formed over the termination gate in the wide trench, and
simultaneously with recessing all exposed surfaces of the well
region, the termination gate may be recessed through the opening to
thereby expose sidewalls of the termination gate through the
opening. The opening may be filled with a gate conductor, and the
gate conductor may contact the exposed sidewalls of the termination
gate.
[0014] In another embodiment, the second portion of the silicon
region is blocked during the recessing step so that no recess is
formed in the second portion of the silicon region.
[0015] In another embodiment, prior to forming the recessed gate, a
thick bottom dielectric is formed along a bottom portion of each
gate trench, and prior to forming the recessed gate, a gate
dielectric is formed lining the sidewalls of each gate trench. The
thick bottom dielectric may be thicker than the gate
dielectric.
[0016] In yet another embodiment, prior to forming the recessed
gate, a shield electrode is formed along a bottom portion of each
gate trench, and prior to forming the recessed gate, a dielectric
layer is formed over each shield electrode.
[0017] These and other aspects of the invention are described below
in greater detail in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a simplified cross section view of a trenched-gate
accumulation FET with integrated Schottky in accordance with an
exemplary embodiment of the invention;
[0019] FIGS. 2A-2I are simplified cross section views depicting
various process steps for forming the integrated FET-Schottky diode
structure in FIG. 1 according to an exemplary embodiment of the
invention;
[0020] FIGS. 3A-3E are simplified cross section views depicting
alternate process steps to those in the latter portion of the
process sequence depicted by FIGS. 2G-2I, according to another
exemplary embodiment of the invention;
[0021] FIG. 3EE is a simplified cross section view of the an
alternate embodiment wherein the dielectric spacers in the process
sequence in FIGS. 3A-3E are removed prior to forming the top-side
conductor layer;
[0022] FIG. 4 is a simplified cross section view of a variation of
the structure in FIG. 3EE wherein shield electrodes are formed
underneath the gates;
[0023] FIG. 5 is a simplified cross section view of a variation of
the structure in FIG. 3E wherein the contact openings are extended
to about the same depth as the gate trenches;
[0024] FIG. 6 is a simplified cross section view of an enhancement
mode variation of the accumulation FET-Schottky diode structure in
FIG. 5;
[0025] FIG. 7A depicts simulation results wherein the electric
filed lines are shown for two SiC based accumulation FETs one with
a deeper Schottky contact recess than the other.
[0026] FIG. 7B is a simulated plot of the drain current versus
drain voltage for the two cases of deeper and shallower Schottky
contact recesses.
[0027] FIG. 8 is a simplified cross section view of a trenched-gate
accumulation FET with polysilicon source spacers, according to an
exemplary embodiment of the invention;
[0028] FIGS. 9A-9H, 9I-1, and 9J-1 are simplified cross section
depicting various process steps for forming the FET-Schottky diode
structure in FIG. 8 in accordance with an exemplary embodiment of
the invention;
[0029] FIGS. 9I-2 and 9J-2 are simplified cross section views
depicting alternate processing steps to the steps corresponding to
FIGS. 9I-1 and 9J-1, resulting in a variation of the FET-Schottky
diode structure in FIG. 8;
[0030] FIGS. 10 and 11 are simplified cross section views
respectively illustrating variations of the FET-Schottky structures
in FIGS. 9J-1 and 9J-2 wherein shield electrodes are formed
underneath the gates;
[0031] FIG. 12 is a simplified cross section view of a
trenched-gate accumulation FET-Schottky structure with shield
electrodes underneath the gates in accordance with another
embodiment of the invention;
[0032] FIG. 13 is a simplified cross section view illustrating a
variation of the FIG. 11 embodiment wherein the Schottky region
between adjacent trenches is modified to form a MPS structure;
[0033] FIG. 14 shows simulated plots of the drain current versus
drain voltage characteristics (left plot) and the gate voltage
versus the gate charge (right plot) for the FET-Schottky structure
in FIG. 1;
[0034] FIGS. 15A-15H are simplified cross section views depicting
various process steps for forming a trenched-gate FET with
self-aligned features in accordance with another embodiment of the
invention;
[0035] FIG. 16 shows an isometric view of a p-channel trenched-gate
FET with a non-planar top surface (prior to top metal formation) in
accordance with another embodiment of the invention;
[0036] FIGS. 17A, 17B-1, and 17B-2 are cross section views for two
abbreviated process sequences for forming the FET in FIG. 16;
[0037] FIG. 18 is cross section view illustrating a technique for
forming self-aligned source and heavy body regions, in accordance
with an embodiment of the invention;
[0038] FIGS. 18A-18I are cross section views at different
processing steps for forming the trenched-gate FET shown in FIG.
18, in accordance with an exemplary embodiment of the
invention;
[0039] FIGS. 19A-19H are cross section views at various process
steps of a process sequence in which no surface polysilicon is
formed and the number of masks is reduced compared to that in the
process of FIGS. 18A-18I, in accordance with another exemplary
embodiment of the invention;
[0040] FIGS. 20A-20G are cross section views depicting another
process sequence in which the number of masks is reduced compared
to that in FIGS. 18A-18I in accordance with yet another exemplary
embodiment of the invention;
[0041] FIGS. 21A-21H are cross section views depicting a process
sequence for forming a similar trenched-gate FET to that resulting
from FIGS. 18A-18I except that a Schottky diode is integrated with
the FET, in accordance with an exemplary embodiment of the
invention;
[0042] FIGS. 22A-22F are cross section views depicting yet another
process sequence for forming a trenched-gate FET with reduced
number of masks, in accordance with another embodiment of the
invention;
[0043] FIGS. 23A-23I are cross section views at different
processing steps for forming a trenched-gate FET with self-aligned
features, in accordance with yet another embodiment of the
invention; and
[0044] FIGS. 24A-24I show cross section views at different
processing steps for forming a trenched-gate FET with self-aligned
features in accordance with yet another embodiment of the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0045] The power switch can be implemented by any one of power
MOSFET, IGBT, various types of thyristors and the like. Many of the
novel techniques presented herein are described in the context of
the power MOSFET for illustrative purposes. It is to be understood
however that the various embodiments of the invention described
herein are not limited to the power MOSFET and can apply to many of
the other types of power switch technologies, including, for
example, IGBTs and other types of bipolar switches. Further, for
the purposes of illustration, the various embodiments of the
invention are shown to include specific p and n type regions. It is
understood by those skilled in the art that the teachings herein
are equally applicable to devices in which the conductivities of
the various regions are reversed.
[0046] FIG. 1 shows a simplified cross section view of a
trenched-gate accumulation field effect transistor (FET) optimally
integrated with a Schottky diode in a single cell, in accordance
with an exemplary embodiment of the invention. A lightly doped
n-type epitaxial layer 104 extends over and is in contact with a
highly doped n-type substrate 102. Gate trenches 106 extend into
and terminate within epitaxial layer 104. Each gate trench 106 is
lined with a dielectric layer 108 along its sidewalls and bottom,
and includes a recessed gate 110 and insulating material 112 atop
recessed gate 110. Triangular-shaped source regions 114 of n-type
conductivity flank each side of trenches 106. Source regions 114
overlap polysilicon gate 110 along the vertical dimension. This
overlap is not necessary in such applications as high-voltage FETs
wherein the absence of the overlap would have minimal impact on the
transistor on-resistance Rdson. The absence of the gate-source
overlap has more of an impact on Rdson in low voltage transistors,
and as such its presence would be advantageous in such
transistors.
[0047] Recessed portions of epitaxial layer 104 together with
source regions 114 form V-shaped contact openings 118 with rounded
bottoms. A Schottky barrier metal 120 extends over the structure
and fills contact openings 118 to make contact with source regions
114 along the sloped sidewalls of source regions 114, and to
contact epitaxial layer 104 in the recessed portions thereof. Since
source regions 114 are highly doped and epitaxial layer 104 is
lightly doped, top-side conductor layer 120 forms an ohmic contact
with source regions 114 and a Schottky contact with epitaxial layer
104. In one embodiment, Schottky barrier metal 120 comprises
titanium. A back-side conductor layer 122, e.g., comprising
aluminum (or titanium), contacts substrate 102.
[0048] Unlike enhancement-mode transistors, the accumulation-mode
transistor in structure 100 in FIG. 1 does not include a blocking
(p-type in this example) well or body region inside which the
conduction channel is formed. Instead a conducting channel is
formed when an accumulation layer is formed in epitaxial layer 104
along the trench sidewalls. The transistor in structure 100 is
normally on or off depending on the doping concentration of the
channel region and the doping type of gates 110. It is turned off
when the channel regions are entirely depleted and lightly
inverted. Also, because no inversion channel is formed, the channel
resistance is eliminated thus improving the transistor power
handling capability and its efficiency. Further, with no pn body
diode, the losses in synchronous rectification circuits
attributable to the pn diode are eliminated.
[0049] In the FIG. 1 embodiment, the FET in structure 100 is a
vertical trenched-gate accumulation MOSFET with the top-side
conductor layer 120 forming the source conductor and the
bottom-side conductor layer 120 forming the drain conductor. In
another embodiment, substrate 102 is p-type thereby forming an
accumulation IGBT.
[0050] FIGS. 2A-2I are simplified cross section views illustrating
various process steps for forming the integrated FET-Schottky diode
structure 100 in FIG. 1, in accordance with an exemplary embodiment
of the invention. In FIG. 2A, lower epitaxial layer 204 and upper
epitaxial layer 205 are sequentially formed over n-type substrate
202 using conventional methods. Alternatively, a starting wafer
material which includes epitaxial layers 204, 205 may be used. The
upper n-type epitaxial layer 205 has a higher doping concentration
than the lower n-type epitaxial layer 204. In FIG. 2B, a mask (not
shown) is used to define and etch the silicon to form trenches 206
extending through upper epitaxial layer 205 and terminating within
lower epitaxial layer 204 using known techniques. A conventional
dry or wet etch may be used in forming the trenches. In FIG. 2C, a
dielectric layer 208, e.g., comprising oxide, is grown or deposited
over the structure whereby the sidewalls and bottom of trenches 206
are lined with dielectric layer 208.
[0051] In FIG. 2D, a layer of polysilicon 209 is then deposited to
fill trenches 206 using conventional techniques. Polysilicon layer
209 may be in-situ doped to obtain the desired gate doping type and
concentration. In FIG. 2E, polysilicon layer 209 is etched back and
recessed within trenches 206 to form gates 210, using conventional
techniques. Recessed gates 210 overlap upper epitaxial layer 205
along the vertical dimension. As mentioned above, depending on the
target application and the design goals, recessed gates 210 need
not overlap upper epitaxial layer 205 (i.e., the process sequence
and the final structure need not be limited by this overlap). In
other embodiments, gate 210 comprises polysilicon carbide or
metal.
[0052] In FIG. 2F, a dielectric layer 211, e.g., from oxide, is
formed over the structure and then planarized using conventional
techniques. In FIG. 2G, a blanket etch of the planarized dielectric
layer 211 (in the active region) is carried out at least in the
active area of the device to expose surface areas of upper
epitaxial layer 205 while portions 212 of dielectric layer 211
remain over recessed gates 210. In FIG. 2H, a blanket angled
silicon etch (e.g., dry etch in the active region) is carried out
at least in the active area to form the V-shaped contact openings
218 with rounded bottoms using conventional techniques. Contact
openings 218 extend clear through upper epitaxial layer 205 thus
forming two source regions 214 between every two adjacent trenches.
Contact openings 218 extend into and terminate within an upper half
of lower epitaxial layer 204.
[0053] In FIG. 2I, top-side conductor layer 220 is formed using
conventional techniques. Top-side conductor layer 220 comprises a
Schottky barrier metal. As shown, top-side conductor layer 220
fills contact openings 218 so as to make contact with source
regions 214 along the slanted sidewalls of source regions 214, and
with lower epitaxial layer 204 along the bottom of contact openings
218. Since source regions 214 are highly doped and lower epitaxial
layer 204 is lightly doped, top-side conductor layer 220 forms an
ohmic contact with source regions 214, and forms a Schottky contact
with lower epitaxial layer 204. As can be seen, source regions 214
and the Schottky contacts are self-aligned to trenches 206.
[0054] FIGS. 3A-3E are simplified cross section views depicting
alternate process steps to those in the latter portion of the
process sequence depicted by FIGS. 2G-2I, according to another
exemplary embodiment of the invention. Thus, in this embodiment,
the same process steps depicted by FIGS. 2A through 2G are carried
out leading to the step depicted by FIG. 3B (the step depicted by
FIG. 3A is the same as the step depicted by FIG. 2G). In FIG. 3B,
upper epitaxial layer 305 is etched back to expose upper sidewalls
of dielectric material 312 sufficiently to accommodate the
subsequent formation of dielectric spacers 316. In one embodiment,
second epitaxial layer 305 is etched back by an amount in the range
of 0.05-0.5 .mu.m. In FIG. 3C, spacers 316 are formed adjacent to
the exposed upper sidewalls of dielectric material 312 using
conventional techniques. Spacers 316 are from a dielectric material
different than that of dielectric material 312. For example, if
dielectric material 312 is from oxide, spacers 316 may be from
nitride.
[0055] In FIG. 3D, the exposed surface areas of upper epitaxial
layer 305 are recessed clear through epitaxial layer 305 thus
forming contact openings 318 which extend into lower epitaxial
layer 304. By recessing clear through upper epitaxial layer 305,
only portions 314 of upper epitaxial layer 305 directly below
spacers 316 remain. Portions 314 form the transistor source
regions. As can be seen, contact openings 318 and thus source
regions 314 are self-aligned to trenches 306. In FIG. 3E, top-side
conductor layer 320 and bottom-side conductor layer 322 are formed
using conventional techniques. Conductor layer 320 comprises a
Schottky barrier metal. As shown, top-side conductor 320 fills
contact openings 318 so as to make contact with source regions 314
along sidewalls of source regions 314, and with the recessed
portions of lower epitaxial layer 304. Since source regions 314 are
highly doped and lower epitaxial layer 304 is lightly doped,
top-side conductor layer 320 forms an ohmic contact with source
regions 314, and forms a Schottky contact with lower epitaxial
layer 304.
[0056] In an alternate embodiment shown in FIG. 3EE, prior to
forming the top-side conductor layer, dielectric spacers 316 are
removed thus exposing the top surfaces of source regions 314.
Top-side conductor layer 321 thus makes contact along the top
surface and sidewalls of source regions 314. The source contact
resistance is thus reduced. In an alternate variation of the
various embodiments described above, known techniques are used to
form a thick bottom dielectric along the bottom of each trench
before forming the gates. The thick bottom dielectric reduces the
miller capacitance.
[0057] As can be seen from the various embodiments described
herein, a Schottky diode is optimally integrated with a FET in a
single cell which is repeated many times in an array of such cells.
Also, the Schottky contact and the source regions are self-aligned
to the trenches. Further, the Schottky contact results in lower on
resistance Rdson and thus lower on-state losses, and also improves
the transistor reverse recovery characteristics. Good blocking
capability is also obtained without the need for a tight cell
pitch.
[0058] In the exemplary process sequences depicted by FIGS. 2A-2I
and FIGS. 3A-3E no diffusion or implantation processes are used.
While these process sequences can be used with conventional
crystalline silicon material, they are particularly suitable for
use with such other types of materials as silicon carbide (SiC),
gallium nitride (GaN), and gallium arsenide (GaAs) where diffusion,
implantation, and dopant activation processes are difficult to
accomplish and control. In such embodiments, the substrate, the
lower and upper epitaxial layers, as well as other regions of the
transistor may comprise one of SiC, GaN, and GaAs.
[0059] Further, in conventional silicon carbide based enhancement
mode FETs, the contribution of the inversion channel to the on
resistance is particularly high. In contrast, the contribution to
the on resistance of the accumulated channel in the silicon carbide
embodiment of the accumulation transistors in FIGS. 2I and 3E is
substantially low.
[0060] FIG. 4 shows a cross section view of another embodiment of
the present invention.
[0061] In FIG. 4, shield electrodes 424 are formed below gates 410.
Shield electrode 424 is insulated from lower epitaxial layer 404 by
a shield dielectric 425, and is insulated from the overlying gate
410 by an inter-electrode dielectric 427. Shield electrodes 424
help reduce miller capacitance to a negligible amount and thereby
drastically reduce transistor switching losses. Though not shown in
FIG. 4, shield electrodes 424 are electrically connected to source
regions 414, or to the ground potential, or to other potentials as
the design and performance requirements dictate. More than one
shield electrode biased to the same or different potentials may be
formed below each gate 410 if desired. One or more methods for
forming such shield electrodes are disclosed in the
above-referenced commonly assigned application Ser. No. 11/026,276.
Also, other charge balance structures disclosed in application Ser.
No. 11/026,276 may be combined with the various embodiments
disclosed herein to further improve the performance characteristics
of the device.
[0062] A limitation of some conventional silicon carbide based
trenched-gate transistors is the low gate oxide breakdown voltage.
In accordance with the invention, this problem is addressed by
extending the Schottky contact recess deeper, e.g., to a depth
greater than one half of the depth of the gate trenches. FIG. 5
shows an exemplary embodiment wherein the Schottky contact recess
is extended to approximately the same depth as gate trenches 506.
The deep Schottky contact serves to shield gate oxide 508 from high
electric fields and thus improves the gate oxide breakdown. This
can be seen in FIG. 7A which shows simulation results for two SiC
based accumulation FETs one of which has a deeper Schottky contact
recess. The electric field lines present along the bottom of the
trench in the transistor with a shallower Schottky contact recess
(right diagram) are eliminated in the transistor with a deeper
Schottky contact recess case (left diagram). The electric field
lines below the gate trench in the right diagram reflect increasing
electric field from bottom to top. That is, the lowest-most
electric field line corresponds to the highest electric filed and
the upper-most electric field line corresponds to lowest electric
field.
[0063] A further advantage of the deep Schottky contact recess is
reduction in transistor leakage in the blocking state. This is more
clearly shown in the simulation results in FIG. 7B wherein the
drain current versus drain voltage is plotted for a deeper Schottky
contact recess versus a shallower Schottky contact recess. As can
be seen, as the drain voltage is increased from 0V to 200V, the
drain current continuously rises in the case of shallower Schottky
contact recess while the drain current remains flat for the deeper
Schottky contact recess. Thus, a substantial reduction in
transistor leakage as well as a higher gate oxide breakdown is
achieved by recessing the Schottky contact deeper into epitaxial
layer 504.
[0064] The deeply recessed Schottky contact structure (e.g., that
in FIG. 5) is particularly suitable in the silicon carbide based
transistors because the gate trenches need not extend as deep in
the epitaxial layer as compared to the silicon based transistors.
This allows shallower Schottky contact recesses which are easier to
define and etch. However, similar improvements in gate oxide
breakdown and transistor leakage can be obtained for similar
structures using other types of material such as SiC, GaN and
GaAs.
[0065] FIG. 6 shows an enhancement mode FET variation of the
accumulation FET in the FIG. 5 structure. In FIG. 6, a p-type body
region 613 extends along each trench sidewall directly below a
corresponding source region 614. As shown, the deep contact
openings 618 extends below a bottom surface of body regions 613 to
enable formation of the Schottky contact between top-side conductor
layer 620 and N- epitaxial layer 604. As in conventional MOSFETs,
when the MOSFET in FIG. 6 is in the on state, a current flows
through a channel extending along each trench sidewall in body
regions 613. In a variation of the FIG. 6 embodiment, spacers 616
are removed so that top-side conductor layer 620 contacts source
regions 614 along their top surface.
[0066] FIG. 8 shows a cross section view of an accumulation mode
FET with spacer source regions optimally integrated with a Schottky
diode in a single cell, in accordance with another exemplary
embodiment of the invention. An n-type epitaxial layer 1104 extends
over and is in contact with an n-type substrate 1102. Gate trenches
1106 extend into and terminate within epitaxial layer 1104. Each
gate trench 1106 is lined with a dielectric layer 1108 along its
sidewalls and bottom, and includes a gate 1110 and insulating
material 1112 atop gate 1110. Spacer source regions 1114 of n-type
material, for example, n-type polysilicon, are over epitaxial layer
1104 and flank each side of trenches 1106.
[0067] Spacer source regions 1114 form contact openings 1118
through which a top-side conductor layer 1120 electrically contacts
both epitaxial layer 1104 and source regions 1114. Top-side
conductor layer 1120 comprises Schottky barrier metal. Since
epitaxial layer 1104 is lightly doped, top-side conductor layer
1120 forms a Schottky contact with epitaxial layer 1104.
[0068] As in previous embodiments, the accumulation-mode transistor
in structure 1100 does not include a blocking (p-type in this
example) well or body region inside which the conduction channel is
formed. Instead a conducting channel is formed when an accumulation
layer is formed in epitaxial layer 1104 along trench sidewalls. The
FET in structure 1100 is normally on or off depending on the doping
concentration of the channel region and the doping type of gates
1110. It is turned off when channel regions are entirely depleted
and lightly inverted. Also, because no inversion channel is formed,
the channel resistance is eliminated thus improving the transistor
power handling capability and its efficiency. Further, with no pn
body diode, the losses in synchronous rectification circuits
attributable to the pn diode are eliminated.
[0069] In the FIG. 8 embodiment the FET in structure 1100 is a
vertical trenched-gate accumulation MOSFET with the top-side
conductor layer 1120 forming the source conductor and the
bottom-side conductor layer (not shown) forming the drain
conductor. In another embodiment, substrate 1102 may be p-type to
form an accumulation IGBT.
[0070] FIGS. 9A to 9H, 9I-1, and 9J-1 show cross section views at
different processing steps for forming the integrated FET/Schottky
diode structure 1100 in FIG. 8 in accordance with an embodiment of
the invention. In FIG. 9A, n-type epitaxial layer 1204 is formed
over n-type substrate 1202 using conventional methods.
Alternatively, a starting wafer which includes epitaxial layer 1204
may be used. In FIG. 9B, a mask (not shown) is used to define and
etch silicon to form trenches 1206 using conventional techniques. A
conventional dry or wet etch may be used in forming the trenches.
Trenches 1206 extend through and terminate within epitaxial layer
1204. In FIG. 9C, a dielectric layer 1208, e.g., comprising oxide,
is grown or deposited over the structure such that the sidewalls
and bottom of trenches 1206 are lined with dielectric layer
1208.
[0071] In FIG. 9D, a layer of polysilicon 1209 is deposited to fill
trenches 1206 using conventional techniques. Polysilicon layer 1209
may be in-situ doped to obtain the desired gate doping type and
concentration. In FIG. 9E, polysilicon layer 1209 is etched back
and recessed within trenches 1206 to form recessed gates 1210 using
conventional techniques.
[0072] In FIG. 9F, a dielectric layer 1211, e.g., comprising oxide,
is formed over the structure and then planarized using conventional
techniques. In FIG. 9G, a blanket etch of the planarized dielectric
layer 1211 (at least in the active region) is carried out to expose
surface areas of epitaxial layer 1204 while portions 1212 of
dielectric layer 1211 remain over gates 1210. In FIG. 9H, epitaxial
layer 1204 is etched back exposing sidewalls of dielectric material
1212 sufficiently to accommodate the subsequent formation of source
spacers 1214. In FIG. 9I-1, a conductive layer, e.g., polysilicon,
is deposited and then etched back to form highly-doped source
spacers 1214 adjacent to the exposed sidewalls of dielectric
material 1212. Where polysilicon is used to form source spacers
1214, the polysilicon may be in-situ doped to obtain highly doped
source spacers. In FIG. 9J-1, a top-side conductor layer 1220 is
formed using conventional techniques. Conductor layer 1220
comprises Schottky barrier metal. In one embodiment, conductor
layer 1220 comprises titanium. As shown, source spacers 1214 form
contact openings 1218 through which top-side conductor layer 1220
contacts epitaxial layer 1204. Conductor layer 1220 also contacts
source spacers 1214. Since source spacers 1214 are highly doped and
epitaxial layer 1204 is lightly doped, top-side conductor layer
1220 forms an ohmic contact with source spacers 1214 and a Schottky
contact with epitaxial layer 1204.
[0073] FIGS. 9I-2 and 9J-2 are cross section views depicting
alternate processing steps to the steps depicted by FIGS. 9I-1 and
9J-1, resulting in a variation of the structure in FIG. 8. In
contrast to the step in FIG. 9I-1 wherein the polysilicon etch is
stopped when the surface of epitaxial layer 1204 is exposed, in the
step shown in FIG. 9I-2, the polysilicon etch is continued to
recess the exposed epitaxial layer regions between the source
spacers. As can be seen, because of the additional etch, source
spacers 1215 in FIG. 9I-2 are smaller than source spacers 1214 in
FIG. 9I-1. In FIG. 9J-2, a top-side conductor layer 1221 is formed
over the structure using conventional methods. Top-side conductor
layer 1221 forms an ohmic contact with source spacers 1215 and a
Schottky contact with epitaxial layer 1204 in regions 1219.
[0074] As can be seen, the Schottky contact and source spacers are
self-aligned to trenches 1406. Further, the Schottky contact
results in lower on resistance Rdson and thus lower on-state
losses, and also improves the transistor reverse recovery
characteristics. Also, good blocking capability is achieved without
the need for a tight cell pitch. Moreover, as described in
connection with the FIG. 7 diagram, a further advantage of the
recessed Schottky contact of the FIGS. 9I-2, 9J-2 embodiment is
reduction in transistor leakage in the blocking state. Also, the
polysilicon source spacers consume a smaller area than the
conventional diffused source regions. This advantageously results
in a larger Schottky contact area.
[0075] FIG. 10 shows a cross section view of a variation of the
FIG. 8 embodiment wherein shield electrodes 1324 are formed below
gates 1310. Shield electrodes 1324 help reduce miller capacitance
to a negligible amount and thereby drastically reduce transistor
switching losses. Shield electrodes 1324 may be electrically biased
to the same potential as the source spacers, or to the ground
potential, or to other potentials as the design and performance
requirements dictate. More than one shield electrode biased to the
same or different potentials may be formed below each gate 1310 if
desired. One or more methods for forming such shield electrodes are
disclosed in the above-referenced commonly assigned application
Ser. No. 11/026,276.
[0076] The advantages in using a recessed Schottky contact and in
using shield electrodes may be realized by combining them in a
single structure as shown by the two examples in FIGS. 11 and 12.
FIG. 11 shows use of the recessed Schottky contact and the shield
electrode in an accumulation mode FET with polysilicon source
spacers 1415. FIG. 12 shows use of the recessed Schottky and shield
electrode in an accumulation mode FET with source regions 1517
formed using conventional diffusion methods. FIG. 13 shows a
variation of the FIG. 11 embodiment wherein the Schottky region is
modified to incorporate p-type regions 1623. P-type regions 1623
may be formed by implanting p-type dopants in the Schottky region
prior to forming top-side conductor layer 1620. The well-known
Merged P-i-N Schottky (MPS) structure is thus formed in the region
between adjacent trenches. In effect, a blocking junction is
introduced in an accumulation transistor. As is well understood in
this art, the MPS structure reduces the transistor leakage when in
blocking state.
[0077] FIG. 14 shows simulation results using the structure in FIG.
1. MEDICI device simulator was used. FIG. 14 includes a left
diagram wherein the drain current versus the drain voltage is
plotted, and a right diagram wherein the gate voltage versus gate
charge is plotted.
[0078] As the left plot shows, a low leakage current of
1.times.10.sup.-14 Amperes/.mu.m and a BVDSS of greater than 35V
are obtained, and as the right plot shows, the shield electrodes
help eliminate the miller capacitance.
[0079] In the exemplary process sequences depicted by FIGS. 9A-9H,
9I-1, 9J-1, 9I-2, and 9J-2 and the exemplary transistor structures
in FIGS. 10 and 11 no diffusion or implantation processes are used.
While these process sequences and structures can be used with
conventional crystalline silicon material, they are particularly
suitable for use with such other types of materials as silicon
carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs) where
diffusion, implantation, and dopant activation processes are
difficult to accomplish and control. In such embodiments, the
substrate, the epitaxial layer over the substrate, the source
regions, as well as other regions of the transistor may be from one
of SiC, GaN, and GaAs. Further, in conventional silicon carbide
based enhancement mode FETs, the contribution of the inversion
channel to the on resistance is particularly high. In contrast, the
contribution to the on resistance of the accumulated channel in the
silicon carbide embodiment of the accumulation transistors in FIGS.
9J-1, 9J-2, 10, and 11 is substantially low.
[0080] While the above embodiments are described using mostly
accumulation mode FETs, many of the above features and advantages
may be realized in enhancement mode FETs. For example, the process
sequences in FIGS. 2A-2I and 3A-3E may be modified by forming
p-type well regions in lower epitaxial layer 204 prior to forming
upper epitaxial layer 205. The process sequences in FIGS. 9A-9H,
9I-1, 9J-1, and 9A-9H, 9I-2 and 9J-2 may also be modified by
forming p-type well regions in epitaxial layer 1204 prior to
forming source spacers 1214 and 1215. Many other ways of modifying
the above described structures and process sequence embodiments in
order to obtain enhancement mode FETs integrated with Schottky
diode would be obvious to one skilled in the art in view of this
disclosure.
[0081] FIGS. 15A-15H are simplified cross section views at
different processing steps for forming a trenched-gate FET in
accordance with another embodiment of the invention. In FIG. 15A,
lightly doped p-type body region 1704 is formed in n-type region
1702 using conventional implant and drive techniques. In one
embodiment, n-type region 1702 comprises a highly doped substrate
region over which a lower doped n-type epitaxial layer is formed.
In such embodiment, body region 1704 is formed in the n-type
epitaxial layer.
[0082] In FIG. 15B, a dielectric stack comprising a lower
dielectric layer 1706, a middle dielectric layer 1708, and an upper
dielectric layer 1710 is formed over body region 1704. The middle
dielectric layer is required to be of a different dielectric
material than the upper dielectric material. In one embodiment, the
dielectric stack comprises oxide-nitride-oxide. As will be seen,
the thickness of the middle dielectric layer 1708 impacts the
thickness of a dielectric cap 1720 (FIG. 15D) formed over the gate
in a later step of the process, and thus must be carefully
selected. The lower dielectric layers is relatively thin in order
to minimize the reduction in thickness of dielectric layer 1720
during removal of lower dielectric layer 1706 in a later step of
the process. As shown, the dielectric stack is patterned and etched
to define opening 1712 through which a gate trench is later
formed.
[0083] In FIG. 15C, a conventional silicon etch is carried out to
form a trench 1703 extending through body region 1704 and
terminating in n-type region 1702. A gate dielectric layer 1714
lining the trench sidewalls and bottom is then formed followed by
deposition of a polysilicon layer 1716 using conventional
techniques. In FIG. 15D, polysilicon layer 1716 is recessed into
the trench to form gate 1718. A dielectric layer is formed over the
structure and then etched back such that dielectric cap 1720
remains directly above gate 1718. Nitride layer 1708 serves as an
etch stop or etch stop detection layer during the etch back of the
dielectric layer. In FIG. 15E, nitride layer 1708 is selectively
stripped to expose sidewalls of dielectric cap 1720, using known
techniques. The bottom oxide layer 1706 thus remains over body
region 1704, and dielectric cap 1720 also remains intact over gate
1718.
[0084] In FIG. 15F, a blanket source implant is carried out in the
active region of the device to form highly doped n-type regions
1722 in body regions 1704 on either sides of trench 1703.
Dielectric spacers 1724 (e.g., comprising oxide) are then formed
along the exposed sidewalls of dielectric cap 1720 using
conventional techniques. The activation and drive-in of the
implanted dopants can be carried out at this or a later stage of
the process sequence. In FIG. 15G, a silicon etch is carried out to
recess the exposed surfaces of n-type regions 1722 clear through
n-type regions 1722 and into body regions 1704 as shown. Portions
1726 of n-type regions 1722 remaining directly under spacers 1724
form the source regions of the device. Heavy body regions 1728 are
then formed in the recessed regions. In one embodiment, heavy body
regions 1728 are formed by filling the etched silicon with p+ type
silicon using conventional silicon epitaxial growth. Heavy body
regions 1728 and source regions 1726 are thus self-aligned to
trench 1703.
[0085] In FIG. 15H, dielectric cap 1720 and spacers 1724 are then
partially etched back to expose surface areas of source regions
1726. After the etch, domed dielectric 1730 remains over gate 1718.
Top conductor layer 1732 is then formed to contact source regions
1726 and heavy body regions 1728. Domed dielectric 1730 serves to
electrically insulate gate 1718 from top conductor layer 1732. In
one embodiment, n-type region 1702 is a lightly doped epitaxial
layer with a highly doped n-type substrate (not shown) extending
below the epitaxial layer. In this embodiment, a back side
conductor layer (not shown) is formed to contact the substrate, the
back side conductor layer forming the device drain terminal. A
trenched-gate FET with self-aligned source and heavy body regions
is thus formed.
[0086] In an alternate embodiment, a thick dielectric layer (e.g.,
comprising oxide) is formed along a bottom portion of trench 1703
before forming gate 1718. The thick bottom dielectric has a greater
thickness than gate dielectric 1714, and serves to reduce the gate
to drain capacitance thus improving the device switching speed. In
yet another embodiment, a shield electrode is formed below gate
1718 similar to those shown in FIGS. 4 and 10-13.
[0087] In yet another variation of the process sequence depicted by
FIGS. 15A-15H, after the steps corresponding to FIG. 15F, the
exposed silicon surfaces are not recessed, and instead a heavy body
implant and drive-in process is carried out to form heavy body
regions extending through n-type regions 1722 and into body regions
1704. A similar cross section view to that in FIG. 15G is obtained
except that heavy body regions 1728 extend under dielectric spacers
1724 due to side diffusion during the drive-in process. Dielectric
spacers 1724 need to be wide enough to ensure that the n-type
region 1722 is not entirely consumed during side diffusion of the
heavy body region. This can be achieved by selecting a thicker
middle dielectric layer 1708.
[0088] The technique of using a dielectric stack to obtain
self-aligned source and heavy body regions as illustrated in FIGS.
15A-15H can be similarly implemented in a number of the process
embodiments disclosed herein. For example, in the process
embodiment depicted by FIGS. 3A-3E, the process steps corresponding
to FIGS. 3A-3B may be replaced with the process steps depicted by
FIGS. 15B-15E in order to obtain self-aligned source regions and
Schottky contacts, as described next.
[0089] The mask used to form trenches 306 in FIG. 3A is replaced
with a dielectric stack of three dielectric layers which is
patterned and etched to form openings through which trenches are
formed (similar to that shown in FIGS. 15B and 15C). Then, in FIG.
3B, with the opening in the ONO composite layer filled with a
dielectric cap (similar to dielectric cap 1720 in FIG. 15D), the
top oxide and the intermediate nitride layer of the ONO composite
layer are removed to expose sidewalls of the dielectric cap
(similar to that shown in FIG. 15E). The remainder of the process
sequence depicted by FIGS. 3C-3E remains unchanged. Recessing of n+
epi layer 305 carried out in FIG. 3B in order to expose sidewalls
of dielectric 312 is no longer necessary, and a thinner epitaxial
layer 305 may be used.
[0090] The dielectric stack technique may also be implemented in
the process embodiment depicted by FIGS. 9A-9J by replacing the
process steps corresponding to FIGS. 9B-9 with the process steps
depicted by FIGS. 15B-15E in a similar manner to that described
above.
[0091] FIG. 16 shows a simplified isometric view of a p-channel
trenched-gate FET having a non-planar top surface (prior to top
metal formation) in accordance with another embodiment of the
invention. This invention is not limited to p-channel FETs. One
skilled in this art would know how to implement the invention in an
n-channel FET or other types of power transistors in view of this
disclosure. In FIG. 16, top metal layer 1832 is peeled back to
reveal the underlying regions. Similarly, dielectric caps 1820 are
partially removed from over the right two gates 1818 for
illustration purposes. As shown, a lightly-doped n-type body region
1804 extends over a lightly doped p-type region 1802. In one
embodiment, p-type region 1802 is an epitaxial layer formed over a
highly doped p-type substrate (not shown), and body region 1804 is
formed in epitaxial layer 1802 by implanting and driving in
appropriate dopants as know in this art.
[0092] Gate trenches 1806 extend through body region 1804 and
terminate in p-type region 1802. Each gate trench 1806 is lined
with a gate dielectric 1805 and then filled with polysilicon which
is recessed relative to a top surface of the adjacent silicon mesa
regions. A dielectric cap 1820 extends vertically over each gate
1818. Heavily doped p-type source regions 1826 are formed in body
region 1804 between adjacent trenches. As shown, a top surface of
dielectric cap 1820 is at a higher plane than the top surface of
source regions 1826, resulting in a non-planar top surface. In one
embodiment, this non-planarity is obtained by recessing the silicon
mesa between dielectric caps 1820. Heavy body regions 1828 are
intermittently formed along the stripe-shaped body regions 1804
between adjacent trenches. A top side metal layer 1832 is formed
over the structure to make electrical contact to both source
regions 1826 and heavy body regions 1828. This FET structure is
advantageous in that the cell pitch is reduced by forming the heavy
body region intermittently along the source stripe, and thus a high
density FET is achieved.
[0093] FIGS. 17A, 17B-1, and 17B-2 will be used to describe two
ways of forming the FET in FIG. 16. These figures do not show the
heavy body regions because these figures correspond to cross
section views along the front face of the isometric view in FIG.
16. In FIG. 17A, n-type body region 1904 is formed in p-type
epitaxial layer 1902 using conventional implant and drive-in
techniques. Trenches 1906, gate insulator 1907 lining trenches
1906, and the recessed polysilicon gates 1918 are formed using
known techniques. A dielectric layer is formed over the structure,
is then planarized, and finally uniformly etached back until the
silicon surface is exposed. The space directly over each gate is
thus filled with dielectric cap 1920. In one embodiment, the
exposed silicon mesa surfaces between adjacent dielectric regions
1920 are recessed to a depth intermediate the top and bottom
surfaces of dielectric region 1920, followed by a source implant to
form p-type source regions. In an alternate embodiment, the source
formation is carried out before recessing the silicon. The heavy
body regions (not shown) can be formed before or after forming the
source regions.
[0094] FIG. 17B-1 shows a variation wherein the silicon recess is
carried out so that upper sidewalls of dielectric regions 1920
become exposed (i.e., source regions 1926 have flat top surfaces).
FIG. 17B-2 shows another variation wherein the silicon recess is
carried out so that the top surface of the source regions between
adjacent trenches is bowl-shaped and thus sidewalls of dielectric
regions 1920 are not exposed. In one embodiment, this is achieved
by performing an anisotropic silicon etch. An advantage of the FIG.
17B-2 variation is that a larger source surface area is provided
for contact with the top conductor layer 1935, and thus the source
contact resistance is reduced. Also, a tighter cell pitch and thus
a high density FET is obtained by forming the heavy body regions
intermittently along the source stripes.
[0095] FIG. 18 is a simplified cross section depicting a technique
for obtaining a highly compact trenched-gate FET with self-aligned
heavy body and source regions. In FIG. 18, gate trenches with gates
2012 therein extend through p-well region 2004 and terminate within
n-type drift region 2000. In one embodiment, n-type drift region
2000 is an epitaxial layer formed over a highly doped n-type
substrate (not shown). Each gate trench includes a dielectric cap
2014 over gate 2012. As shown, the mesa regions between the two
trenches is recessed such that the silicon recess has sloped outer
walls extending from near the top of dielectric cap 2014 to the
bottom of the mesa recess.
[0096] As indicated by the solid line arrow 2019 extending
perpendicularly to the bottom surface of the mesa recess, highly
doped p-type heavy body region 2016 is formed by carrying out a
blanket implant of dopants (e.g., BF.sub.2) at a zero degree angle.
Given the zero degree angle of the heavy body implant, the opposite
slopes of each trench sidewall and its immediately adjacent outer
wall of the mesa recess, together with careful selection of the
implant dopant type and such implant variables as implant energy,
ensure that the implanted dopants do not reach the channel regions
extending along the trench sidewalls in well regions 2004.
[0097] As indicated by the two angled dashed line arrows 2018, a
blanket two-pass angled implant of n-type dopants is performed to
form source regions 2020 along the sloped walls of each mesa
recess. As shown, the upper trench corners block the source
implants from entering the central portion of the heavy body
region. As can be seen no mask is used during either the heavy body
implant or the two-pass angled source implant. The mesa recess, in
effect, creates a natural mask enabling formation of self-aligned
heavy body and source regions.
[0098] The self-aligned heavy body and source regions enable a
significant reduction in the cell pitch resulting in a highly dense
cell structure which in turn helps reduce the transistor
on-resistance. Further, self-aligned heavy body regions help
improve the unclamped inductive switching (UIL) ruggedness. Also,
forming the source and heavy body regions in a self-aligned manner,
reduces the number of masks thus reducing the manufacturing cost
while simplifying the process sequence and improving manufacturing
yield. Moreover, the particular profile of the source and heavy
body regions are advantageous in that: (i) the sloped outer walls
the mesa recess provides a large source surface area which helps
reduce the source contact resistance, and (ii) the heavy body
region overlaps under the source regions which helps improve the
transistor UIL ruggedness. Further, as will be seen, the technique
illustrated in FIG. 18 is compatible with many thick bottom
dielectric processes, and lends itself well to the LOCOS
process.
[0099] FIGS. 18A-18I, 19A-19H, 20A-20G, 21A-21H, and 22A-22F show
various process sequences wherein the technique illustrated in FIG.
18 is used to form various FET structures with self-aligned
features. Many other process sequences or variations of those
disclosed herein with the technique illustrated in FIG. 18
implemented therein can be envisioned by one skilled in this art in
view of this disclosure.
[0100] FIGS. 18A-18I show cross section views at different
processing steps for forming a trenched-gate FET with self-aligned
source and heavy body regions in accordance with another embodiment
of the invention. In FIG. 18A, conventional silicon etch and LOCOS
processes are used to form insulation-filled trench 2001 in the
termination region. A pad oxide layer (not shown) and a nitride
layer (not shown) are first formed over n-type silicon region 2000.
A first mask is then used to define the portion of silicon region
2000 in the termination region where silicon is to be removed. The
nitride layer, pad oxide and the underlying silicon region are
removed through the first mask to form trench 2001 in the
termination region. Local oxidation is then carried out to fill
trench 2001 with insulating material 2002. Although not shown, the
starting material may comprise a highly doped n-type substrate over
which n-type region 2000 is formed, for example, epitaxially.
[0101] In FIG. 18B, a blanket well implant and drive-in is carried
out to form p-type well region 2004 in silicon region 2000. The
implanted impurities may alternatively be driven in at a later
stage of the process. In FIG. 18C, a second masking step is carried
out to define and etch trenches 2006 which extend through well
region 2004 and terminate within silicon region 2000. A bottom
portion of trenches 2006 is filled with insulating material by, for
example, depositing high density plasma (HDP) oxide and then
etching the deposited HDP oxide to form thick bottom oxide
2008.
[0102] In FIG. 18D, a gate insulating layer 2010 is formed along
all surface areas including the trench sidewalls. Polysilicon is
then deposited and doped (e.g., in situ). A third mask is used to
define and etch the polysilicon to form recessed gates 2012A in the
active area, termination trench gate 2012B and the surface gate
2012C. In FIG. 18E, a dielectric layer is formed over the
structure. A fourth mask is then used to define the portion of the
active region and the opening 2015 in the termination region where
the dielectric layer is to be etched back. The dielectric layer is
etched through the mask openings until silicon is reached. Thus, in
the active region, the space directly over each gate 2012A remains
filled with dielectric material 2014A, while opening 2015 is formed
in the termination region. As can be seen, surfaces of well regions
2004B in the active region and well region 2004A in the termination
region are exposed.
[0103] In FIG. 18F, a silicon etch step is carried out to recess
the exposed silicon surface areas in the active and termination
regions. An almost bowl-shaped silicon surface is formed in well
regions 2004B between adjacent trenches in the active region and in
well region 2004A in the termination region. Next, a zero degree
heavy body implant (e.g., BF.sub.2) is carried out to form p-type
heavy body regions 2016B in well regions 2004B of the active
region, and to form heavy body region 2016A in well region 2004A of
the termination region. Source regions 2020 are then formed using a
two-pass angled source implant as depicted by arrows 2018. In the
two-pass angled implant, n-type impurities are implanted at such
angle that the upper trench corners prevent a central portion 2016B
of the heavy body regions from receiving the implant. Source
regions 2020 are thus formed immediately adjacent the trenches
while a central portion 2016B of the heavy body regions remains
intact as shown. Because of the aspect ratio of the opening 2015
(FIG. 18E) and the angle of the two-pass source implant,
termination well region 2004A does not receive the source
implants.
[0104] In FIG. 18G, an implant activation step is carried out to
drive in the implanted dopants. A fifth mask is then used to define
and etch insulating layer 2014C to form gate contact opening 2019.
In FIG. 18H, a conductor layer (e.g., comprising metal) is then
formed over the structure. A sixth mask is used to define and etch
the conductor layer in order to isolate source conductor 2021A from
gate conductor 2021B. In FIG. 18I, a passivation layer is
deposited. A seventh mask is then used to etch portions of the
passivation layer to thereby define source and gate areas where
wirebond contacts are to be made. In embodiments wherein a
passivation layer is not necessary, the corresponding mask and
process steps are eliminated.
[0105] As can be seen no mask is used in forming heavy body regions
2016B and source regions 2020. Also, both the heavy body and source
regions are self-aligned with the trench edges. Further, heavy body
region 2016B overlaps beneath source regions 2020 but does not
extend into the channel regions. A tight cell pitch with an
exceptional snapback and UIL ruggedness is thus achieved. The small
cell pitch helps achieve a lower Rdson. Also, since source regions
2020 are formed along the outer curved surfaces of well regions
2004B, a larger source contact area is obtained and thus a lower
source contact resistance is achieved. Moreover, the simple process
sequence uses a reduced number of masking steps, is compatible with
many thick bottom oxide (TBO) process modules, and lends itself
well to the LOCOS method of forming the TBO.
[0106] The cross sections in FIGS. 18A-18I depict merely an
exemplary process sequence and an exemplary termination structure.
This process sequence may be optimized in various ways to further
reduce the number of masks and implement different termination
structures including those illustrated by the process sequences in
FIGS. 19A-19H, 20A-20G, 21A-21H, and 22A-22F described next.
[0107] FIGS. 19A-19H are cross section views of a process sequence
in which instead of a surface polysilicon a trenched polysilicon is
formed which enables reducing the number of masks by one compared
to that in the process of FIGS. 18A-18I. The process steps
corresponding to FIGS. 19A-19C are similar to those corresponding
to FIGS. 18A-18C and thus will not be explained. In FIG. 19D, gate
insulator 2110 is formed and then polysilicon is deposited and
doped. A blanket etch of the deposited polysilicon is carried out
so that recessed gates 2112 remain in the trenches. Here, the gate
mask in FIG. 18D of the previous embodiment is eliminated. In FIG.
19E, a similar sequence of process steps to that in FIG. 18E is
carried out so that the space directly over each gate 2112 is
filled with dielectric material 2114A, while opening 2115 is formed
in the dielectric layer over termination p-well 2014A. In FIG. 19F,
a similar sequence of process steps to that in FIG. 18F is carried
out to form self-aligned heavy body regions 2116A and 2116B and
self-aligned source regions 2120.
[0108] In FIG. 19G, a gate contact mask (the fourth mask) is used
to define and etch a gate contact opening 2113 in the dielectric
layer over the far left gate trench, followed by activation of the
implanted dopants. Gate contact opening 2113 provides electrical
access to the trenched polysilicon gates which are interconnected
along a third dimension not shown in FIG. 19G. In an alternate
embodiment, termination p-well 2104A is allowed to float thus
eliminating the need for termination source conductor 2121A.
[0109] In FIG. 19H, a conductor layer (e.g., comprising metal) is
deposited followed by a masking step (fifth) to define and isolate
source conductor portions 2121A from gate conductor portion 2121B.
As can be seen, only five masks are used in the process depicted by
FIGS. 19A-19H. The thin layer directly beneath the gate and source
conductor layers is an optional barrier metal.
[0110] FIGS. 20A-20G are cross section views of another process
sequence using fewer masks as compared to the process depicted by
FIGS. 18A-18I. The process steps corresponding to FIGS. 20A-20D are
similar to those corresponding to FIGS. 18A-18D, and thus will not
be explained. The process sequence corresponding to FIG. 20E is
similar to that corresponding to FIG. 18E expect that the fourth
mask is used to form an additional opening 2217 in the termination
dielectric layer over surface polysilicon 2212C. The process
sequence corresponding to FIG. 20F is similar to that corresponding
to FIG. 18F. However, because of opening 2217 (in FIG. 20E) over
surface polysilicon 2212C, the silicon etch for recessing the
exposed mesa surfaces also etches the exposed portion of surface
polysilicon 2212C creating an opening 2218 therein. Sidewalls of
the surface polysilicon thus become exposed through contact opening
2218. Depending on the depth of mesa recess in the active area and
the thickness of surface polysilicon 2212C, the mesa recess etch
may etch clear through surface polysilicon 2212C or leave a thin
layer of polysilicon along the bottom of opening 2218. In one
embodiment, opening 2218 is formed such that its aspect ratio
allows the two angled source implants 2218 to reach the sidewalls
of surface polysilicon portions 2213A and 2213B. This
advantageously minimizes the contact resistance between later
formed gate conductor layer 2221B (FIG. 20G) and surface
polysilicon portions 2213A and 2213B.
[0111] The process sequence corresponding to FIG. 20G is similar to
that corresponding to FIG. 18H except that the FIG. 20G process
sequence includes activation of the implanted regions. Also, unlike
FIG. 18H wherein gate conductor 2021B contacts a top surface of
polysilicon 2012C, gate conductor 2221B in FIG. 20G contacts the
sidewalls of the surface polysilicon through opening 2218. If after
the silicon recess step in FIG. 20F the surface polysilicon 2212C
is not fully etched through (i.e., a portion of it remains along
the bottom of opening 2218), then gate conductor 2021B would also
contact a surface area of the remaining polysilicon in opening
2218.
[0112] In FIG. 20G, the thin layer directly beneath the source and
gate conductor layers is an optional barrier metal. This embodiment
is advantageous in that similar to the FIGS. 19A-19H embodiment
only five masks are used up through the step of forming the
top-side conductors, and also surface area is preserved by
eliminating the need for source conductor layer 2121A (FIG. 19H)
surrounding the peripheral gate conductor layer 2121B (FIG.
19H).
[0113] FIGS. 21A-21H are cross section views at different
processing steps for forming a similar trenched-gate FET to that
resulting from the process depicted by FIGS. 18A-18I, except that a
Schottky diode is integrated with the FET. The process sequence
corresponding to FIG. 21A is similar to that corresponding to FIG.
18A and thus will not be explained. In FIG. 21B, using a p-well
blocking mask (the second mask), p-type impurities are implanted
and driven in to form well regions 2304 in n-type silicon region
2300. The implanted impurities may alternatively be driven in at a
later stage of the process sequence. The p-well blocking mask
prevents the p-type impurities from being implanted into a portion
2303 of silicon region 2300 which, as will be seen, forms the
Schottky region.
[0114] In FIGS. 21C and 21D, similar sets of process steps to those
for FIGS. 18C and 18D are carried out and thus will not be
described. In FIG. 21E, similar process steps to those for FIG. 18E
are carried out however, the contact mask (fifth) and dielectric
planarization steps are carried out such that portion 2314D of the
insulating layer remains over Schottky region 2303 to prevent this
region from receiving dopants during the later source and heavy
body implant steps (FIG. 21F). The process sequence corresponding
to FIG. 21F is similar to that corresponding to FIG. 18F and thus
will not be described.
[0115] In FIG. 21G, an implant activation step is carried out to
drive in the implanted dopants. A sixth mask is then used to define
and etch both the insulating region 2314D from over the Schottky
region 2303 and to form gate contact opening 2319 over the surface
gate 2312C. The process sequence corresponding to FIG. 21H is the
same as that corresponding to FIG. 18H, except that source
conductor 2321A, in addition to contacting the source and heavy
body regions, contacts Schottky region 2303 to form a Schottky
contact with silicon region 2300 using, for example, titanium
silicide as a barrier metal. A trenched-gate FET with an integrated
Schottky diode is thus formed.
[0116] While FIGS. 21A-21H show how a Schottky diode is integrated
with the process sequence depicted by FIGS. 18A-18I, the process
sequences depicted by each of FIGS. 19A-19H, 20A-20G, 21A-21H,
22A-22F, 23A-23I, and 24A-24I may similarly be modified to
integrate a Schottky diode therewith.
[0117] FIGS. 22A-22F are cross section views of another process
sequence for forming a trenched-gate FET in accordance with an
embodiment wherein the number of masks through formation of the
top-side source and gate conductors is reduced to four. In FIG.
22A, a pad oxide layer (not shown) is formed over n-type silicon
region 2400. Dopants of p-type conductivity are implanted and
driven in to form p-well region 2404 in n-type silicon region 2400.
The implanted impurities may alternatively be driven in at a later
stage of the process sequence. A first mask is used to define and
etch both trenches 2406 in the active region and wide trench 2401
in the termination region. A LOCOS thick bottom oxide (TBO) process
is then used to form a layer of insulating material 2402 along the
bottom portion of both the active trenches 2406 and the wide
termination trench 240 ltrench, as well as over a top surface of
the silicon mesa between adjacent trenches.
[0118] The process steps corresponding to FIG. 22C are similar to
those corresponding to FIG. 20D, however in FIG. 22C instead of
forming a planar surface polysilicon 2212C as in FIG. 20D,
polysilicon 2412C extends over termination p-well 2204A and down
into wide trench 2401. The process steps corresponding to each of
FIGS. 22D, 22E, and 22F are similar to those corresponding to each
of FIGS. 20E, 20F, and 20G, respectively, and thus will not be
described. As can be seen in FIG. 22F, the gate conductor 2421B
makes contact to sidewalls of gate 2412D inside the wide trench in
the termination region. As in the FIGS. 20A-20G embodiment, if
after the silicon recess step in FIG. 22E, the termination
polysilicon 2412C is not fully etched through (i.e., a portion of
it remains along the bottom of opening 2218 in polysilicon 2412C),
then gate conductor 2021B would also contact a surface area of the
remaining polysilicon in opening 2218. A total of 4 masks are used,
which together with the passivation pad mask (as, for example,
identified in the process sequence corresponding to FIG. 18I) makes
a total of 5 masks.
[0119] FIGS. 23A-23I are cross section views at different
processing steps for forming a trenched-gate FET with self-aligned
features, in accordance with yet another embodiment of the
invention. The process steps corresponding to FIGS. 23A-23D are
similar to those corresponding to FIGS. 18A-18D, and thus will not
be described. In FIG. 23E, a dielectric layer is formed over the
structure. A fourth mask is then used to cover the termination
region as a dielectric planaraization etch is carried out in the
active region so that dielectric caps 2514A remain over each trench
gate 2512A. In FIG. 23F, a mesa recess etch is carried out to
recess the p-type well regions 2504B below the top surface of
dielectric caps 2514A such that upper sidewalls of dielectric caps
2514A become exposed. A blanket implant of dopants (e.g., arsenic)
is then carried out to form n+ regions 2517 in well regions 2504B
between adjacent trenches. Nitride spacers 2518 are then formed
over n+ regions 2517 along the exposed sidewalls of dielectric caps
2514A using conventional techniques. In FIG. 23G, the exposed
silicon mesa between adjacent spacers 2518 are recessed to a depth
within well regions 2504B. The silicon recess removes the middle
portion of n+ region 2517 (FIG. 23F), leaving outer portions 2520
of n+ regions 2517 extending directly below spacers 2518 intact.
Portions 2520 form the transistor source regions. Dopants of p-type
impurity are then implanted to form heavy body regions 2516.
[0120] In FIG. 23H, nitride spacers 2518 are removed using
conventional techniques. A fifth mask is then used in the
termination region to create openings 2515 and 2519 in dielectric
region 2514B. In FIG. 23I, source and gate conductors are formed in
a similar manner to those in FIG. 18I. A total of six masks are
thus used. This process sequence is particularly suitable for
forming trench gate FETs with wide pitch body. Also, this process
sequence advantageously results in formation of source and heavy
body regions which are self-aligned to the trenches.
[0121] FIGS. 24A-24I are cross section views at different
processing steps for forming a trenched-gate FET in accordance with
yet another embodiment of the invention. The process steps
corresponding to FIGS. 24A-24D are similar to those corresponding
to FIGS. 19A-19D and thus will not be described. In FIG. 24E, a
dielectric layer is formed over the structure. A third mask is then
used to cover the termination region as a dielectric planaraization
etch is carried out in the active region so as to form dielectric
caps 2614A over each trench gate 2612. The process steps
corresponding to FIGS. 24F and 24G are similar to those
corresponding to FIGS. 23F and 23G, respectively, and thus will be
not described.
[0122] In FIG. 24H, nitride spacers 2618 are removed using
conventional techniques. A fourth mask is then used in the
termination region to create opening 2615 in dielectric region
2614B (FIG. 24G). In FIG. 24I, a metal layer is formed over the
structure, and a fifth mask is used to define source conductor
2621A and gate conductor 2621B. As shown, source conductor 2621A
contacts heavy body regions 2616 and source regions 2620 along
their top surface and sidewall. Termination well region 2604B
electrically floats. Alternatively, well region 2604B may be biased
via an electrical contact made along the dimension into the
page.
[0123] Similar to the embodiment represented by FIGS. 23A-23I, this
embodiment is suitable for forming trench gate FETs with wide pitch
body, and has source and heavy body regions which are self-aligned
to the trenches. However, this embodiment advantageously requires
one less mask than the FIG. 23A-23I embodiment.
[0124] While the various process sequences depicted by FIGS.
18A-18I, 19A-19H, 20A-20G, 21A-21H, 22A-22F, 23A-23I, and 24A-24I
are shown in the context of a single gate trench structure,
modifying these process sequence to include a shield electrode
beneath the gate, similar to shield gate 1324 in FIG. 10, would be
obvious to one skilled in this art in view of this disclosure.
[0125] The various structures and methods of the present invention
may be combined with one or more of a number of charge spreading
techniques disclosed in the above-referenced commonly assigned
application Ser. No. 11/026,276, to achieve even a lower
on-resistance, higher blocking capability and higher
efficiency.
[0126] The cross-section views of the different embodiments may not
be to scale, and as such are not intended to limit the possible
variations in the layout design of the corresponding structures.
Also, the various transistors can be formed in open cell
architecture (e.g., stripe) or closed cell architecture (e.g.,
hexagonal or square shaped cells).
[0127] Although a number of specific embodiments are shown and
described above, embodiments of the invention are not limited
thereto. For example, it is understood that the doping polarities
of the structures shown and described could be reversed and/or the
doping concentrations of the various elements could be altered
without departing from the invention. As another example, various
exemplary accumulation-mode and enhancement mode vertical
transistors described above have the trenches terminating in the
drift region (a lightly doped epitaxial layer extending over the
substrate), but they can also terminate in the more heavily doped
substrate. Also, the features of one or more embodiments of the
invention may be combined with one or more features of other
embodiments of the invention without departing from the scope of
the invention. For this and other reasons, therefore, the above
description should not be taken as limiting the scope of the
invention, which is defined by the appended claims.
* * * * *