U.S. patent application number 12/969250 was filed with the patent office on 2012-05-31 for tsv substrate structure and the stacked assembly thereof.
This patent application is currently assigned to Industrial Technology Research Institute. Invention is credited to Tzu-Kun Ku, Cha-Hsin Lin, Pei-Jer Tzeng, Chung-Chih Wang.
Application Number | 20120133030 12/969250 |
Document ID | / |
Family ID | 46126057 |
Filed Date | 2012-05-31 |
United States Patent
Application |
20120133030 |
Kind Code |
A1 |
Wang; Chung-Chih ; et
al. |
May 31, 2012 |
TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF
Abstract
The disclosure provides a TSV substrate structure and the
stacked assembly of a plurality of the substrate structures, the
TSV substrate structure including: a substrate comprising a first
surface, a corresponding second surface, and a TSV communicating
the first surface with the second surface through the substrate;
and a conductor unit completely filling the TSV, the conductor unit
comprising a conductor body which has a first and a second ends
corresponding to the first and second surfaces of the substrate,
respectively.
Inventors: |
Wang; Chung-Chih; (Taipei
County, TW) ; Tzeng; Pei-Jer; (Hsinchu City, TW)
; Lin; Cha-Hsin; (Tainan City, TW) ; Ku;
Tzu-Kun; (Hsinchu City, TW) |
Assignee: |
Industrial Technology Research
Institute
Hsinchu
TW
|
Family ID: |
46126057 |
Appl. No.: |
12/969250 |
Filed: |
December 15, 2010 |
Current U.S.
Class: |
257/621 ;
257/E29.112 |
Current CPC
Class: |
H01L 2224/05009
20130101; H01L 2225/06541 20130101; H01L 2924/00014 20130101; H01L
2224/0557 20130101; H01L 2224/16 20130101; H01L 2224/16146
20130101; H01L 2224/8114 20130101; H01L 2224/13023 20130101; H01L
21/76871 20130101; H01L 2224/81911 20130101; H01L 21/76865
20130101; H01L 2924/00014 20130101; H01L 2224/13009 20130101; H01L
21/76883 20130101; H01L 25/50 20130101; H01L 23/5384 20130101; H01L
23/562 20130101; H01L 2224/13 20130101; H01L 21/3212 20130101; H01L
23/481 20130101; H01L 2224/05552 20130101; H01L 21/32133 20130101;
H01L 2224/81 20130101; H01L 2224/0401 20130101; H01L 21/76898
20130101 |
Class at
Publication: |
257/621 ;
257/E29.112 |
International
Class: |
H01L 29/41 20060101
H01L029/41 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 26, 2010 |
TW |
099141056 |
Claims
1. A substrate structure comprising: a substrate comprising a first
surface, a corresponding second surface, and a through-silicon via
(TSV) communicating the first surface with the second surface
through the substrate; and a conductor unit completely filling the
TSV, the conductor unit comprising a conductor body which has a
first and a second ends corresponding to the first and second
surfaces of the substrate, respectively.
2. The substrate structure of claim 1, wherein the conductor unit
further comprises a first extensional part formed on the side
surface of the conductor body in proximity to the first end.
3. The substrate structure of claim 2, wherein the first
extensional part surrounds the conductor body.
4. The substrate structure of claim 2, wherein the conductor unit
further comprises a second extensional part formed on the side
surface of the conductor body in proximity to the second end.
5. The substrate structure of claim 4, wherein the second
extensional part surrounds the conductor body.
6. The substrate structure of claim 1, wherein the conductor unit
further comprises: a first protrusion formed on the base surface of
the conductor body at the first end.
7. The substrate structure of claim 6, wherein the conductor unit
further comprises: a second protrusion formed on the base surface
of the conductor body at the second end.
8. The substrate structure of claim 6, wherein the conductor unit
further comprises: a recess formed in the base surface of the
conductor body at the second end, wherein the recess is not smaller
than the protrusion in area and is not higher than the protrusion
in highness.
9. The substrate structure of claim 1, wherein the conductor unit
further comprises: a first recess formed in the base surface of the
conductor body at the first end.
10. The substrate structure of claim 9, wherein the conductor unit
further comprises: a second recess formed in the base surface of
the conductor body at the second end.
11. The substrate structure of claim 1, wherein the substrate is
selected from the group consisting of a die, a chip, a wafer, an
interposer, or the combinations thereof.
12. The substrate structure of claim 1, wherein the substrate
further comprises: a first insulator layer formed on the side
surface of the TSV.
13. The substrate structure of claim 12, wherein the first
insulator layer further comprises: a first recessed portion formed
on the base surface of the conductor body at the first end, wherein
the area of the first recessed portion is not larger than the
cross-sectional area of the conductor body.
14. The substrate structure of claim 13, wherein the first
insulator layer further comprises: a second recessed portion formed
on the base surface of the conductor body at the second end,
wherein the area of the second recessed portion is not larger than
the cross-sectional area of the conductor body.
15. The substrate structure of claim 1, wherein the substrate
further comprises: a second insulator layer formed on the first
surface of the substrate.
16. The substrate structure of claim 15, wherein the substrate
further comprises: a third insulator layer formed on the second
surface of the substrate.
17. A stacked assembly comprising a plurality of substrate
structures stacked on each other, each of the substrate structures
comprising: a substrate comprising a first surface, a corresponding
second surface, and a TSV communicating the first surface with the
second surface through the substrate; and a conductor unit
completely filling the TSV, the conductor unit comprising a
conductor body which has a first and a second ends corresponding to
the first and second sides of the substrate, respectively.
18. The stacked assembly of claim 17, wherein the conductor unit
further comprises a first extensional part formed on the side
surface of the conductor body in proximity to the first end.
19. The stacked assembly of claim 18, wherein the first extensional
part surrounds the conductor body.
20. The stacked assembly of claim 18, wherein the conductor unit
further comprises a second extensional part formed on the side
surface of the conductor body in proximity to the second end.
21. The stacked assembly of claim 20, wherein the second
extensional part surrounds the conductor body.
22. The stacked assembly of claim 17, wherein the conductor unit
further comprises: a first protrusion formed on the base surface of
the conductor body at the first end.
23. The stacked assembly of claim 22, wherein the conductor unit
further comprises: a second protrusion formed on the base surface
of the conductor body at the second end.
24. The stacked assembly of claim 22, wherein the conductor unit
further comprises: a recess formed in the base surface of the
conductor body at the second end, wherein the recess is not smaller
than the protrusion in area and is not higher than the protrusion
in highness.
25. The stacked assembly of claim 17, wherein the conductor unit
further comprises: a first recess formed in the base surface of the
conductor body at the first end.
26. The stacked assembly of claim 25, wherein the conductor unit
further comprises: a second recess formed in the base surface of
the conductor body at the second end.
27. The stacked assembly of claim 17, wherein the substrate is
selected from the group consisting of a die, a chip, a wafer, an
interposer, or the combinations thereof.
28. The stacked assembly of claim 17, wherein the substrate further
comprises: a first insulator layer formed on the side surface of
the TSV.
29. The stacked assembly of claim 28, wherein the first insulator
layer further comprises: a first recessed portion formed on the
base surface of the conductor body at the first end, wherein the
area of the first recessed portion is not larger than the
cross-sectional area of the conductor body.
30. The stacked assembly of claim 29, wherein the first insulator
layer further comprises: a second recessed portion formed on the
base surface of the conductor body at the second end, wherein the
area of the second recessed portion is not larger than the
cross-sectional area of the conductor body.
31. The stacked assembly of claim 17, wherein the substrate further
comprises: a second insulator layer formed on the first surface of
the substrate.
32. The stacked assembly of claim 31, wherein the substrate further
comprises: a third insulator layer formed on the second surface of
the substrate.
33. The stacked assembly of claim 17, wherein the TSV of each of
the substrate structures corresponds to each other.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a device of
three-dimensional integrated circuit (3DIC), and more particularly,
to a substrate structure with a through-silicon via (TSV) and the
stacked assembly of a plurality of the substrate structures.
TECHNICAL BACKGROUND
[0002] The advantages of the three-dimensional-integrated-circuit
(3DIC) technique, such as high performance, low power dissipation,
low cost, compactness, integration of hetero-generous IC
substrates, lead to a potential trend for developing the System on
Chip (SoC). Wherein the through-silicon-via (TSV) technique plays a
key role of being capable of overcoming the limitations by the IC
fabrication process and the low dielectric-constant material, so
that the interconnection among the stacked IC chips can be with
lower cost and higher performance.
[0003] However, misalignment between the TSVs of the stacked IC
substrates or conductor bumps between the stacked IC chips happened
frequently in the assembly process of the 3DIC, which may lead to
potential errors or distortions in the communication of electrical
signals. Furthermore, the reliability of the interconnection or
assembly of the TSVs is subject to the bumps, which tend to
increase the resistance of TSV connection and, even more, to cause
cracks or defects of opened circuit. Therefore, it is in need to
develop a reliable structure of TSV substrates.
TECHNICAL SUMMARY
[0004] According to one aspect of the present disclosure, a first
embodiment provides a TSV substrate structure including: a
substrate comprising a first surface, a corresponding second
surface, and a TSV communicating the first surface with the second
surface through the substrate; and a conductor unit completely
filling the TSV, the conductor unit comprising a conductor body
which has a first and a second ends corresponding to the first and
second surfaces of the substrate, respectively.
[0005] According to another aspect of the present disclosure, a
second embodiment provides a stacked assembly comprising a
plurality of substrate structures stacked on each other, each of
the substrate structures including: a substrate comprising a first
surface, a corresponding second surface, and a TSV communicating
the first surface with the second surface through the substrate;
and a conductor unit completely filling the TSV, the conductor unit
comprising a conductor body which has a first and a second ends
corresponding to the first and second surfaces of the substrate,
respectively.
[0006] Further scope of applicability of the present application
will become more apparent from the detailed description given
hereinafter. However, it should be understood that the detailed
description and specific examples, while indicating exemplary
embodiments of the disclosure, are given by way of illustration
only, since various changes and modifications within the spirit and
scope of the disclosure will become apparent to those skilled in
the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The present disclosure will become more fully understood
from the detailed description given herein below and the
accompanying drawings which are given by way of illustration only,
and thus are not limitative of the present disclosure and
wherein:
[0008] FIG. 1 is a perspective view of a TSV substrate structure
according to a first embodiment of the present disclosure.
[0009] FIGS. 2A and 2B are TSV substrate structures of the
protrusion.sub.top-protrusion.sub.bottom and
recess.sub.top-recess.sub.bottom types, respectively, according to
the first embodiment.
[0010] FIGS. 3A to 3C are architectures of the stacked assembly
according to the second embodiment of the present disclosure:
example 1 to 3, respectively.
[0011] FIGS. 4A and 4B are architectures of the stacked assembly of
example 4 according to the second embodiment: with and without the
insulator layer on the substrate surfaces, respectively.
[0012] FIGS. 5A and 5B are architectures of the stacked assembly of
example 5 according to the second embodiment: with and without the
insulator layer on the substrate surfaces, respectively.
[0013] FIGS. 6A and 6B are architectures of the stacked assembly of
example 6 according to the second embodiment: with and without the
insulator layer on the substrate surfaces, respectively.
[0014] FIGS. 7A and 7B are architectures of the stacked assembly of
example 7 according to the second embodiment: with and without the
insulator layer on the substrate surfaces, respectively.
[0015] FIGS. 8A to 8M are the evolutional steps of fabricating the
TSV substrate structure of FIG. 1.
DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
[0016] For further understanding and recognizing the fulfilled
functions and structural characteristics of the disclosure, several
exemplary embodiments cooperating with detailed description are
presented as the following. Hereinafter, for the description of the
embodiments, in the case of describing as forming each layer
(film), portions, patterns or structures "on" or "under"
substrates, each layer (film), portions, or patterns, "on" or
"under" includes all of "directly" or "indirectly" formed things.
In addition, a standard about "on" or "under" each layer will be
described based on the drawings. In the drawings, a thickness or
size of each layer is shown roughly, exaggeratedly, or briefly for
sake of convenience of description or for a definite description.
In addition, a size of each element does not reflect entirely real
size.
[0017] Please refer to FIG. 1, which is a perspective view of a TSV
substrate structure according to a first embodiment of the present
disclosure. In FIG. 1, the TSV substrate structure 100 comprises a
substrate 110 having a TSV 130 and a conductor unit 120 completely
filling the TSV 130. The conductor unit 120 is used as a channel of
electrical and thermal interconnection to build up a 3DIC.
[0018] The substrate 110 has a top and a bottom surfaces, or in
terms of the first surface 111 and second surface 112 in this
embodiment. The substrate 110 includes at least one TSV 130, which
communicates the first surface 111 with the second surface 112
through the substrate body. The TSV 130 itself has a column-shaped
space to receive conductor or metal, so as to connect the two sides
of the substrate 110 electrically or thermally. For sake of
simplicity, only one TSV is depicted in the specification and
drawings to illustrate the structure and fabrication of the
embodiments; but is not limited thereby, which can be more than one
TSV. Moreover, the TSV 130 or the conductor unit 120 has a column
body with a circular cross-section; but is not limited thereby,
which can be with a cross-section of rectangle, rhombus, polygon,
or other shapes in accordance with the practical demand.
[0019] As shown in FIG. 1, an insulator layer 114 is formed on the
side surface of the TSV 130 to electrically isolate the conductor
unit 120 from the devices or circuits in the substrate 110. In this
embodiment, the insulator layer 114 is also formed on the first
and/or second surfaces 111/112 of the substrate 110. The substrate
110 may be a die, a chip, a wafer, an interposer connecting a die
or a chip to a printed-circuit board (PCB), or the combinations
thereof, which are all applicable to the embodiment.
[0020] The conductor unit 120, which completely fills the TSV 130
and has a conductor body 125 corresponding to the TSV 130, has a
top and bottom terminals, or in terms of the first end 121 and
second end 122, corresponding to the first and second surfaces
111/112 of the substrate, respectively. This embodiment is
characterized partly by the solid and complete filling of the
conductor body 125 in the TSV 130, so as to increase conductivity
and reliability of the conductor unit 120. This embodiment is also
characterized by an extensional part 123 formed on the side surface
of the conductor body in proximity to the first or/and second ends
of the conductor unit 120. As shown in FIG. 1, the extensional
parts 123 of conductor are formed to surround the conductor body
125 at both ends. The extensional part 123 is used to enhance the
positioning area of alignment when more than one TSV substrate
structures 100 are stacked or assembled to form a 3DIC device. The
extensional part 123 is provided in this embodiment to increase the
tolerance of aligning the TSVs between the TSV substrate structures
100 and hence to diminish the parasitical devices or circuits due
to the misalignment. The extensional part 123 may be formed at one
or both ends of the conductor unit 120, or may not be formed at
either end; this depends on the practical demand.
[0021] In order to facilitate alignment and assembly of the IC
substrates with TSVs and to enhance the structural robustness of
the assembly, the conductor unit 120 further comprises a recess 127
formed in the base surface of the conductor body 125 at the first
end 121 and a protrusion 128 formed on the other base surface of
the conductor body 125 at the second end 122, as the embodiment
illustrated in FIG. 1. It should be noted that the recess 127 is
not smaller than the protrusion 128 in area and is not higher than
the protrusion 128 in highness, to facilitate the alignment and
assembly in the succeeding fabrication process of the stacked
assembly of the TSV IC substrates. The conductor unit 120 is
composed of copper in this embodiment, while it can be composed of
the other metal or conductor material. Furthermore, the conductor
unit 120 has a cross-section of circle in the embodiment, while it
can be with a cross-section of rectangle, rhombus, polygon, or
other shapes corresponding to the TSV 130.
[0022] The formation of the protrusion on or the recess in the base
surfaces of the two ends the conductor unit 120 may be in the other
type. For example, a recess may be formed in the bottom surface of
the conductor body while a protrusion formed on the top surface of
the conductor body. Further, two protrusions may be formed
respectively on both base surfaces of the conductor body as shown
in FIG. 2A; or two recesses may be formed respectively in both base
surfaces of the conductor body as shown in FIG. 2B. The IC
substrates with one of the two forgoing types of conductor units in
the TSV 130 can be assembled correspondingly. This will be
described in detail in the succeeding embodiments. The protrusion
or recess may be formed at one or both ends of the conductor unit
120, or may not be formed at either end; this depends on the
practical demand.
[0023] To construct a 3DIC device, IC substrates of various
potential types of conductor units in the TSV in the first
embodiment may be stacked on each other or on a carrier. In a
second embodiment according this present disclosure, a stacked
assembly comprises: a first TSV substrate structure formed of one
of possible types of conductor units in the TSV according to the
first embodiment, a second TSV substrate structure formed of one of
possible types of conductor units in the TSV according to the first
embodiment, wherein the second TSV substrate structure is stacked
on the first TSV substrate structure. Preferably, the TSV in the
first TSV substrate structure corresponds to the TSV in the second
TSV substrate structure.
[0024] Please refer to FIGS. 3A to 3C, which illustrate three
examples of the stacked assembly according to the second
embodiment. Example 1 provides the stacked assembly of the TSV
substrate structures of the recess.sub.top-protrusion.sub.bottom
type as schematically shown in FIG. 3A, where a recess is formed in
the top surface of the conductor body while a protrusion formed on
the bottom surface of the conductor body in each TSV substrate
structure. Example 2 describes the stacked assembly of the TSV
substrate structures of the protrusion.sub.top-recess.sub.bottom
type as schematically shown in FIG. 3B, where a protrusion is
formed on the top surface of the conductor body while a recess
formed in the bottom surface of the conductor body in each TSV
substrate structure. On the contrary, example 3 describes the
stacked assembly of the TSV substrate structures of the
recess.sub.top-recess.sub.bottom and
protrusion.sub.top-protrusion.sub.bottom types as schematically
shown in FIG. 3C, where the recess.sub.top-recess.sub.bottom type
means that two recesses are formed respectively in both base
surfaces of the conductor body, while the
protrusion.sub.top-protrusion.sub.bottom type is that two
protrusions are formed respectively on both base surfaces. It
should be noted in the neighboring TSV IC substrates that the
recess is not smaller than the corresponding protrusion in area and
is not higher than the corresponding protrusion in highness, to
facilitate the alignment and assembly of the TSV IC substrates. The
assembly may be proceeded as the following: providing TSV substrate
structures with corresponding recesses and/or protrusions; aligning
the TSVs and corresponding the conductor unit of the TSV substrate
structures, and stacking one TSV substrate structure on the another
one; and pressing the stacked TSV substrate structures vertically
to the substrate surfaces. Since the recess is not smaller than the
corresponding protrusion in area and is not higher than the
corresponding protrusion in highness, the pressure on the stacked
TSV substrate structures can deform the conductor of metal or the
like to fix the recess and protrusion tightly and coincidentally at
the connection point, so as to increase conductivity and
reliability of the TSV interconnection.
[0025] Based on the TSV substrate structures of the
recess.sub.top-protrusion.sub.bottom type, several more exemplary
embodiments of various TSV substrate structures are provided below.
Example 4 provides the stacked assembly of the TSV substrate
structures as schematically shown in FIGS. 4A and 4B, where each
TSV substrate structure have a conductor unit with an extensional
part surrounding the conductor body only in proximity to the
bottom; FIG. 4A illustrates each substrate with insulator layers on
the side surface of the TSV and on the top and bottom surfaces of
the substrate, while FIG. 4B illustrates each substrate with
insulator layers only on the side surface of the TSV. Example 5
provides the stacked assembly of the TSV substrate structures as
schematically shown in FIGS. 5A and 5B, where each TSV substrate
structure have a conductor unit with an extensional part
surrounding the conductor body only in proximity to the top; FIG.
5A illustrates each substrate with insulator layers on the side
surface of the TSV and on the top and bottom surfaces of the
substrate, while FIG. 5B illustrates each substrate with insulator
layers only on the side surface of the TSV. Example 6 provides the
stacked assembly of the TSV substrate structures as schematically
shown in FIGS. 6A and 6B, where each TSV substrate structure does
not have any extensional part at the top or bottom; FIG. 6A
illustrates each substrate with insulator layers on the side
surface of the TSV and on the top and bottom surfaces of the
substrate, while FIG. 6B illustrates each substrate with insulator
layers only on the side surface of the TSV.
[0026] Example 7 provides the stacked assembly of the TSV substrate
structures as schematically shown in FIGS. 7A and 7B, where each
TSV substrate structure does not have any extensional part at
either the top or bottom, each TSV substrate structure has a
protrusion formed on the bottom surface of the conductor unit, and
the insulator layer further includes a recessed portion formed on
the base surface of the conductor body at the top end, wherein the
area of the recessed portion is not larger than the cross-sectional
area of the conductor body and is larger than the protrusion at the
bottom; FIG. 7A illustrates each substrate with insulator layers on
the side surface of the TSV and on the top and bottom surfaces of
the substrate, while FIG. 7B illustrates each substrate with
insulator layers only on the side surface of the TSV. It should be
noted, the TSV substrate structures in the second embodiment or in
the foregoing examples in FIGS. 3 to 7 are not required to be in
one identical type, TSV substrate structures of various types can
be stacked or assembled according to this present disclosure.
[0027] Here is an exemplary embodiment of the fabrication process
to fabricate the TSV substrate structure in the foregoing
embodiments. Referring to FIGS. 8A to 8M, which schematically
illustrate the evolutional steps of fabricating the TSV substrate
structure of FIG. 1, wherein the copper is used to be the conductor
material as an example. At first, a substrate 110 having a TSV
filled with copper is provided with an insulator layer 114 of oxide
formed on both the substrate surfaces. The back or bottom surface
of the substrate 110 is then planarized or polished until the
exposure of the copper, as shown in FIG. 8A. Next, a barrier layer
401 and a seed layer 402 are electroplated on the top surface of
the substrate 110, as shown in FIG. 8B, where the barrier layer 401
and seed layer 402 are conductor themselves. To form the
extensional part of the conductor unit 120, the photolithography is
used to pattern a photoresist layer 403 on the seed layer 402, as
shown in FIG. 8C. A copper film is electroplated on the seed layer
402 as shown in FIG. 8D, where the copper film can not be disposed
on the photoresist 403 by electroplating. Next, the photoresist
layer 403 is removed, and the substrate 110 is planarized or
polished by the CMP (chemical mechanical planarization) method
until the insulator layer 114 of oxide, as shown in FIG. 8E. A
carrier 405 is then adhered onto the top surface of the substrate
110 with an adhesive layer 406 formed between the carrier 405 and
the substrate 110, as shown in FIG. 8F. Then another oxide layer is
formed on the back surface of the substrate 110, as shown in FIG.
8G. Next, an appropriate pattern of photoresist layer 407 is
selectively formed on the back surface of the substrate 110 by the
photolithography to etch the oxide layer 114, as shown in FIG. 8H.
After that, the photoresist 407 is removed, and the copper layer is
then electroplated on the back surface of the substrate 110, as
shown in FIG. 81. Then a barrier layer 408 and a seed layer 409 are
electroplated on the back surface of the substrate 110, as shown in
FIG. 8J. Next, the photolithography is used to pattern a
photoresist layer 410 on the back surface of the substrate 110, and
copper is then electroplated, as shown in FIG. 8K. The photoresist
410 is then removed, and the exposed barrier layer 408 and seed
layer 409 are then removed, too, as shown in FIG. 8L. Finally, the
carrier 405 is removed, as shown in FIG. 8M, to complete the TSV
substrate structure 100 as in FIG. 1. Also, the foregoing
fabrication process may be used to fabricate other types of the TSV
substrate structures according to the embodiments of this present
disclosure, and is not limited to this exemplary TSV substrate
structure of the recess.sub.top-protrusion.sub.bottom type.
[0028] With respect to the above description then, it is to be
realized that the optimum dimensional relationships for the parts
of the disclosure, to include variations in size, materials, shape,
form, function and manner of operation, assembly and use, are
deemed readily apparent and obvious to one skilled in the art, and
all equivalent relationships to those illustrated in the drawings
and described in the specification are intended to be encompassed
by the present disclosure.
* * * * *