U.S. patent application number 13/344581 was filed with the patent office on 2012-04-26 for method and apparatus for performing an operation with a plurality of sub-operations in a configurable ic.
Invention is credited to Andrew Caldwell, Jason Redgrave, Steven Teig.
Application Number | 20120098568 13/344581 |
Document ID | / |
Family ID | 40635976 |
Filed Date | 2012-04-26 |
United States Patent
Application |
20120098568 |
Kind Code |
A1 |
Redgrave; Jason ; et
al. |
April 26, 2012 |
METHOD AND APPARATUS FOR PERFORMING AN OPERATION WITH A PLURALITY
OF SUB-OPERATIONS IN A CONFIGURABLE IC
Abstract
Some embodiments provide a method of performing a mathematical
operation on a set of operands. The mathematical operation includes
several sub-operations. The method examines several bits of at
least one operand at a time and depending on the value of these
bits, reconfigures a single logic circuit to perform one of the
sub-operations to generate a partial result of the mathematical
operation. In some embodiments, the logic circuit is reconfigured
by receiving a first set of configuration data that cause the logic
circuit to reconfigure to perform a first sub-operation operation
and a second set of configuration data that cause the logic circuit
to reconfigure to perform a second sub-operation. In some
embodiments, the logic circuit receives different inputs based on
the value of the bits being examined. In some embodiments, the
mathematical operation is multiplication and the sub-operations are
addition and subtraction.
Inventors: |
Redgrave; Jason; (Mountain
View, CA) ; Caldwell; Andrew; (Santa Clara, CA)
; Teig; Steven; (Menlo Park, CA) |
Family ID: |
40635976 |
Appl. No.: |
13/344581 |
Filed: |
January 5, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11754262 |
May 25, 2007 |
8112468 |
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13344581 |
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61066135 |
Mar 22, 2007 |
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Current U.S.
Class: |
326/38 |
Current CPC
Class: |
G06F 30/3323 20200101;
H03K 19/1733 20130101 |
Class at
Publication: |
326/38 |
International
Class: |
H03K 19/173 20060101
H03K019/173 |
Claims
1-15. (canceled)
16. An integrated circuit ("IC") comprising: a reconfigurable logic
circuit that receives a plurality of inputs; a signal generator for
generating a selection signal based on a set of user signals; and a
selection circuit for supplying one of a plurality of configuration
data sets to the reconfigurable logic circuit based on the
selection signal, wherein the reconfigurable logic circuit performs
different operations on the plurality of inputs based on supplied
configuration data sets.
17. The IC of claim 16, wherein a user signal is a signal that is
determined at least partially based on a set of inputs to the
IC.
18. The IC of claim 17, wherein the set of inputs to the IC is not
stored in configuration storages within the IC.
19. The IC of claim 16, wherein a user signal is a signal that is
determined based on a current state of the IC, wherein the current
state is determined based on configuration data received by the IC,
inputs to the IC, and a prior state of the IC.
20. The IC of claim 16, wherein the plurality of inputs comprise
first and second inputs, wherein the plurality of configuration
data sets comprise a first configuration data set for configuring
the reconfigurable logic circuit to perform an XOR operation
between the first and second inputs, a second configuration data
set for configuring the reconfigurable logic circuit to perform an
AND operation between the second input and complement of the first
input, a third configuration data set for configuring the
reconfigurable logic circuit to perform an OR operation between the
first input and complement of the second input, and a fourth
configuration data set for configuring the reconfigurable logic
circuit to perform an AND operation between the first and second
input.
21. The IC of claim 20, wherein the selection circuit supplies one
of the first, second, third, and fourth configuration data sets to
the reconfigurable logic circuit based on the selection signal.
22. The IC of claim 20, wherein, based on the configuration data
set supplied to the reconfigurable logic circuit, the
reconfigurable logic circuit performs one of the XOR operation
between the first and second inputs, the AND operation between the
second input and complement of the first input, the OR operation
between the first input and complement of the second input, and the
AND operation between the first and second input to perform an
encryption operation.
23. The IC of claim 22, wherein the encryption operation is MD5
encryption operation.
24. The IC of claim 16, wherein the user signal is
non-repetitive.
25. A method for operating a reconfigurable circuit of an
integrated circuit ("IC"), the method comprising: generating a
user-design signal within the IC; when the user-design signal has a
first value, performing a first set of operations by the
reconfigurable circuit based on a first set of configuration data
sets; and when the user-design signal has a second value,
performing a second set of operations by the reconfigurable circuit
based on a second set of configuration data sets, wherein the first
and second set of configuration data sets are different sub-sets of
a plurality of configuration data sets stored in a set of
configuration storage elements within the IC for the reconfigurable
circuit.
26. The method of claim 25, wherein the user-design signal is a
signal that is determined at least partially based on a set of
inputs to the IC.
27. The method of claim 26, wherein the set of inputs to the IC is
not stored in the set of configuration storage elements.
28. The method of claim 25, wherein a user-design signal is a
signal that is determined based on a current state of the IC,
wherein the current state is determined based on configuration data
received by the IC, inputs to the IC, and a prior state of the
IC.
29. The method of claim 25 further comprising performing an
operation before performing one of the first and second set of
operations.
30. The method of claim 25, wherein each configuration data set
defines a set of operations that the reconfigurable circuit
performs.
31. The method of claim 25, wherein the user-design signal is
non-repetitive.
32. The method of claim 25 further comprising supplying one of the
first and second set of configuration data sets to the
reconfigurable circuit by a selection circuit based on the
user-design signal.
33. The method of claim 32 further comprising generating a
selection signal by a signal generator for the selection circuit
based on the user-design signal to conditionally supply
configuration data sets to the reconfigurable circuit.
34. The method of claim 33 further comprising supplying a plurality
of period clock signals from a global clock generator to the signal
generator.
35. The method of claim 33, wherein the signal generator generates
sub-cycle signals to drive the reconfigurable circuit.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This Application is related to concurrently filed and
commonly owned U.S. Applications entitled "Configurable ICs that
Conditionally Transition Through Configuration Data Sets", with the
attorney docket number TBUL.P0098; and "Method and Apparatus for
Function Decomposition", with the attorney docket number,
TBUL.P0099.
FIELD OF THE INVENTION
[0002] The present invention is directed towards reconfigurable ICs
and more specifically towards a reconfigurable IC that
conditionally performs operations.
BACKGROUND OF THE INVENTION
[0003] An IC is a device that includes numerous electronic
components (e.g., transistors, resistors, diodes, etc.) that are
embedded typically on the same substrate, such as a single piece of
semiconductor wafer. These components are connected with one or
more layers of wiring to form multiple circuits, such as Boolean
gates, memory cells, arithmetic units, controllers, decoders, etc.
An IC is often packaged as a single IC chip in one IC package,
although some IC chip packages can include multiple pieces of
substrate or wafer.
[0004] The use of configurable integrated circuits ("ICs") has
dramatically increased in recent years. One example of a
configurable IC is a field programmable gate array ("FPGA"). An
FPGA is a field programmable IC that often has logic circuits,
interconnect circuits, and input/output (I/O) circuits. The logic
circuits (also called logic blocks) are typically arranged as an
internal array of circuits. These logic circuits are typically
connected together through numerous interconnect circuits (also
called interconnects). The logic and interconnect circuits are
often surrounded by the I/O circuits. Like some other configurable
ICs, the logic circuits and interconnect circuits of an FPGA are
configurable.
[0005] FPGAs have become popular as their configurable logic and
interconnect circuits allow the FPGAs to be adaptively configured
by system manufacturers for their particular applications. Also, in
recent years, several configurable ICs have been suggested that are
capable of reconfiguration at runtime. However, there has not been
much innovation regarding ICs that can configure one or more times
during one clock cycle. Consequently, most reconfigurable ICs take
several cycles (e.g., tens, hundreds, or thousands of cycles) to
reconfigure.
[0006] Recently, there have been configurable ICs that can
configure at least once during each clock cycle. Ideally, the
configurable IC can configure multiple times during sub-cycles
within one clock cycle. See, e.g., the U.S. patent application Ser.
No. 10/883,276 entitled "Configurable Circuits, IC's, and Systems",
filed on Jun. 3, 2004. Such configurability would have many
advantages, such as enabling an IC to perform numerous functions
within any given clock cycle. Such a reconfigurable IC may contain
reconfigurable logic circuits that can perform different functions
in different sub-cycles. There are also many applications today
that require different functions to be performed on the same set of
inputs based on a certain condition that is only determined during
runtime. There is, therefore, a need in the art to make a
reconfigurable IC that can conditionally perform different
functions on the same set of input based on a user-design
signal.
SUMMARY OF THE INVENTION
[0007] Some embodiments provide a reconfigurable IC with at least
one reconfigurable circuit that conditionally transitions through
configuration data sets. In some embodiments, the reconfigurable
circuit transitions through configuration data sets based on a
user-design signal. In some embodiments, at least one
reconfigurable circuit conditionally performs different operations
on the same set of inputs.
[0008] Some embodiments provide a method of operating a
configurable circuit of an integrated circuit (IC). The method
performs a first operation by the configurable circuit based on a
first configuration data set. The method generates a user-design
signal within the IC. When the user-design signal has a value from
a set of values, the method performs a second operation by the
configurable circuit based on a second configuration data set,
after the first operation. When the user-design signal does not
have a value from said set of values, the method performs a third
operation by the configurable circuit based on a third
configuration data set, after the first operation. In some
embodiments, the first, second, and third configuration data sets
are supplied to the configurable circuit by a selection circuit
that receives a selection signal based on the user-design signal.
In some embodiments, the selection signal is generated by a signal
generator that receives the user-design signal and generates the
selection signal based on the user-design signal. In some
embodiments, the user-design signal is a non-repetitive, non-clock
signal.
[0009] Some embodiments provide a reconfigurable integrated circuit
(IC) that includes a set of reconfigurable circuits and sets of
configuration storage elements. Each set of configuration storage
elements is associated with one reconfigurable circuit. Each set of
configuration storage elements stores several configuration data
sets. Each configuration data set defines a set of operations that
a reconfigurable circuit performs. At least one reconfigurable
circuit receives a first sub-set of its configuration data when a
user-design signal has a first value and receives a second sub-set
of its configuration data when the user-design signal has a second
value. In some embodiments, the reconfigurable IC also includes a
set of selection circuits. Each selection circuit can supply
several configuration data sets from the configuration storage
elements to each reconfigurable circuit. At least one selection
circuit conditionally supplies configuration data sets to the at
least one reconfigurable circuit based on the user-design
signal.
[0010] Some embodiments provide a method of performing a
mathematical operation on a set of operands. The mathematical
operation includes several sub-operations. The method examines
several bits of at least one operand at a time and depending on the
value of these bits, reconfigures a single logic circuit to perform
one of the sub-operations to generate a partial result of the
mathematical operation. In some embodiments, the logic circuit is
reconfigured by receiving a first set of configuration data that
cause the logic circuit to reconfigure to perform a first
sub-operation operation and a second set of configuration data that
cause the logic circuit to reconfigure to perform a second
sub-operation. In some embodiments, the logic circuit receives
different inputs based on the value of the bits being examined. In
some embodiments, the mathematical operation is multiplication and
the sub-operations are addition and subtraction.
[0011] Some embodiments provide a reconfigurable integrated circuit
("IC") that can perform multiplication. The IC includes a first
reconfigurable logic circuit and a signal generator that can
generate a selection signal based on a value of a particular number
of bits of a multiplier. The IC also includes a first selection
circuit that ca supply several configuration data sets for the
first reconfigurable circuit based on the selection signal. The
reconfigurable logic circuit is reconfigured to perform either an
addition operation or a subtraction operation to generate a partial
result of the multiplication. In some embodiments, the IC also
includes a second reconfigurable circuit that can supply several
inputs to the first configurable circuits and a second selection
circuit that can supply several configuration data sets for the
second reconfigurable circuit based on the selection signal. Based
on the selection signal, the second reconfigurable circuit supplies
either a value of a multiplicand, twice the value of the
multiplicand, or a value of 0 as input to the first reconfigurable
circuit.
[0012] Some embodiments provide a method of performing circuit
synthesis that receives a design that has a function with several
inputs. The method identifies a set of early arriving inputs of the
function and performs Shannon decomposition on the function based
on one of the early arriving inputs. In some embodiments, the
method estimates the number of circuits a signal has to travel
through to reach each input of the function and selects a set of
inputs with signals that travel through fewer numbers of circuits
compared to signals of inputs that are not selected. In some
embodiments in which the design has more than a particular number
of inputs, the method recursively identifies early arriving signals
and performs Shannon decomposition on the resulting functions until
Shannon decomposition results in a set of functions all of which
with fewer than a particular number of inputs.
[0013] Some embodiments provide a computer readable medium that
stores a computer program that can perform circuit synthesis. The
computer program is executable by at least one processor. The
computer program includes sets of instructions for receiving a
design comprising a function with a plurality of inputs, for
identifying a set of early arriving inputs of the function, and for
performing a function decomposition on the function based on one of
the early arriving inputs.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The novel features of the invention are set forth in the
appended claims. However, for purpose of explanation, several
embodiments of the invention are set forth in the following
figures.
[0015] FIG. 1 illustrates a configurable IC of some embodiments in
which each four tiles share one carry logic circuit.
[0016] FIG. 2 illustrates several configuration data sets received
by a reconfigurable circuit in a loop.
[0017] FIG. 3 illustrates an example of a reconfigurable circuit
that conditionally transitions through configuration data sets.
[0018] FIG. 4 another example of a reconfigurable circuit that
conditionally transitions through configuration data sets.
[0019] FIG. 5 another example of a reconfigurable circuit that
conditionally transitions through configuration data sets.
[0020] FIG. 6 conceptually illustrates a time multiplexer in some
embodiments.
[0021] FIG. 7 illustrates a prior art circuit that conditionally
performs either an add operation or a subtract operation.
[0022] FIG. 8A conceptually illustrates a circuit that
conditionally performs either an add operation or a subtract
operation in some embodiments.
[0023] FIG. 8B conceptually illustrates a multi-tier multiplexer of
some embodiments that is utilized to supply configuration data to a
configurable circuit.
[0024] FIG. 9 summarizes the actions that are taken to perform
multiplication based on the value of the current three bits of the
multiplier using a modified Booth algorithm.
[0025] FIG. 10 conceptually illustrates a traditional
implementation of a modified Booth multiplier that multiplies a
multiplicand A, by a multiplier B.
[0026] FIG. 11 conceptually illustrates a modified Booth multiplier
implemented using time multiplexer in some embodiments.
[0027] FIG. 12 is a prior art illustration of the operations that
are required for performing MD5 encryption.
[0028] FIG. 13 conceptually illustrates an implementation of MD5
encryption in some embodiments utilizing time multiplexer.
[0029] FIG. 14 illustrates a circuit that produces an output in
some embodiments.
[0030] FIG. 15 illustrates a circuit that implements an equivalent
functionality as the circuit of FIG. 14 by using resource
sharing.
[0031] FIG. 16 illustrates a circuit that produces an output in
some embodiments.
[0032] FIG. 17 illustrates a circuit that implements an equivalent
functionality as the circuit in FIG. 16 by using time
multiplexer.
[0033] FIG. 18 illustrates Shannon decomposition used to break a
function into two functions with fewer inputs.
[0034] FIG. 19 illustrates the use of time multiplexer in some
embodiments to implement a 4-input function by utilizing a 3-input
LUT.
[0035] FIG. 20 illustrates a process of some embodiments that uses
Shannon decomposition to decompose a function that has more than a
particular number of inputs.
[0036] FIG. 21 conceptually illustrates two input signals of a
logic circuit that go through several other logic circuits prior to
arrival.
[0037] FIG. 22 conceptually illustrates the arrival time of a set
of inputs that are received by a circuit.
[0038] FIG. 23 illustrates a process of some embodiments that uses
Shannon decomposition to decompose a 4-input function and implement
the resulting two functions using time multiplexer.
[0039] FIG. 24 conceptually illustrates a tile of some
embodiments.
[0040] FIG. 25 conceptually illustrates a tile of some
embodiments.
[0041] FIG. 26 illustrates a space-time context generator of some
embodiments.
[0042] FIG. 27 illustrates the timing between the Clk signal and
the two sets of four one-hot signals.
[0043] FIG. 28 illustrates a space-time context generator of some
embodiments that uses a user-design signal to generate the next
space-time context.
[0044] FIG. 29 illustrates the detailed tile arrangement of some
embodiments.
[0045] FIG. 30 illustrates a portion of a configurable IC of some
embodiments of the invention.
[0046] FIG. 31 illustrates a more detailed example of data between
a configurable node and a configurable circuit arrangement that
includes configuration data that configure the nodes to perform
particular operations.
[0047] FIG. 32 illustrates a system on chip ("SoC") implementation
of a configurable IC.
[0048] FIG. 33 illustrates an embodiment that employs a system in
package ("SiP") implementation for a configurable IC.
[0049] FIG. 34 conceptually illustrates a more detailed example of
an electronics system that has an IC, which implements inventions
of some embodiments.
DETAILED DESCRIPTION OF THE INVENTION
[0050] In the following description, numerous details are set forth
for purpose of explanation. However, one of ordinary skill in the
art will realize that the invention may be practiced without the
use of these specific details. For instance, not all embodiments of
the invention need to be practiced with the specific number of bits
and/or specific devices (e.g., multiplexers) referred to below. In
other instances, well-known structures and devices are shown in
block diagram form in order not to obscure the description of the
invention with unnecessary detail.
I. Overview
[0051] Some embodiments provide a reconfigurable IC with at least
one reconfigurable circuit that conditionally transitions through
configuration data sets. In some embodiments, the reconfigurable
circuit transitions through configuration data sets based on a
user-design signal. In some embodiments, at least one
reconfigurable circuit conditionally performs different operations
on the same set of inputs.
[0052] Some embodiments provide a method of operating a
configurable circuit of an integrated circuit (IC). The method
performs a first operation by the configurable circuit based on a
first configuration data set. The method generates a user-design
signal within the IC. When the user-design signal has a value from
a set of values, the method performs a second operation by the
configurable circuit based on a second configuration data set,
after the first operation. When the user-design signal does not
have a value from said set of values, the method performs a third
operation by the configurable circuit based on a third
configuration data set, after the first operation. In some
embodiments, the first, second, and third configuration data sets
are supplied to the configurable circuit by a selection circuit
that receives a selection signal based on the user-design signal.
In some embodiments, the selection signal is generated by a signal
generator that receives the user-design signal and generates the
selection signal based on the user-design signal. In some
embodiments, the user-design signal is a non-repetitive, non-clock
signal.
[0053] Some embodiments provide a reconfigurable integrated circuit
(IC) that includes a set of reconfigurable circuits and sets of
configuration storage elements. Each set of configuration storage
elements is associated with one reconfigurable circuit. Each set of
configuration storage elements stores several configuration data
sets. Each configuration data set defines a set of operations that
a reconfigurable circuit performs. At least one reconfigurable
circuit receives a first sub-set of its configuration data when a
user-design signal has a first value and receives a second sub-set
of its configuration data when the user-design signal has a second
value. In some embodiments, the reconfigurable IC also includes a
set of selection circuits. Each selection circuit can supply
several configuration data sets from the configuration storage
elements to each reconfigurable circuit. At least one selection
circuit conditionally supplies configuration data sets to the at
least one reconfigurable circuit based on the user-design
signal.
[0054] Some embodiments provide a method of performing a
mathematical operation on a set of operands. The mathematical
operation includes several sub-operations. The method examines
several bits of at least one operand at a time and depending on the
value of these bits, reconfigures a single logic circuit to perform
one of the sub-operations to generate a partial result of the
mathematical operation. In some embodiments, the logic circuit is
reconfigured by receiving a first set of configuration data that
cause the logic circuit to reconfigure to perform a first
sub-operation operation and a second set of configuration data that
cause the logic circuit to reconfigure to perform a second
sub-operation. In some embodiments, the logic circuit receives
different inputs based on the value of the bits being examined. In
some embodiments, the mathematical operation is multiplication and
the sub-operations are addition and subtraction.
[0055] Some embodiments provide a reconfigurable integrated circuit
("IC") that can perform multiplication. The IC includes a first
reconfigurable logic circuit and a signal generator that can
generate a selection signal based on a value of a particular number
of bits of a multiplier. The IC also includes a first selection
circuit that ca supply several configuration data sets for the
first reconfigurable circuit based on the selection signal. The
reconfigurable logic circuit is reconfigured to perform either an
addition operation or a subtraction operation to generate a partial
result of the multiplication. In some embodiments, the IC also
includes a second reconfigurable circuit that can supply several
inputs to the first configurable circuits and a second selection
circuit that can supply several configuration data sets for the
second reconfigurable circuit based on the selection signal. Based
on the selection signal, the second reconfigurable circuit supplies
either a value of a multiplicand, twice the value of the
multiplicand, or a value of 0 as input to the first reconfigurable
circuit.
[0056] Some embodiments provide a method of performing circuit
synthesis that receives a design that has a function with several
inputs. The method identifies a set of early arriving inputs of the
function and performs Shannon decomposition on the function based
on one of the early arriving inputs. In some embodiments, the
method estimates the number of circuits a signal has to travel
through to reach each input of the function and selects a set of
inputs with signals that travel through fewer numbers of circuits
compared to signals of inputs that are not selected. In some
embodiments in which the design has more than a particular number
of inputs, the method recursively identifies early arriving signals
and performs Shannon decomposition on the resulting functions until
Shannon decomposition results in a set of functions all of which
with fewer than a particular number of inputs.
[0057] Some embodiments provide a computer readable medium that
stores a computer program that can perform circuit synthesis. The
computer program is executable by at least one processor. The
computer program includes sets of instructions for receiving a
design comprising a function with a plurality of inputs, for
identifying a set of early arriving inputs of the function, and for
performing a function decomposition on the function based on one of
the early arriving inputs.
[0058] Several more detailed embodiments of the invention are
described in sections below. Before describing these embodiments
further, an overview of the configurable IC architecture that is
used by some of these embodiments is first described below in
Section II. This discussion is followed by the discussion in
Section III of reconfigurable circuits that loop through less than
the maximum number of available configuration data sets. Next,
Section IV describes time multiplexers and discusses how portions
of the IC in some embodiments go through sub-cycle configuration
conditionally. Next, Section V describes the use of time
multiplexers and function decomposition in automatic circuit
design. Next, Section VI describes the space-time context generator
of some embodiments that generates sub-cycle signals to drive a
reconfigurable circuit to go through the states in a loop. Last,
Section VII describes a configurable IC and an electronics system
that has an IC which implements some of the embodiments of the
invention.
II. Architecture
[0059] Some embodiments are implemented in a reconfigurable IC. A
reconfigurable IC is a form of a configurable IC. A configurable
circuit is a circuit that can "configurably" perform a set of
operations. Specifically, a configurable circuit receives
"configuration data" that specifies the operation that the
configurable circuit has to perform from the set of operations that
it can perform. In some embodiments, the configuration data is
generated outside of the configurable IC. In these embodiments, a
set of software tools typically converts a high-level IC design
description (e.g., a circuit representation or a hardware
description language design) into a set of configuration data that
can configure the configurable IC (or more accurately, the
configurable circuits of the configurable IC) to implement the IC
design.
[0060] A reconfigurable IC is a configurable IC that has at least
one circuit that reconfigures during runtime. In other words, a
reconfigurable IC is an IC that has reconfigurable logic circuits
and/or reconfigurable interconnect circuits, where the
reconfigurable logic and/or interconnect circuits are configurable
logic and/or interconnect circuits that can "reconfigure" more than
once at runtime. A configurable logic or interconnect circuit
reconfigures when it receives a different set of configuration
data. Some embodiments of the invention are implemented in
reconfigurable ICs that are sub-cycle reconfigurable (i.e., can
reconfigure circuits on a sub-cycle basis). In some embodiments, a
reconfigurable IC has a large number of logic and interconnect
circuits (e.g., hundreds, thousands, etc. of such circuits). Some
or all of these circuits can be reconfigurable.
[0061] In some embodiments, runtime reconfigurability means
reconfiguring without resetting the reconfigurable IC. Resetting a
reconfigurable IC entails in some cases resetting the values stored
in the state elements of the IC, where state elements are elements
like latches, registers, and non-configuration memories (e.g.,
memories that store the user signals as opposed to the memories
that store the configuration data of the configurable circuits). In
some embodiments, runtime reconfigurability means reconfiguring
after the reconfigurable IC has started processing of the user
data. Also, in some embodiments, runtime reconfigurability means
reconfiguring after the reconfigurable IC has powered up. These
definitions of runtime reconfigurability are not mutually
exclusive. Examples of configurable and reconfigurable ICs are
described in detail in U.S. patent application Ser. No. 11/081,859,
"Configurable IC with Interconnect Circuits that also Perform
Storage Operations", filed on Mar. 15, 2005.
[0062] FIG. 1 conceptually illustrates a portion 100 of the
configurable circuit architecture of some embodiments of the
invention. As shown in FIG. 1, this architecture is formed by
numerous conceptual configurable tiles 105 that are arranged in an
array with multiple rows and columns. In FIG. 1, each configurable
tile is a conceptual grouping of a configurable three-input logic
circuit 110, three configurable input-select interconnect circuits
115, and several configurable routing interconnect circuits 120.
Different embodiments have different number of configurable routing
interconnect circuits 120. For instance, some embodiments may have
eight configurable routing interconnect circuits while others may
have more or less such circuits. For each configurable circuit, the
configurable IC includes a set of storage elements (not shown) for
storing a set of configuration data.
[0063] In some embodiments, the logic circuits are look-up tables
(LUTs) while the interconnect circuits are multiplexers. Also, in
some embodiments, the LUTs and the multiplexers are sub-cycle
reconfigurable circuits, as described in U.S. patent application
"Configurable IC with Routing Circuits with Offset Connections",
Ser. No. 11/082,193, filed on Mar. 15, 2005. In some of these
embodiments, the configurable IC stores multiple sets of
configuration data for a sub-cycle reconfigurable circuit, so that
the reconfigurable circuit can use a different set of configuration
data in different sub-cycles. Other configurable tiles can include
other types of circuits, such as memory arrays instead of logic
circuits.
[0064] In FIG. 1, an input-select multiplexer 115, also referred to
as IMUX, is an interconnect circuit associated with the LUT 110
that is in the same tile as the input select multiplexer. One such
input select multiplexer receives input signals for its associated
LUT and passes one of these input signals to its associated
LUT.
[0065] In FIG. 1, a routing multiplexer (also referred to as an
RMUX) 120 is an interconnect circuit that at a macro level connects
other logic and/or interconnect circuits. In other words, unlike an
input select multiplexer that only provides its output to a single
logic circuit (i.e., that only has a fan out of 1) in some
embodiments, a routing multiplexer either provides its output to
several logic and/or interconnect circuits (i.e., has a fan out
greater than 1), or provides its output to other interconnect
circuits.
[0066] In some embodiments, an RMUX is a complementary pass logic
(CPL) implemented 8-to-1 multiplexer. In some of these embodiments,
an RMUX may have a latch built in its output stage. In a CPL
implementation of a circuit, a complementary pair of signals
represents each logic signal. In other words, the circuit receives
true and complement sets of input signals and provides true and
complement sets of output signals. To implement the latch function
of an RMUX, the two (true and complement) outputs of the 8-to-1
multiplexer can be cross coupled with two NMOS transistors that
receive a latch enable signal at their gates. This implementation
of an RMUX is further described in the above mentioned U.S. patent
application Ser. No. 11/081,859.
[0067] In the architecture illustrated in FIG. 1, each tile
includes one three-input LUT, three input select multiplexer and
several routing multiplexers. In addition, every four tiles 125
share a carry logic circuit 130. In the examples used in this
application, the term 4-aligned LUT tile refers to four tiles (each
with one LUT) with a common carry logic circuit.
[0068] In the embodiments described below, one, two, or three of
the IMUXs are hybrid multiplexers, called HMUXs. An HMUX is a
multiplexer that can receive "user-design signals" or configuration
data. A user-design signal within a configurable IC is a signal
that is generated by a circuit (e.g., logic circuit) of the
configurable IC. The word "user" in the term "user-design signal"
connotes that the signal is a signal that the configurable IC
generates for a particular application that a particular user has
configured the IC for. User-design signal is abbreviated to user
signal in some of the discussions below.
[0069] In some embodiments, a user signal is a signal that is
generated within the configurable IC. In some embodiments, a user
signal is a signal that is a function of at least a portion of the
configuration data received by the configurable IC and at least a
portion of the inputs to the configurable IC. In these embodiments,
the user signal can also be dependent on (i.e., can also be a
function of) the state of the configurable IC. The initial state of
a configurable IC is a function of the configuration data received
by the configurable IC and the inputs to the configurable IC.
Subsequent states of the configurable IC are functions of the
configuration data received by the configurable IC, the inputs to
the configurable IC, and the prior states of the configurable
IC.
[0070] When implementing a particular user design, a configurable
IC performs user-design operations that allow the IC to implement
the particular user design in a circuit or device. During such
user-design operations, the configurable IC (1) can receive
user-design input data, which are neither configuration signals nor
clocking signals, and (2) can process these signals to implement
the particular user design in a circuit or device. Accordingly, in
some cases, a configurable IC performs user-design operations when
it receives and processes user-design input data and provides user
design output data. For instance, when the configurable IC performs
user-design operations, its configurable logic circuits in some
cases can receive user-design input data, compute functions based
on the user-design input data, and output their results to other
circuits inside the IC. In other contexts, a configurable IC might
implement a user design that simply directs the IC to generate
output without receiving any user-design input.
[0071] When a configurable IC performs user-design operations, its
circuits typically receive clocking signals that allow them to
process user-design signals. Examples of such clocking signals
include (1) clocking signals applied to input/output buffer
circuits that allow these circuits to receive and output
user-design data, (2) clocking signals applied to the configurable
logic circuits that allow these circuits to compute user-design
functions, and/or (3) clocking signals applied to the IC's
configurable interconnect circuits that allow these circuits to
perform user-design connection operations. In case of a
reconfigurable IC that has reconfigurable circuits that receive
different configuration data sets loaded on the IC, the clock
signals can also include clock signals that allow the
reconfigurable circuit to step through the different configuration
data sets.
[0072] A person of ordinary skill in the art will recognize that
other architectures are possible and the invention can be embodied
in other specific forms without departing from the spirit of the
invention. For instance, some embodiments have different logic
circuits, interconnect circuits, etc.; different number of these
circuits; different arrangement of these circuits; or different
number of inputs and outputs for these circuits.
III. Reconfigurable Circuits That Loop through Less Than the
Maximum Number of Available Configuration Data Sets
[0073] A. Configuration Data Sets and "Looperedness"
[0074] In some embodiments, a reconfigurable circuit receives
configuration data sets sequentially in an order that loops from
the last configuration data set to the first configuration data
set. FIG. 2 illustrates eight configuration data sets received by a
reconfigurable circuit according to such a looping sequence that
can loop through configuration data sets. In this figure, the
arrows illustrate how the configuration data sets follow each
other. Such a sequential reconfiguration scheme is hereinafter
referred to as a "loopered" scheme. For instance, FIG. 2
illustrates an 8-loopered scheme for providing the configuration
data sets to a reconfigurable circuit. The full cycle of the
reconfigurable circuit is, therefore, divided into eight
sub-cycles.
[0075] In FIG. 2, each one of the eight configuration data sets
(0-7) provides a space-time context (or configuration state) for
the reconfigurable circuit. Each space-time context is defined by a
set of bits. The space-time context for a reconfigurable circuit in
a particular clock cycle or sub-cycle is the configuration data
sets that the circuit receives during the cycle. Each set (or word)
of configuration data is termed as context as it defines the
operation (i.e., the logic or interconnect operation) that a
particular reconfigurable circuit (i.e., a logic circuit or an
interconnect circuit) performs for a particular cycle out of the
rest of operations that the circuit can perform. During a cycle,
space-time context for the IC is all the configuration data sets
that all the reconfigurable circuits receive during that cycle.
[0076] In some embodiments, however, a reconfigurable circuit does
not receive all configuration data sets in each loop. This is the
case when, e.g., due to timing constraints, a portion of the user
design does not require all configuration data sets to run. The
unused configuration data sets can be utilized to conditionally
perform different operations. For instance, if there are n
configuration data sets, a reconfigurable circuit may conditionally
cycle through m (where m is smaller than n) configuration states in
each loop based on a certain condition. FIG. 3 illustrates one such
example. Specifically, it illustrates eight configuration data sets
that are available for a particular reconfigurable circuit.
[0077] As shown, after configuration data set 0, the circuit
receives either configuration data set 1 or configuration data set
3. Specifically, as long as a certain condition (such as presence
of a certain signal) is true, then the reconfigurable circuit
receives configuration data sets 0, 1, 2, 5, 6, and 7 in a loop.
Once the condition becomes false, the circuit receives
configuration data sets 0, 3, 2, 5, 6, and 7 in a loop. As shown,
configuration data set 4 is not used for the particular
reconfigurable circuit and the particular user design shown in FIG.
3. A full cycle of the reconfigurable circuit that receives the
configuration data sets shown in FIG. 3 is, therefore, divided into
6 sub-cycles. In some embodiments, a user-design signal determines
the condition upon which the reconfigurable circuit receives a
particular configuration data set.
[0078] Similarly, FIG. 4 illustrates eight configuration data sets
0-7. Based on a certain condition, the reconfigurable circuit
receives either configuration data sets 0, 1, 2, 5, 6, and 7 or
configuration data sets 0, 3, 2, 5, 6, and 7. As shown,
configuration data set 4 is not used for the particular
reconfigurable circuit and the particular user design shown in FIG.
4. A full cycle of the reconfigurable circuit that receives the
configuration data sets shown in FIG. 4 is, therefore, divided into
6 sub-cycles.
[0079] FIG. 5 illustrates another possible way of conditionally
going through eight possible configuration data sets. The
reconfigurable circuit receives either configuration data sets 0,
5, 2, 7 or 4, 1, 6, 3. As shown, after receiving configuration data
set 7, the reconfigurable circuit may receive configuration data
set 4 instead of configuration data set 0. Similarly, after
receiving configuration data set 3, the reconfigurable circuit may
receive configuration data set 0 instead of configuration data set
4.
[0080] In each of the cases illustrated in FIGS. 3-5, the decision
to which configuration data set the circuit receives depends on the
value of a user signal (not shown). For instance, as will be
described below, in FIG. 3 a particular user signal with a value of
0 may cause the reconfigurable circuit to receive configuration
data set 1 after configuration data set 0. The configuration data
set 1 may, for instance, reconfigure the circuit to perform an add
operation. On the other hand, a value of 1 for that user signal may
cause the reconfigurable circuit to receive configuration data set
3 after configuration data set 0 and reconfigure to perform a
subtraction operation.
[0081] B. Time Multiplexers
[0082] Time multiplexer (TMUX) conceptually refers to configurable
circuits conditionally going through their configuration data sets.
To facilitate this, some embodiments use space-time context
generators (ST-context generators) which generate sub-cycle signals
that control the operations of the circuitry that provides
configuration data sets to the configurable circuits. In generating
such sub-cycle signals, ST-context generators (also referred to as
sub-cycle signal generators) of some embodiments receive user
signals which cause them to modify the signals it generates for
different configurable circuits. In other words, these users design
signals cause the configurable circuits to conditionally transition
through their configuration data sets by having the ST-context
generator to modify its output which in turn modify the
configuration data fetching circuitry associated with the
configuration circuits.
[0083] A TMUX provides the ability to make configuration decisions
based on user signals. A TMUX is conceptually illustrated in FIG.
6. The ST-context generator 615 operates as a counter that decodes
the next row of configuration storage 610. As shown, the ST-context
generator receives a set of configuration bits 620 that determine
whether the ST-context generator operators, e.g., in any of the 2,
4, 6, or 8 loopered configurations. As shown in FIG. 6, a user
signal 605 determines the next row of the configuration storage 610
that is decoded. The configuration storage stores a set of
configuration data bits for a configurable circuit. A selection
circuit 625 supplies the configuration data sets to a
reconfigurable circuit (not shown). ST-context generators and their
associated selection circuits are described further below. A TMUX
re-coups the waste of configuration storage when, due to timing
constraints, a user design is not run at the highest looperedness
(i.e., the user design is not using all configuration data sets in
each particular loop).
[0084] There are a number of ways this configuration storage can be
reused. What differentiates the techniques is whether the user
specifies the "decision" to be made by the TMUX, or whether the
synthesis tools determine it directly from a user register transfer
level (RTL) description of the user design. An example of a user
determined decision is two substantial design modules which are
mutually exclusive. Which of the two modules is currently relevant
is determined by the state of the design. The two modules can be
placed on the same region and the TMUX can be used to select
between these two contexts based on the design state. In the case
of tools doing the determination, the tools can do "Shannon
decomposition in time" to determine two mutually exclusive
configuration of a logic circuit based on previously known logic
values.
IV. Going through Sub-Cycle Configuration Conditionally
[0085] When there are more configuration sets than the sub-cycles
needed for a part of the design to operate, the extra configuration
data set(s) can be utilized to conditionally perform different
operations in that particular part of the design. Several examples
are given in the following sub-sections.
[0086] A. Conditional Add or Subtract
[0087] FIG. 7 illustrates a prior art circuit 700 that
conditionally performs either an add operation or a subtract
operation. The two inputs, X and Y, are fed to the adder 705 and
the subtractor 710. The outputs of the adder 705 and the subtractor
710 are connected to the inputs of the 2-to-1 multiplexer 715. A
signal, Z, that is connected to select line of multiplexer 715
determines the results of which of the two operations is output
from the multiplexer.
[0088] FIG. 8A conceptually illustrates a circuit 800 that
conditionally performs an add operation or a subtract operation in
some embodiments. The 8-to-1 multiplexer receives eight sets of
configuration data, F(0) to F(7), at its inputs. Each set of
configuration data, F(0) to F(7) is a multi-bit value. Based on the
value of the multi-bit select signal S, the multiplexer connects
one of its inputs to its output. The signal S is dependent on the
value of a user signal, Z. As shown, the output of the multiplexer
805 is connected to the input of the look-up table (LUT) 810. LUT
810 is a reconfigurable circuit. In each sub-cycle, the
configuration data set 815 that the LUT receives determines the
operation that the LUT performs during that sub-cycle.
[0089] In some embodiments, the 8-to-1 multiplexer is implemented
as a two-tiered multiplexer. FIG. 8B conceptually illustrates such
a two-tiered multiplexer 820. As shown, the first tier has two
4-to-1 multiplexers 825 and 830, and the second tier has one 2-to-1
multiplexer 835. The multiplexers in the first tier receive
configuration data as their inputs. Specifically, multiplexer 825
receives F(0), F(2), F(4), and F(6) while multiplexer 830 receives
F(1), F(3), F(5), and F(7) at their inputs. Two bits (S1 and S2) of
the select signal S control the multiplexers of the first tier and
one bit (S3) controls the multiplexer of the second tier. Depending
on the value of the three bits of the select signal S (which are in
turn dependent on the value of a user signal such as Z shown in
FIG. 8A), one of the configuration bits F(0) to F(7) is selected to
connect to the output of the two-tiered multiplexer 820.
[0090] Some embodiments that use this two-tiered structure, build
the first tier of multiplexers into the sensing circuitry of the
configuration storage. Examples of this structure are described in
the above mentioned U.S. application Ser. No. 11/081,859.
[0091] As shown in FIG. 8A, when the user signal Z is 0, the 3-bit
select signal S of the multiplexer 805 selects configuration data
sets F(0), F(1), F(2), F(5), F(6), and F(7). When the user signal
is 1, the select signal S of the multiplexer selects configuration
data sets F(0), F(3), F (2), F(5), F(6), and F(7). The LUT is
designed to perform an add operation if it receives configuration
data set F(1) and to perform a subtract operation if it receives
configuration data set F(2). The LUT, therefore, conditionally
performs either an add or a subtract operation based on the value
of the user signal, Z.
[0092] Circuit 800 performs a similar operation as circuit 700.
While circuit 700 requires an adder (705), a subtractor (710), and
a multiplexer (715), circuit 800 only needs a LUT and its
associated configuration multiplexer 805. Circuit 800, therefore,
saves on the logic circuitry and routing resources.
[0093] B. Use of TMUX to Perform Complex Operations
[0094] The following example shows how a modified Booth recoding
scheme is implemented using the time-space context generator in
some embodiments to perform multiplication. In a Booth multiplier,
two bits of the multiplier are considered at a time and a partial
product (which is initially set to 0) is updated based on the value
of the current two bits of the multiplier. The Booth algorithm
works on the following equality (A):
2.sup.J+2.sup.J-1+2.sup.J-2+. . . +2.sup.K=2.sup.J+1-2.sup.K
(A)
[0095] The Booth algorithm exploits the equality, (A), to create
faster multipliers by replacing a sequence of n 1s in the
multiplier (that requires n additions), by one addition and one
subtraction. The Booth algorithm doesn't perform well when the
multiplier has a singleton 1 (i.e., a 1 separated by 0s) which
would replace one addition by one addition and one subtraction. The
modified Booth algorithm is an improvement of the Booth
algorithm.
[0096] In a modified Booth algorithm, three bits of the multiplier
are considered at a time. Table 900 in FIG. 9 summarizes the
actions that are taken by the modified Booth multiplier algorithm
to perform multiplication based on the value of the current three
bits of the multiplier.
[0097] The modified Booth multiplier algorithm ignores runs of 0 or
1 in the multiplier. Therefore, as shown in Table 900, when the
three bits of the multiplier are 000 or 111, no action is required.
A singleton 1 (010) requires the multiplicand to be added to the
partial result. A single 1 at the end of a run of 1 (001) and two
is at the end of a run of 1 (011) require adding either the
multiplicand or two times the multiplicand to be added to the
partial result, respectively. A single 1 beginning a run of 1 s
(001) or two 1 s beginning a run of 1 s (110) require subtracting
two times the multiplicand or the multiplicand from the partial
results, respectively. Finally, end of run of is and beginning of
another (101) requires subtracting the multiplicand from the
partial results.
[0098] FIG. 10 conceptually illustrates a traditional
implementation of the modified Booth multiplier that multiplies a
multiplicand A, by a multiplier B. The partial product is initially
set to zero (not shown). The bits of the multiplier are examined
three at a time. The current three bits of the multiplier are
utilized as the three select lines of multiplexer 1010. The values
of the current three bits of the multiplier (B.sub.i, B.sub.i-1,
and B.sub.i-2) determine what value is added to the partial
product. Specifically, Table 900 shows the required action for each
combination of 000 to 111 of the current three bits of the
multiplier.
[0099] FIG. 11 conceptually illustrates a Booth multiplier
implemented using TMUX. ST-context generator 1120 uses the user
signal (which is the current three bits of the multiplier) to
generate space-time context for each sub-cycle. The context
generator 1120 does not make context generation in a traditional
sense, instead it operates as a per sub-cycle multiplier function.
Specifically, instead of cycling through as a counter, it uses the
three current bits of the multiplier to generate the sub-cycle
signal.
[0100] LUT 1105 is a reconfigurable circuit and can reconfigure to
perform either addition or subtraction. As shown, LUT 1105 has an
associated selection circuit 1125 and configuration storage 1130
that receive the sub-cycle signal from the ST-context generator and
supply space-time context to the LUT.
[0101] IMUXs 1110 and 1115 route inputs to the LUT. As shown, IMUX
1110 has an associated selection circuit 1135 and configuration
storage 1140 that receive the sub-cycle signal from the ST-context
generator and supply space-time context to the LUT. IMUX 1110 also
has an associated selection circuit and configuration storage which
are not shown in FIG. 11. Since LUT 1105 is a reconfigurable
circuit, instead of adding or 2A the value of A or 2A is subtracted
from the partial product, respectively. This reduces the inputs of
the IMUX 1110 by two and saves routing resources.
[0102] IMUX 1110 is used to input the next values to add or
subtract. IMUX 1115 is used to input the partial product from the
previous sub-cycle. In each sub-cycle, depending on the values of
the current three bits of the multiplier, ST-context generator 1120
generates an appropriate signal to selection circuit 1125 and
configuration storage 1130 which causes them to supply the
appropriate configuration data to LUT 1105 to configure the LUT as
either an adder or a subtractor. Specifically, LUT 1105 is either
configured to act as an adder (when the current three bits of the
multiplier are 000, 001, 010, 011, and 111) or as a subtractor
(when the bits are 100, 101, or 110).
[0103] Similarly, in each sub-cycle, depending on the values of the
current three bits of the multiplier, ST-context generator 1120
generates an appropriate signal to selection circuit 1135 and
configuration storage 140 which causes them to supply the
appropriate configuration data to IMUX 1110. IMUX 1110 is
configured to input either 0 (when the current three bits of the
multiplier are 000 or 111), A (when the bits are 001 or 010, 101,
or 110), or 2A (when the bits are 011 or 100) to LUT 1110. Some
embodiments require only the two values of A and 2A (and not the
value of 0) to be input to IMUX 1110. In these embodiments, LUT
1105 is configured to leave the partial product unchanged when the
three bits of the multiplier are 000 or 111.
[0104] Although the above description was given using a Booth
multiplier as an example, one of ordinary skill in the art will
realize that the same approach can be applied to implement other
mathematical operations that conditionally perform several
sub-operations based on the value of a portion of at least one of
the operands. Specifically, the method described in this section
can be applied to examine a portion of one or more of the operands
and to use a single logic circuit to conditionally perform one of
the several sub-operations to generate a partial result of the
mathematical operation.
[0105] C. Use of TMUX to Share Routing Resources and Save on Data
Paths
[0106] The previous examples for performing mathematical operations
were examples of utilizing TMUX to perform conditional operations.
More complex operations can be performed using TMUX whenever a
circuit design includes multiplexers that select between a set of
functions, each of which operate on the same set of input. In many
cases, using TMUX will result in sharing routing resources and
reduction of data paths. For instance, the MD5 encryption
operations can be greatly simplified by using TMUX. MD5 encryption
operations are a set of AND, OR, and exclusive OR (XOR) operations
that are performed on two inputs.
[0107] FIG. 12 conceptually illustrates operations that are
required for performing MD5 encryption on a set of two 32-bit
values, A and B. The multiplexer 1205 selects one of the outputs of
function generators 1210-1225. Function generators 1210-1225
perform A.sym.B, .cndot.B, A+ B, and A.cndot.B operations
respectively.
[0108] As is shown in FIG. 12, implementing a circuit 1200 to
perform MD5 encryption requires many routing resources.
Specifically, the 32-bit inputs, A and B, have to be routed to
function generators 1210-1225 and the 32-bit outputs of these
function generators have to be routed to the inputs of multiplexer
1205.
[0109] FIG. 13 conceptually illustrates a circuit 1300 that
performs MD5 encryptions in some embodiments. The 8-to-1
multiplexer 1305 receives eight sets of configuration data, F(0) to
F(7), at its inputs. Based on the value of the select signal S, the
multiplexer connects one of its inputs to its output. The signal S
is dependent on the values of user signals, Z.sub.1 and Z.sub.2. As
shown, the output of multiplexer 1305 is connected to the input of
the look-up table (LUT) 1310. LUT 1310 is a reconfigurable circuit.
In each sub-cycle, the configuration data set 1315 that the LUT
receives determines the operation that the LUT performs during that
sub-cycle.
[0110] As shown, when the user signals Z.sub.1 and Z.sub.2 are 00,
the multiplexer selects configuration data sets F(1) and F(2). When
the user signals are 01, the multiplexer selects configuration data
sets F(1) and F(4). When the user signals are 10, the multiplexer
selects configuration data sets F(1) and F(6). Finally, when the
user signals are 11, the multiplexer selects configuration data
sets F(1) and F(8).
[0111] The LUT is designed to perform an XOR operation when it
receives configuration data set F(2), to perform AND operation
between B and the complement of A when it receives configuration
data set F(4), to perform OR operation between A and the complement
of B when it receives configuration data sets F(6), and to perform
AND operation when it receives configuration data set F(8). The
LUT, therefore, conditionally performs the operations that are
required for MD5 encryption based on the value of the user signals,
Z.sub.1 and Z.sub.2.
[0112] As shown, using circuit 1300 requires that the two 32-bit
inputs, A and B to be routed to the inputs of only one logic
circuit, i.e., LUT 1310. Therefore, comparing with the prior art
arrangement shown in FIG. 12, circuit 1300 saves a large amount of
routing resources. In addition, circuit 1300 requires only one
function generator (e.g., LUT 1310) as oppose to the four function
generators 1210-1225 required in FIG. 12. Therefore, comparing with
the prior art, circuit 1300 also saves on the computing
resources.
[0113] D. Difference between using TMUX and Doing Resource
Sharing
[0114] Resource sharing can be utilized when the same (or similar)
operation is performed by the same logic circuit on different sets
of input for generating mutually exclusive output results (i.e.,
results that are not needed at the same time). Note that at least
one input should be different in each set to make resource sharing
meaningful. FIG. 14 illustrates a circuit 1400 that conditionally
performs an add operation on either of two sets of inputs (A and B
or C and D) and produces an output 1420. The inputs to multiplexer
1415 are the outputs of adder 1405 (i.e., A+B) and the output of
adder 1410 (C+D). Depending on the value of the select signal, S,
multiplexer 1415 selects the output of either adder 1405 or 1410 to
connect to the output 1420. Therefore, circuit 1400 performs the
same operation (i.e., addition) on different sets of inputs (either
A and B or C and D) to produce mutually exclusive results
(multiplexer 1415 only allows the output of one of the adders 1405
and 1410 to appear at the output 1420).
[0115] The output of circuit 1400 can be generated using resource
sharing. FIG. 15 illustrates a circuit 1500 that has an adder 1515
and two multiplexers 1505 and 1510. The two multiplexers have the
same select signal, S. Depending on the value of S, either 1505
selects A and 1510 selects B or 1505 selects C and 1510 selects D.
The input to the adder are, therefore, either A and B or C and D.
The output 1520 of the circuit 1500 is either A+B or C+D. Circuit
1500 implements the same functionality as circuit 1400 by sharing
the adder resource to generate two mutually exclusive results. Note
that if the logic circuit (in this case adder 1515) can perform
other similar operations, such as subtraction, resource sharing can
be utilized to perform similar operations. There is, however, the
limitation that the operations have to be performed by the same
logic unit that is being shared and the outputs should not be
needed at the same time.
[0116] Utilizing TMUX is a more generalized way of utilizing the
resources. The only requirement to use TMUX is to have functions
that operate conditionally to produce mutually exclusive outputs.
In other words, using TMUX does not require the operations to be
performed by the same logic unit nor the input sets need to be
necessarily different.
[0117] As an example, FIG. 16 illustrates a circuit 1600 that
produces an output 1620. The inputs to multiplexer 1615 are the
outputs of the logic circuit 1605 (i.e., A XOR B) and the output of
the logic circuit 1610 (C+D). Depending on the value of the select
signal, S, multiplexer 1615 selects the output of either the logic
circuit 1605 or 1610 to connect to the output 1620. Since the two
logic circuits 1605 and 1610 perform different operations (i.e.,
XOR and addition), resource sharing technique shown in FIG. 15
cannot be used to implement an equivalent for circuit 1600. An
equivalent of circuit 1600, however, can be implemented using
TMUX.
[0118] FIG. 17 illustrates a circuit 1700 that conditionally
performs either an add operation or an XOR operation and produces
an output 1720. The 4-to-1 multiplexer 1705 receives four sets of
configuration data, F(0) to F(3), at its inputs. Based on the value
of the select signal S, the multiplexer connects one of its inputs
to its output. The signal S is dependent on the value of a user
signal, Z. As shown, the output of the multiplexer 1705 is
connected to the input of the look-up table (LUT) 1710. LUT 1710 is
a reconfigurable circuit. In each sub-cycle, the configuration data
set 1715 that the LUT receives determines the operation that the
LUT performs during that sub-cycle.
[0119] As shown, when the user signal Z is 0, the select signal S
of the multiplexer selects configuration data sets F(0) and F(1).
When the user signal is 1, the multiplexer selects configuration
data sets F(0) and F(3). The LUT is designed to perform an XOR
operation if it receives configuration data set F(1) and to perform
an addition operation if it receives configuration data set F(3).
The LUT, therefore, conditionally performs either an XOR or an
addition operation based on the value of the user signal Z received
at the select line S.
[0120] Circuit 1700 performs a similar operation as the circuit
1600. While the circuit 1600 requires two logic circuits 1605 and
1610 and a multiplexer 1615, circuit 1700 only needs a LUT and its
associated configuration multiplexer 1705. Circuit 1700, therefore,
saves on the logic circuitry and routing resources in a situation
where two different operations have to be performed.
V. Use of TMUX and Function Decomposition in Automatic Circuit
Design
[0121] TMUXs can be used to implement functions with large fan-ins
using circuit components with fewer inputs. More specifically, some
embodiments use a function decomposition (e.g., Shannon
decomposition) to decompose functions. A Shannon decomposition
decomposes a function F(a,b, . . . ,n) into two functions F.sub.0
and F.sub.1, each with one less input. The following equation (B)
shows an example of performing Shannon decomposition on a multiple
input function, F.
F(a, b, . . . ,n)=[{a.cndot.F.sub.1(b, . . . ,n)}+{
.cndot.F.sub.0(b, . . . ,n)}] (B)
[0122] Some embodiments use TMUXs to implement the "if-then-else"
(ITE) expression needed for Shannon decomposition. For instance, if
the user design requires only four space-time contexts and the
space-time context generator supports generating eight
configuration data sets, the extra space-time context can be used
to perform a function that is decomposed using Shannon
decomposition.
[0123] For instance, the reconfigurable circuits can be programmed
to use one set of the space-time context (e.g., space-time context
0) if the user input (e.g., variable a in Equation A, above) is 1
and to use the other set of space-time context (e.g., space-time
context 2) if the user input is 0. The reconfigurable circuits are
then designed in a way that when they receive the space-time
context 0, they perform the first part of the Shannon decomposed
function (e.g., F.sub.1 (b, . . . ,n) in Equation A, above) and
when they receive the space-time context 2, they perform the other
part of the Shannon decomposed function (e.g., F.sub.0(b, . . . ,n)
in Equation A, above).
[0124] As an example, FIG. 18 illustrates a function, G that
requires four inputs a, b, c, and d. Shannon decomposition is used
to break this function into two functions with three inputs each.
Specifically, the four input function G(a, b, . . . , n) is
decomposed into two functions G.sub.0 and G.sub.1:
G(a,b,c,d)=[{a.cndot.G.sub.1(b,c,d)}+{a.cndot.G.sub.0(b,c,d)}]
As shown in FIG. 18, function G is implemented with two 3-input
logic circuits 1805 and 1810 as well as two AND gates and one OR
gate. FIG. 19 illustrates the use of a TMUX in implementing the
same function G. Multiplexer 1905 is designed to provide
configuration data sets 1915 to logic circuit (in this example, a
LUT) 1910. Depending on the value of its select signal, S,
multiplexer 1905 connects one of two groups of configuration data
sets to LUT 1910. As shown, the select signal is a function of
input "a" of function G. If a is 0, the group F(1), F(2), F(3),
F(4), F(5), and F(6) is used in a loop to configure the LUT.
Otherwise, if a is 1, the group F(1), F(0), F(3), F(4), F(5), and
F(6) is used in a loop to configure the LUT. By configuring LUT
1910 to perform function G.sub.0 when the LUT receives
configuration data set F(2) and to perform function G.sub.1 when
the LUT receives configuration data set F(0), the 3-input LUT 1910
can perform 4-input function G.
[0125] Shannon Decomposition based on the Early Arriving
Signals
[0126] FIG. 20 illustrates a process 2000 of some embodiments that
uses Shannon decomposition to decompose a function that has more
than a particular number of inputs. For instance, in some
embodiment if a certain portion of an IC has circuits to perform
3-input functions, the particular number of inputs is set to four.
The resulting functions are decomposed using Shannon decomposition
one more time as described further below in connection with FIG. 23
before being implemented. As shown in FIG. 20, the process receives
(at 2005) the function to decompose. The process determines (at
2010) whether the function has more than a particular number of
inputs. If no, the process exits. Otherwise, the process proceeds
to 2015 to compute the estimated arrival time of each input of the
function.
[0127] The process selects (at 2020) one of the inputs as the pivot
to perform Shannon decomposition. This input will be used, as input
"a" is used in equation (B) above, to decompose the received
function. In some embodiments, one of the earliest arriving input
is selected to perform the decomposition. An early arriving signal
is used to ensure that the input signal that is used in selecting
configuration bits arrives early and is stable at the beginning of
the sub-cycle. The use of an early arriving signal for doing
Shannon decomposition in this invention is in contrast to the use
of late arriving signals that is common with doing Shannon
decomposition in circuit design. Prior use of Shannon decomposition
in circuit design used the late arriving signals in doing the
decomposition in order to allow operations be done on the early
arriving signals selected with the late arriving signal.
[0128] In some embodiments, the early arriving input signals are
estimated by the number of logic circuits the signal has to travel
through to arrive at the input. For instance, as shown in FIG. 21
the signal for input "a" of the logic circuit 2105 has to go
through four logic circuits 2110-2125 while the input signal for
the input "d" has to go through only two logic circuits 2130-2135.
The signal for "d" input which goes through less number of circuits
is, therefore, estimated to arrive earlier than the signal for
input "a".
[0129] In some embodiments, a heuristic is used to select one of
the earliest arriving inputs to perform Shannon decomposition. The
selected input (not necessarily the particular earliest arriving
input) is chosen from a group of inputs that, when used as the
pivot in Shannon decomposition, will not cause any delays in
generating the final result of the received function. FIG. 22
conceptually illustrates a set of inputs i.sub.1 to i.sub.n that
are received by a circuit. Some embodiments identify a group of
early arriving signals 2205. For instance, in some embodiments
these inputs have to arrive before a threshold time 2210.
[0130] In some embodiments, this threshold time is a certain amount
time (shown by time period 2215) prior to an event 2220. In some
embodiments, this event 2220 is the time that the circuit produces
an output for the current user clock cycle. In other embodiments,
this event is the start of the next user clock cycle. In some
embodiments, the time period 2215 is selected such that it allows
for an arrived signal in input group 2205 to become stable for
being used during the next user clock cycle.
[0131] Different embodiments use different techniques to identify
which input in the early arriving input group 2205 to be used as
pivot for Shannon decomposition. Some embodiments perform trial and
error to select one of the inputs. Some embodiments associate a
cost (e.g., number of logic circuits, amount of required routing
resources, delays produced in generating the output, etc.) for the
decomposition and select an input that minimized the given cost.
Several heuristics for approximating disjoint decompositions are
described in "Logic Minimization Algorithms for VLSI Synthesis" by
Robert K. Brayton, et al. which is herein incorporated by
reference.
[0132] Referring to FIG. 20, after selecting one of the inputs to
perform Shannon decomposition, the process performs (at 2025)
Shannon decomposition on the received function based on the
identified input. The process then determines (at 2030) whether any
resulting functions of Shannon decomposition has more than the
particular number of inputs. When the process determines (at 2030)
that none of the resulting functions have more than the particular
number of inputs, the process proceeds to 2040 which is described
below. Otherwise, the process recursively calls itself (at 2035)
once for each of these functions. After the process receives the
results of its recursive calls, the process returns (at 2040) the
functions that the process identified itself or identified through
its recursive calls, and then ends.
[0133] When the original function has been broken down into a
series of functions with the particular number of inputs, the
original function is implemented using the available circuitry on
the IC. As an example, FIG. 23 illustrates a process 2300 that
facilitates implementing a 4-input function using a 3-input
reconfiguration circuit. Although this example is shown for a
4-input function, a person of ordinary skill in the art realizes
that the same technique can be used to implement any n-input
function with a reconfigurable circuit with n-1 inputs.
[0134] As shown. The process receives (at 2305) the function to be
implemented. The process then computes (at 2310) the estimated
arrival time of each of the input signals of the function. After
2310, the process selects (at 2315) an input as pivot for Shannon
decomposition as described in relation with process 2000 above.
Next, the process performs (at 2320) Shannon decomposition on the
function to extract this input. The process then assigns (at 2325)
the two resulting 3-input functions to two separate contexts of a
function generator (such as a LUT), where each one of the contexts
is selected in a particular sub-cycle based on the extracted
signal. The IC synthesizer has to designate an association between
the two functions in order for the placer to assign both functions
to the same LUT to ensure the correct operation of the resulting
TMUX.
VI. Space-Time Context Generator
[0135] A. ST-Context Generator
[0136] To facilitate the loopered scheme described in the previous
sections, some embodiments use a multi-tiered multiplexer structure
that uses three clocks signals CLK, STo, and STe to select
different configuration data sets for a configurable circuit. The
configuration data sets then determine the function that the
configurable circuit performs. In some embodiments, the
configuration data sets for configurable circuits are stored in
memory locations (e.g., in SRAM cells), referred to as
configuration storage. Examples of tiered multiplexer structures
are described in detail in the above mentioned U.S. patent
application Ser. No. 11/081,859.
[0137] In some embodiments, each one of the clock signals CLK, STo,
and STe are generated as a differential pair of signals. Some of
these embodiments globally distribute the differential pair of CLK
and CLK signals, while locally generating the signals STo
<0:3> and STe <0:3>. Some embodiments use a global
clock generator to generate the differential clock signals CLK and
CLK. In some embodiments, the global clock generator is outside of
the configurable tile arrangement (e.g., the generator might be on
a different circuit than the IC that includes the configurable tile
arrangement, or it might be partially or completely on the IC that
includes the arrangement but positioned outside of the
arrangement). However, in other embodiments, this global clock
generator can be placed within the configurable tile
arrangement.
[0138] In some embodiments, the globally distributed differential
clock signals CLK and CLK are received by two local ST-context
generators in each tile. FIG. 24 conceptually illustrates a tile
2400 of some embodiments. The local ST-context generator 2425 in
the tile provides the signals STo and STe for the tiered
multiplexer structures that retrieve and provide configuration data
sets to the routing multiplexers of the tile. The local ST-context
generator 2420 in the tile provides the signals STo and STe for the
tiered multiplexer structures that retrieve and provide
configuration data sets to the input select multiplexers and
three-input LUT of the tile. Having two different local ST-context
generators 2420 and 2425 for each tile allows the embodiments
illustrated in FIG. 24 to have the routing multiplexers of a tile
operate on different clock domains than the input select
multiplexers and the LUT of the tile. This is beneficial for
allowing the routing multiplexers of a tile to be used to route
signals that belong to different clock domains than the logic
circuits of the tile.
[0139] Having different local ST-context generators for different
tiles allows the embodiments illustrated in FIG. 24 to have
different tiles operate on different clock domains (i.e., on
different global clock signals that are based on different clock
domains). Specifically, some embodiments include one global clock
generator for each clock domain that the reconfigurable IC can
handle. For instance, an IC design might require the IC to
interface with two bus interfaces that operate at two different
rates and to implement a particular design that operates at yet
another rate. In such a situation, the reconfigurable IC might
include three global clock generators, two for generating the clock
signals associate with the two bus interfaces and one for receiving
the design clock signal, as illustrated in FIG. 25.
[0140] In some embodiments, the three global clock generators are
on the configurable IC and generate their three clocks based on
three clocks signals that they received from outside of the IC. As
shown, the local ST-context generators (2520 and 2525) within the
configurable tile 2500 are preceded by a set of multiplexers 2520
that route one of the globally distributed clocks and its
complement to each local ST-context generator. The local ST-context
generators in the tile then generate their local clocks STo and STe
based on the received global clocks. For instance, in the example
mentioned above, the local ST-context generators of the set of
tiles that implement one bus interface receive the global clock
signal for that bus interface and generate the local sub-cycle
signals that are needed to achieve the operational rate for
implementing the particular bus interface.
[0141] FIG. 26 illustrates an ST-context generator 2600 of some
embodiments. The ST-context generator 2600 is a signal generator
that can generate sub-cycle signals to drive (using e.g., tiered
multiplexers and configuration storage) a reconfigurable circuit to
go through the states in a loop similar to the loops shown in FIG.
2. This ST-context generator generates two sets of sub-cycle
signals STe (state-time even) and STo (state-time odd) that are
offset by 90.degree.. As shown, the sub-cycle signal STe is
generated by a next-state decoder 2605 and is latched by a set (or
a row) of latch drivers 2610. Similarly, the sub-cycle signal STo
is generated by a next-state decoder 2615 and is latched by the row
latch drivers 2630. In the example shown in FIG. 26, each set of
sub-cycle signals, STe and STo has four individual one-hot signals.
FIG. 27 illustrates an example of two sets of one-hot signals STo
and STe. As shown, at each point of time, only one of the signals
in each one-hot set is logical 1.
[0142] Each next-state decoder (2605 and 2615) act as a counter
that determines the next context generated. Specifically, the next
state decoder 2605 gets a one-hot state and generates a one-hot
next state. The output 2620 of this decoder is sent of a set of row
latches 2610. These latches are drivers with built-in latches.
Similarly, the next state decoder 2615 gets a one-hot state and
generates a one-hot next state. The output 2625 of this decoder is
sent of a set of row latches 2630. The next-state decoders can be
programmed to count up to a certain number depending on how many
configuration states are required. For instance, the next-state
decoders can be programmed to generate 4, 6, or 8 configuration
states.
[0143] In some embodiments, each set of latches 2610 or 2630
includes four latches connected in a row. The output of each of the
first three latches is connected to the input of the next latch.
The output of the last latch is fed back to the input of the
opposite next-state generator. As the latches are clocked, the
output value of each latch is copied to the input of the next
latch. In order to generate eight sub-cycle signals, each of the
STe and STo signals has to have four bits and each of the
next-state decoders 2605 and 2615 generate a four bit output 2620
and 2625 respectively. The output of the next-state decoder 2605 is
latched using the set of latches 2610. Similarly, the output of the
next-state decoder 2615 is latched using the set of latches 2630.
For eight sub-cycle signals, the output of each next-state decoder
will have four bits and each set of latches will have four latches.
As shown, the output of each row latch 2610 and 2630 are fed back
to the input of the other next state decoder (2615 and 2605,
respectively) in order to ensure that the two signals STe and STo
are offset by 90.degree..
[0144] As shown in FIG. 26, the clock signal (Clk)) is connected to
enable input (en) of row latches 2630 while Clk is connected to en
input. In contrast, Clk is connected to en input of row latches
2610 and Clk signal is connected to en input. The row latches 2610
and 2630, therefore, operate on different edges of the clock
signal. This arrangement eliminates the need for one set of flip
flops to operate on the rising edge of the clock and another set of
flip flops to operate on the falling edge of the clock.
[0145] B. ST-Context Generator that Generates Sub-cycle Signals
based on User-Design Signals
[0146] FIG. 28 illustrates an ST-context generator 2800 of some
embodiments that can generate configuration data sets based on a
user-design signal. This ST-context generator can generate
configuration data sets shown in FIGS. 2-5. This context generator
is similar to the context generator shown in FIG. 26 with the
addition of being able to utilize a user signal 2835 to determine
the signal generated by the next-state decoders 2805 and 2815.
[0147] In order to incorporate the user signal, two user latches
(2840 and 2845) are added to the ST-context generator. As shown,
the user signal 2835 is latched into user latches 2840 and 2845 and
is fed into the next-state decoders 2805 and 2815. Latching the
user signal ensures that user signal is stable while the next state
is calculated by the next-state decoders 2805 and 2815. The
next-state decoders 2805 and 2815 utilize the user signal 2835 to
generate the context for the next sub-cycle.
[0148] In some embodiments, two 4-aligned LUTs are tied together to
form a single tile, in order to save configuration storage and
configuration network overhead. FIG. 29 illustrates the
organization of one such tile in some embodiments. As shown, two
sets of 4-aligned LUTs and their associated IMUXs and RMUXs share
five configuration memories. The LUTs in each set of 4-aligned LUTs
share one carry chain. The addressing is done per half row. When
the context is changed for one of the RMUXs in each half row, the
context for all RMUXs in that half row is changed.
VII. Configurable IC and System
[0149] Some embodiments described above are implemented in
configurable ICs that can compute configurable combinational
digital logic functions on signals that are presented on the inputs
of the configurable ICs. In some embodiments, such computations are
state-less computations (i.e., do not depend on a previous state of
a value). Some embodiments described above are implemented in
configurable ICs that can perform a continuous function. In these
embodiments, the configurable IC can receive a continuous function
at its input, and in response, provide a continuous output at one
of its outputs.
[0150] FIG. 30 illustrates a portion of a configurable IC 3000 of
some embodiments of the invention. As shown in this figure, this IC
has a configurable circuit arrangement 3005 and I/O circuitry 3010.
The configurable circuit arrangement 3005 can be any of the
invention's configurable circuit arrangements that were described
above. The I/O circuitry 3010 is responsible for routing data
between the configurable nodes 3015 of the configurable circuit
arrangement 3005 and circuits outside of this arrangement (i.e.,
circuits outside of the IC, or within the IC but outside of the
configurable circuit arrangement 3005). As further described below,
such data includes data that needs to be processed or passed along
by the configurable nodes.
[0151] The data also includes in some embodiments configuration
data that configure the nodes to perform particular operations.
FIG. 31 illustrates a more detailed example of this. Specifically,
this figure illustrates a configuration data pool 3105 for the
configurable IC 3000. This pool includes N configuration data sets
(CDS). As shown in FIG. 31, the input/output circuitry 3010 of the
configurable IC 3000 routes different configuration data sets to
different configurable nodes of the IC 3000. For instance, FIG. 31
illustrates configurable node 3145 receiving configuration data
sets 1, 3, and J through the I/O circuitry, while configurable node
3150 receives configuration data sets 3, K, and N-1 through the I/O
circuitry. In some embodiments, the configuration data sets are
stored within each configurable node. Also, in some embodiments, a
configurable node can store multiple configuration data sets so
that it can reconfigure quickly by changing to another
configuration data set. In some embodiments, some configurable
nodes store only one configuration data set, while other
configurable nodes store multiple such data sets.
[0152] A configurable IC of the invention can also include circuits
other than a configurable circuit arrangement and I/O circuitry.
For instance, FIG. 32 illustrates a system on chip ("SoC")
implementation of a configurable IC 3200. This IC has a
configurable block 3250, which includes a configurable circuit
arrangement 3105 and I/O circuitry 3110 for this arrangement. It
also includes a processor 3215 outside of the configurable circuit
arrangement, a memory 3220, and a bus 3210, which conceptually
represents all conductive paths between the processor 3215, memory
3220, and the configurable block 3250. As shown in FIG. 32, the IC
3200 couples to a bus 3230, which communicatively couples the IC to
other circuits, such as an off-chip memory 3225. Bus 3230
conceptually represents all conductive paths between the components
of the IC 3200.
[0153] This processor 3215 can read and write instructions and/or
data from an on-chip memory 3220 or an off-chip memory 3225. The
processor 3215 can also communicate with the configurable block
3250 through memory 3220 and/or 3225 through buses 3210 and/or
3230. Similarly, the configurable block can retrieve data from and
supply data to memories 3220 and 3225 through buses 3210 and
3230.
[0154] Instead of, or in conjunction with, the system on chip
("SoC") implementation for a configurable IC, some embodiments
might employ a system in package ("SiP") implementation for a
configurable IC. FIG. 33 illustrates one such SiP 3300. As shown in
this figure, SiP 3300 includes four ICs 3320, 3325, 3330, and 3335
that are stacked on top of each other on a substrate 3305. At least
one of these ICs is a configurable IC that includes a configurable
block, such as the configurable block 3250 of FIG. 32. Other ICs
might be other circuits, such as processors, memory, etc.
[0155] As shown in FIG. 33, the IC communicatively connects to the
substrate 3305 (e.g., through wire bondings 3360). These wire
bondings allow the ICs 3320-3335 to communicate with each other
without having to go outside of the SiP 3300. In some embodiments,
the ICs 3320-3335 might be directly wire-bonded to each other in
order to facilitate communication between these ICs. Instead of, or
in conjunction with the wire bondings, some embodiments might use
other mechanisms to communicatively couple the ICs 3320-3335 to
each other.
[0156] As further shown in FIG. 33, the SiP includes a ball grid
array ("BGA") 3310 and a set of vias 3315. The BGA 3310 is a set of
solder balls that allows the SiP 3300 to be attached to a printed
circuit board ("PCB"). Each via connects a solder ball in the BGA
3310 on the bottom of the substrate 3305, to a conductor on the top
of the substrate 3305.
[0157] The conductors on the top of the substrate 3305 are
electrically coupled to the ICs 3320-3335 through the wire
bondings. Accordingly, the ICs 3320-3335 can send and receive
signals to and from circuits outside of the SiP 3300 through the
wire bondings, the conductors on the top of the substrate 3305, the
set of vias 3315, and the BGA 3310. Instead of a BGA, other
embodiments might employ other structures (e.g., a pin grid array)
to connect a SiP to circuits outside of the SiP. As shown in FIG.
33, a housing 3380 encapsulates the substrate 3305, the BGA 3310,
the set of vias 3315, the ICs 3320-3335, the wire bondings to form
the SiP 3300. This and other SiP structures are further described
in U.S. patent application Ser. No. 11/081,820 entitled "Method for
Manufacturing a Programmable System In Package", filed on Mar. 15,
2005.
[0158] FIG. 34 conceptually illustrates a more detailed example of
an electronics system 3400 that has an IC 3405, which implements
some of the above described inventions (such as using TMUXs to do
multiplication, using TMUXs to utilize Shannon decomposition, etc).
The system 3400 can be a stand-alone computing or communication
device, or it can be part of another electronic device. As shown in
FIG. 34, the system 3400 not only includes the IC 3405, but also
includes a bus 3410, a system memory 3415, a non-volatile memory
3420, a storage device 3425, input devices 3430, output devices
3435, and communication interface 3440. In some embodiments, the
non-volatile memory 3420 stores configuration data and re-loads it
at power-up. Although the non-volatile memory 3420 is shown outside
of the IC 3405, in some embodiments, the non-volatile memory is
either on the same die or the same package as the IC 3405.
[0159] The bus 3410 collectively represents all system, peripheral,
and chipset interconnects (including bus and non-bus interconnect
structures) that communicatively connect the numerous internal
devices of the system 3400. For instance, the bus 3410
communicatively connects the IC 3410 with the non-volatile memory
3420, the system memory 3415, and the permanent storage device
3425.
[0160] From these various memory units, the IC 3405 receives data
for processing and configuration data for configuring the ICs
configurable logic and/or interconnect circuits. When the IC 3405
has a processor, the IC also retrieves from the various memory
units instructions to execute. The non-volatile memory 3420 stores
static data and instructions that are needed by the IC 3410 and
other modules of the system 3400. The storage device 3425, on the
other hand, is read-and-write memory device. This device is a
non-volatile memory unit that stores instruction and/or data even
when the system 3400 is off. Like the storage device 3425, the
system memory 3415 is a read-and-write memory device. However,
unlike storage device 3425, the system memory is a volatile
read-and-write memory, such as a random access memory. The system
memory stores some of the instructions and/or data that the IC
needs at runtime.
[0161] The bus 3410 also connects to the input and output devices
3430 and 3435. The input devices enable the user to enter
information into the system 3400. The input devices 3430 can
include touch-sensitive screens, keys, buttons, keyboards,
cursor-controllers, microphone, etc. The output devices 3435
display the output of the system 3400.
[0162] Finally, as shown in FIG. 34, bus 3410 also couples system
3400 to other devices through a communication interface 3440.
Examples of the communication interface include network adapters
that connect to a network of computers, or wired or wireless
transceivers for communicating with other devices. One of ordinary
skill in the art would appreciate that any other system
configuration may also be used in conjunction with the invention,
and these system configurations might have fewer or additional
components.
[0163] While the invention has been described with reference to
numerous specific details, one of ordinary skill in the art will
recognize that the invention can be embodied in other specific
forms without departing from the spirit of the invention. Thus, one
of ordinary skill in the art would understand that the invention is
not to be limited by the foregoing illustrative details, but rather
is to be defined by the appended claims.
* * * * *