loadpatents
Patent applications and USPTO patent grants for Caldwell; Andrew.The latest application filed is for "timer services".
Patent | Date |
---|---|
Media gateway Grant 11,218,517 - Caldwell , et al. January 4, 2 | 2022-01-04 |
Timer Services App 20210274003 - CALDWELL; Andrew ;   et al. | 2021-09-02 |
Timer services Grant 10,958,738 - Caldwell , et al. March 23, 2 | 2021-03-23 |
Telephony signalling element Grant 10,834,143 - Caldwell , et al. November 10, 2 | 2020-11-10 |
Media Gateway App 20200329076 - CALDWELL; Andrew ;   et al. | 2020-10-15 |
Processing notifications relating to telecommunication sessions Grant 10,785,823 - Williams , et al. Sept | 2020-09-22 |
Media gateway Grant 10,637,893 - Caldwell , et al. | 2020-04-28 |
Timer Services App 20190182339 - CALDWELL; Andrew ;   et al. | 2019-06-13 |
Processing Notifications Relating To Telecommunication Sessions App 20190132902 - WILLIAMS; Matthew ;   et al. | 2019-05-02 |
Media Gateway App 20190014157 - CALDWELL; Andrew ;   et al. | 2019-01-10 |
Telephony Signalling Element App 20180352007 - CALDWELL; Andrew ;   et al. | 2018-12-06 |
Processing notifications relating to telecommunication sessions Grant 10,123,364 - Williams , et al. November 6, 2 | 2018-11-06 |
Implementation of related clocks Grant 9,954,530 - Ebeling , et al. April 24, 2 | 2018-04-24 |
Transport network Grant 9,659,124 - Hutchings , et al. May 23, 2 | 2017-05-23 |
Processing Notifications Relating To Telecommunication Sessions App 20170064772 - WILLIAMS; Matthew ;   et al. | 2017-03-02 |
Optimizing IC design using retiming and presenting design simulation results as rescheduling optimization Grant 9,582,634 - Teig , et al. February 28, 2 | 2017-02-28 |
Optimizing IC performance using sequential timing Grant 9,582,635 - Teig , et al. February 28, 2 | 2017-02-28 |
Method and apparatus for decomposing functions in a configurable IC Grant 9,507,900 - Caldwell , et al. November 29, 2 | 2016-11-29 |
Identifying the cause of timing failure of an IC design using sequential timing Grant 9,501,606 - Teig , et al. November 22, 2 | 2016-11-22 |
Sequential timing using level-sensitive clocked elements to optimize IC performance Grant 9,436,794 - Teig , et al. September 6, 2 | 2016-09-06 |
Operational Time Extension App 20160087635 - Rohe; Andre ;   et al. | 2016-03-24 |
Rescaling Grant 9,257,986 - Weber , et al. February 9, 2 | 2016-02-09 |
Processing communication status information Grant 9,247,072 - Caldwell , et al. January 26, 2 | 2016-01-26 |
Identifying The Cause Of Timing Failure Of An Ic Design Using Sequential Timing App 20150324513 - Teig; Steven ;   et al. | 2015-11-12 |
Sequential Timing Using Level-sensitive Clocked Elements To Optimize Ic Performance App 20150324512 - Teig; Steven ;   et al. | 2015-11-12 |
Optimizing Ic Performance Using Sequential Timing App 20150324514 - Teig; Steven ;   et al. | 2015-11-12 |
Timing operations in an IC with configurable circuits Grant 9,183,344 - Teig , et al. November 10, 2 | 2015-11-10 |
Configurable storage elements Grant 9,154,134 - Voogel , et al. October 6, 2 | 2015-10-06 |
Configurable storage elements Grant 9,148,151 - Teig , et al. September 29, 2 | 2015-09-29 |
Timer Services App 20150215152 - CALDWELL; Andrew ;   et al. | 2015-07-30 |
Implementation Of Related Clocks App 20150200671 - Ebeling; Christopher D. ;   et al. | 2015-07-16 |
Optimizing Ic Design Using Retiming And Presenting Design Simulation Results As Rescheduling Optimization App 20150186561 - Teig; Steven ;   et al. | 2015-07-02 |
Transport Network App 20150154332 - Hutchings; Brad ;   et al. | 2015-06-04 |
Operational time extension Grant 9,041,430 - Rohe , et al. May 26, 2 | 2015-05-26 |
Decision Modules App 20150135148 - Caldwell; Andrew ;   et al. | 2015-05-14 |
Implementation of related clocks Grant 9,000,801 - Ebeling , et al. April 7, 2 | 2015-04-07 |
Method and Apparatus for Decomposing Functions in a Configurable IC App 20150082261 - Caldwell; Andrew ;   et al. | 2015-03-19 |
Operating A User Device App 20150067807 - WILLIAMS; Matthew ;   et al. | 2015-03-05 |
Sequential Delay Analysis By Placement Engines App 20150040094 - Caldwell; Andrew ;   et al. | 2015-02-05 |
Decision modules Grant 8,935,647 - Caldwell , et al. January 13, 2 | 2015-01-13 |
Transport network Grant 8,935,640 - Hutchings , et al. January 13, 2 | 2015-01-13 |
Configurable Storage Elements App 20140333345 - Voogel; Martin ;   et al. | 2014-11-13 |
Processing Communication Status Information App 20140323083 - CALDWELL; Andrew ;   et al. | 2014-10-30 |
Timing Operations In An IC With Configurable Circuits App 20140317588 - Teig; Steven ;   et al. | 2014-10-23 |
Sequential delay analysis by placement engines Grant 8,863,067 - Caldwell , et al. October 14, 2 | 2014-10-14 |
Detecting Aberrant Behavior In An Exam-taking Environment App 20140272882 - Kaufman; James ;   et al. | 2014-09-18 |
Operational Time Extension App 20140240001 - Rohe; Andre ;   et al. | 2014-08-28 |
Rescaling App 20140210512 - Weber; Scott J. ;   et al. | 2014-07-31 |
Rescaling Grant 8,788,987 - Weber , et al. July 22, 2 | 2014-07-22 |
Configurable storage elements Grant 8,760,193 - Voogel , et al. June 24, 2 | 2014-06-24 |
Timing operations in an IC with configurable circuits Grant 8,756,547 - Teig , et al. June 17, 2 | 2014-06-17 |
Method and apparatus for decomposing functions in a configurable IC Grant 8,726,213 - Caldwell , et al. May 13, 2 | 2014-05-13 |
Translating a User Design in a Configurable IC for Debugging the User Design App 20140109028 - Hutchings; Brad ;   et al. | 2014-04-17 |
Operational time extension Grant 8,664,974 - Rohe , et al. March 4, 2 | 2014-03-04 |
Rescaling Grant 8,650,514 - Weber , et al. February 11, 2 | 2014-02-11 |
Decision Modules App 20140007027 - Caldwell; Andrew ;   et al. | 2014-01-02 |
Decision modules Grant 8,555,218 - Caldwell , et al. October 8, 2 | 2013-10-08 |
Performing mathematical and logical operations in multiple sub-cycles Grant 8,463,836 - Pugh , et al. June 11, 2 | 2013-06-11 |
Decision modules in integrated circuit design Grant 8,458,629 - Caldwell , et al. June 4, 2 | 2013-06-04 |
Translating a user design in a configurable IC for debugging the user design Grant 8,429,579 - Hutchings , et al. April 23, 2 | 2013-04-23 |
Rescaling App 20130097575 - Weber; Scott J. ;   et al. | 2013-04-18 |
Configurable Storage Elements App 20130093462 - Teig; Steven ;   et al. | 2013-04-18 |
Configurable Storage Elements App 20130093460 - Voogel; Martin ;   et al. | 2013-04-18 |
Timing Operations In An Ic With Configurable Circuits App 20120182046 - Teig; Steven ;   et al. | 2012-07-19 |
Rescaling App 20120176155 - Weber; Scott J. ;   et al. | 2012-07-12 |
Translating a User Design in A Configurable IC for Debugging the User Design App 20120117525 - Hutchings; Brad ;   et al. | 2012-05-10 |
Method And Apparatus For Performing An Operation With A Plurality Of Sub-operations In A Configurable Ic App 20120098568 - Redgrave; Jason ;   et al. | 2012-04-26 |
Timing operations in an IC with configurable circuits Grant 8,166,435 - Teig , et al. April 24, 2 | 2012-04-24 |
Method and apparatus for routing with independent goals on different layers Grant 8,112,733 - Frankle , et al. February 7, 2 | 2012-02-07 |
Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC Grant 8,112,468 - Redgrave , et al. February 7, 2 | 2012-02-07 |
Translating a user design in a configurable IC for debugging the user design Grant 8,069,425 - Hutchings , et al. November 29, 2 | 2011-11-29 |
Operational Time Extension App 20110181317 - Rohe; Andre ;   et al. | 2011-07-28 |
IC that efficiently replicates a function to save logic and routing resources Grant 7,971,172 - Pugh , et al. June 28, 2 | 2011-06-28 |
Decision Modules App 20110154278 - Caldwell; Andrew ;   et al. | 2011-06-23 |
Decision Modules App 20110154279 - Caldwell; Andrew ;   et al. | 2011-06-23 |
System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture Grant 7,962,705 - Schmit , et al. June 14, 2 | 2011-06-14 |
Operational time extension Grant 7,898,291 - Rohe , et al. March 1, 2 | 2011-03-01 |
System And Method For Providing A Virtual Memory Architecture Narrower And Deeper Than A Physical Memory Architecture App 20100241800 - Schmit; Herman ;   et al. | 2010-09-23 |
Use of hybrid interconnect/logic circuits for multiplication Grant 7,765,249 - Pugh , et al. July 27, 2 | 2010-07-27 |
Plow Device and Method App 20100088930 - Brame; Gregory ;   et al. | 2010-04-15 |
System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture Grant 7,694,083 - Schmit , et al. April 6, 2 | 2010-04-06 |
Operational Time Extension App 20100066407 - Rohe; Andre ;   et al. | 2010-03-18 |
Timing operations in an IC with configurable circuits App 20090327987 - Teig; Steven ;   et al. | 2009-12-31 |
Configurable integrated circuit with a 4-to-1 multiplexer Grant 7,609,085 - Schmit , et al. October 27, 2 | 2009-10-27 |
Method and apparatus for function decomposition Grant 7,610,566 - Caldwell , et al. October 27, 2 | 2009-10-27 |
Method and Apparatus for Decomposing Functions in a Configurable IC App 20090243651 - Caldwell; Andrew ;   et al. | 2009-10-01 |
Operational time extension Grant 7,587,698 - Rohe , et al. September 8, 2 | 2009-09-08 |
Configurable ICs that conditionally transition through configuration data sets Grant 7,535,252 - Teig , et al. May 19, 2 | 2009-05-19 |
Method and apparatus for decomposing functions in a configurable IC Grant 7,530,033 - Caldwell , et al. May 5, 2 | 2009-05-05 |
Method And Apparatus For Routing With Independent Goals On Different Layers App 20090077522 - Frankle; Jonathan ;   et al. | 2009-03-19 |
Method and apparatus for routing with independent goals on different layers Grant 7,480,885 - Frankle , et al. January 20, 2 | 2009-01-20 |
Translating A User Design In A Configurable Ic For Debugging The User Design App 20090007027 - Hutchings; Brad ;   et al. | 2009-01-01 |
Replacing circuit design elements with their equivalents Grant 7,461,362 - Caldwell , et al. December 2, 2 | 2008-12-02 |
Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources Grant 7,372,297 - Pugh , et al. May 13, 2 | 2008-05-13 |
Interconnect lines with non-rectilinear terminations Grant 7,310,793 - Teig , et al. December 18, 2 | 2007-12-18 |
Method and apparatus for decomposing functions in a configurable IC App 20070257700 - Caldwell; Andrew ;   et al. | 2007-11-08 |
Method and apparatus for computing cost of a path expansion to a surface Grant 7,246,338 - Teig , et al. July 17, 2 | 2007-07-17 |
Operational time extension Grant 7,236,009 - Rohe , et al. June 26, 2 | 2007-06-26 |
Routing method and apparatus Grant 7,155,697 - Teig , et al. December 26, 2 | 2006-12-26 |
Method for layout of gridless non manhattan integrated circuits with tile based router Grant 7,143,383 - Teig , et al. November 28, 2 | 2006-11-28 |
Method and apparatus for decomposing a design layout Grant 7,114,141 - Teig , et al. September 26, 2 | 2006-09-26 |
Method and apparatus for routing a set of nets Grant 7,107,564 - Teig , et al. September 12, 2 | 2006-09-12 |
Topological vias route wherein the topological via does not have a coordinate within the region Grant 7,089,524 - Teig , et al. August 8, 2 | 2006-08-08 |
Method and apparatus for identifying optimized via locations Grant 7,080,329 - Teig , et al. July 18, 2 | 2006-07-18 |
Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space Grant 7,073,151 - Teig , et al. July 4, 2 | 2006-07-04 |
Method and apparatus for routing groups of paths Grant 7,069,530 - Teig , et al. June 27, 2 | 2006-06-27 |
Method and apparatus for identifying a path between source and target states in a space with more than two dimensions Grant 7,069,531 - Teig , et al. June 27, 2 | 2006-06-27 |
Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space Grant 7,058,917 - Teig , et al. June 6, 2 | 2006-06-06 |
Method and apparatus for specifying a distance between an external state and a set of states in space Grant 7,051,298 - Teig , et al. May 23, 2 | 2006-05-23 |
Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space Grant 7,047,512 - Teig , et al. May 16, 2 | 2006-05-16 |
Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's Grant 7,036,105 - Teig , et al. April 25, 2 | 2006-04-25 |
Method and apparatus for decomposing a region of an integrated circuit layout Grant 7,032,201 - Teig , et al. April 18, 2 | 2006-04-18 |
Method and apparatus for decomposing a region of an integrated circuit layout Grant 7,020,863 - Teig , et al. March 28, 2 | 2006-03-28 |
Method and apparatus for propagating cost functions Grant 7,013,448 - Teig , et al. March 14, 2 | 2006-03-14 |
Method and apparatus for routing Grant 7,003,752 - Teig , et al. February 21, 2 | 2006-02-21 |
Method and apparatus for propagating a piecewise linear function to a surface Grant 7,000,209 - Teig , et al. February 14, 2 | 2006-02-14 |
Method and apparatus for routing Grant 6,988,257 - Teig , et al. January 17, 2 | 2006-01-17 |
Method and apparatus for identifying a path between source and target states Grant 6,986,117 - Teig , et al. January 10, 2 | 2006-01-10 |
Method and apparatus for propagating a piecewise linear function to a point Grant 6,978,432 - Teig , et al. December 20, 2 | 2005-12-20 |
Circular vias and interconnect-line ends Grant 6,976,238 - Teig , et al. December 13, 2 | 2005-12-13 |
IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout Grant 6,973,634 - Teig , et al. December 6, 2 | 2005-12-06 |
Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring App 20050240893 - Teig, Steven ;   et al. | 2005-10-27 |
Gridless IC layout and method and apparatus for generating such a layout Grant 6,957,411 - Teig , et al. October 18, 2 | 2005-10-18 |
Method and apparatus for routing nets in an integrated circuit layout Grant 6,957,408 - Teig , et al. October 18, 2 | 2005-10-18 |
Method and apparatus for generating topological routes for IC layouts using perturbations Grant 6,957,409 - Teig , et al. October 18, 2 | 2005-10-18 |
Method and apparatus for selecting a route for a net based on the impact on other nets Grant 6,951,005 - Teig , et al. September 27, 2 | 2005-09-27 |
Decomposing IC regions and embedding routes Grant 6,951,006 - Teig , et al. September 27, 2 | 2005-09-27 |
Method and apparatus for costing a path expansion Grant 6,948,144 - Teig , et al. September 20, 2 | 2005-09-20 |
Method and apparatus for proportionate costing of vias Grant 6,944,841 - Teig , et al. September 13, 2 | 2005-09-13 |
Method and apparatus for defining vias Grant 6,938,234 - Teig , et al. August 30, 2 | 2005-08-30 |
Method and apparatus for identifying a path between source and target states Grant 6,931,615 - Teig , et al. August 16, 2 | 2005-08-16 |
Method and apparatus for determining viability of path expansions Grant 6,931,608 - Teig , et al. August 16, 2 | 2005-08-16 |
IC layout having topological routes Grant 6,928,633 - Teig , et al. August 9, 2 | 2005-08-09 |
Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring Grant 6,915,500 - Teig , et al. July 5, 2 | 2005-07-05 |
Method and apparatus for propagating a piecewise linear function to a line Grant 6,915,499 - Teig , et al. July 5, 2 | 2005-07-05 |
Method and apparatus for defining vias Grant 6,898,772 - Teig , et al. May 24, 2 | 2005-05-24 |
Method and apparatus for producing multi-layer topological routes Grant 6,898,773 - Teig , et al. May 24, 2 | 2005-05-24 |
Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs Grant 6,895,567 - Teig , et al. May 17, 2 | 2005-05-17 |
IC layout with non-quadrilateral Steiner points Grant 6,895,569 - Teig , et al. May 17, 2 | 2005-05-17 |
Method and apparatus for propagating a function Grant 6,889,371 - Teig , et al. May 3, 2 | 2005-05-03 |
Method and apparatus for routing Grant 6,889,372 - Teig , et al. May 3, 2 | 2005-05-03 |
Method and apparatus for routing sets of nets Grant 6,886,149 - Teig , et al. April 26, 2 | 2005-04-26 |
Non-rectilinear polygonal vias Grant 6,882,055 - Teig , et al. April 19, 2 | 2005-04-19 |
Method and apparatus for routing a set of nets Grant 6,877,146 - Teig , et al. April 5, 2 | 2005-04-05 |
Polygonal vias Grant 6,859,916 - Teig , et al. February 22, 2 | 2005-02-22 |
Method and apparatus for generating multi-layer routes Grant 6,829,757 - Teig , et al. December 7, 2 | 2004-12-07 |
Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits Grant 6,769,105 - Teig , et al. July 27, 2 | 2004-07-27 |
Method and apparatus for routing with independent goals on different layers App 20040098697 - Frankle, Jonathan ;   et al. | 2004-05-20 |
Method and apparatus for routing App 20040098695 - Teig, Steven ;   et al. | 2004-05-20 |
Method and apparatus for routing App 20040098696 - Teig, Steven ;   et al. | 2004-05-20 |
Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits Grant 6,711,727 - Teig , et al. March 23, 2 | 2004-03-23 |
Routing method and apparatus App 20030066043 - Teig, Steven ;   et al. | 2003-04-03 |
Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction Grant 6,526,555 - Teig , et al. February 25, 2 | 2003-02-25 |
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