U.S. patent application number 13/194089 was filed with the patent office on 2012-02-02 for modular frequency divider and mixer configuration.
Invention is credited to Stefano Dal Toso, Danilo Gerna, Gregory Uehara.
Application Number | 20120027121 13/194089 |
Document ID | / |
Family ID | 45526701 |
Filed Date | 2012-02-02 |
United States Patent
Application |
20120027121 |
Kind Code |
A1 |
Gerna; Danilo ; et
al. |
February 2, 2012 |
Modular Frequency Divider and Mixer Configuration
Abstract
A system including a first frequency divider, a plurality of
second frequency dividers, and a control module. The first
frequency divider includes a first plurality of components and is
configured to divide an input frequency of an input signal to
generate a first signal having a first frequency and a first phase.
Each of the plurality of second frequency dividers includes a
second plurality of components and is configured to divide the
input frequency of the input signal to generate a second signal
having the first frequency and a second phase. The control module
is configured to connect the second plurality of components of one
of the second frequency dividers to the first plurality of
components of the first frequency divider.
Inventors: |
Gerna; Danilo; (Fino
Mornasco, IT) ; Dal Toso; Stefano; (Montegalda,
IT) ; Uehara; Gregory; (Austin, TX) |
Family ID: |
45526701 |
Appl. No.: |
13/194089 |
Filed: |
July 29, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61368935 |
Jul 29, 2010 |
|
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|
61480335 |
Apr 28, 2011 |
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Current U.S.
Class: |
375/295 ;
327/118 |
Current CPC
Class: |
H03B 19/00 20130101;
H04B 1/0483 20130101; H03L 7/18 20130101; H04B 2001/0491 20130101;
H03K 23/667 20130101 |
Class at
Publication: |
375/295 ;
327/118 |
International
Class: |
H04L 27/00 20060101
H04L027/00; G06G 7/16 20060101 G06G007/16 |
Claims
1. A system comprising: a first frequency divider configured to
divide an input frequency of an input signal to generate a first
signal having a first frequency and a first phase, wherein the
first frequency divider includes a first plurality of components; a
plurality of second frequency dividers each configured to divide
the input frequency of the input signal to generate a second signal
having the first frequency and a second phase, wherein each of the
second frequency dividers includes a second plurality of
components; and a control module configured to connect the second
plurality of components of one of the second frequency dividers to
the first plurality of components of the first frequency
divider.
2. The system of claim 1, wherein, in response to the control
module sequential connecting the second plurality of components of
the one of the second frequency dividers to the first plurality of
components of the first frequency divider, the second phase of the
second signal generated by the one of the second frequency dividers
matches the first phase of the first signal generated by the first
frequency divider.
3. The system of claim 1, wherein: the first plurality of
components of the first frequency divider has a first area; and the
second plurality of components of each of the second frequency
dividers has a second area that is less than the first area.
4. The system of claim 1, wherein the control module is configured
to connect the second plurality of components of the one of the
second frequency dividers to the first plurality of components of
the first frequency divider via a plurality of pass transistors and
by turning on the plurality of pass transistors at a same time.
5. The system of claim 1, further comprising a mixer configured to
upconvert a transmit signal using a clock signal, wherein the clock
signal includes the first signal generated by the first frequency
divider and the second signal generated by the one of the second
frequency dividers.
6. The system of claim 5, wherein each of the first and second
frequency dividers is further configured to: divide the input
signal by a first factor when the transmit signal is transmitted in
a first frequency band; and divide the input signal by a second
factor when the transmit signal is transmitted in a second
frequency band, wherein the second factor is different than the
first factor, and wherein the second band is different than the
first band.
7. The system of claim 1, wherein the control module is further
configured to sequentially connect the plurality of second
frequency dividers in parallel to the first frequency divider,
wherein, in response to the control module sequentially connecting
the plurality of second frequency dividers in parallel to the first
frequency divider, the second phase of the second signal generated
by each of the plurality of second frequency dividers matches the
first phase of the first signal generated by the first frequency
divider.
8. The system of claim 1, further comprising: a first mixer
configured to upconvert a transmit signal using a first clock
signal, wherein the first clock signal includes the first signal
generated by the first frequency divider; and a second mixer
configured to upconvert the transmit signal using a second clock
signal, wherein the second clock signal includes the first signal
generated by the first frequency divider and the second signal
generated by each of the plurality of second frequency dividers
connected to the first frequency divider, wherein the control
module is further configured to activate the first mixer when the
transmit signal is transmitted at a first power level, and
deactivate the first and activate the second mixer when the
transmit signal is transmitted at a second power level that is
greater than the first power level.
9. The system of claim 8, wherein: the first mixer includes
components having a first area; and the second mixer includes
components having a second area that is greater than the first
area.
10. The system of claim 8, wherein a number of the second frequency
dividers connected in parallel to the first frequency divider
depends on the first and second power levels.
11. A system comprising: a first frequency divider including, a
first divider configured to divide an input frequency of an input
signal and generate a first signal, wherein the first divider
includes first components; and a second divider configured to
divide the first signal and generate a second signal, wherein the
second divider includes second components; a second frequency
divider including a third divider configured to divide the input
frequency and generate a third signal, wherein the third divider
includes third components; and a fourth divider configured to
divide the third signal and generate a fourth signal, wherein the
fourth divider includes fourth components; and a control module
configured to selectively activate the first and third dividers,
deactivate the second and fourth dividers, and sequentially connect
the third components of the third divider to the first components
of the first divider, or selectively activate the first, second,
third, and fourth dividers, sequentially connect the third
components of the third divider to the first components of the
first divider, and sequentially connect the fourth components of
the fourth divider to the second components of the second
divider.
12. The system of claim 11, wherein: the first components of the
first divider have a first area; the first signal has a first
phase; the third components of the third divider have a second area
that is less than the first area; the third signal has a second
phase; and in response to the control module connecting the third
components of the third divider to the first components of the
first divider, the second phase matches the first phase.
13. The system of claim 11, wherein: the first and second
components of the first and second dividers collectively have a
first area; the third and fourth components of the third and fourth
dividers collectively have a second area that is less than the
first area; the second signal has a first phase; the fourth signal
has a second phase; and in response to the control module
connecting the third components of the third divider to the first
components of the first divider and connecting the fourth
components of the fourth divider to the second components of the
second divider, the second phase matches the first phase.
14. The system of claim 11, further comprising a mixer configured
to upconvert a transmit signal using the first signal generated by
the first divider and the third signal generated by the third
divider in response to the control module connecting the third
components of the third divider to the first components of the
first divider.
15. The system of claim 11, further comprising a mixer configured
to upconvert transmit signal using the second signal generated by
the second divider and the fourth signal generated by the fourth
divider in response to the control module connecting the third
components of the third divider to the first components of the
first divider and connecting the fourth components of the fourth
divider to the second components of the second divider.
16. The system of claim 11, further comprising: a first mixer
configured to upconvert a transmit signal using a first clock
signal, wherein the first mixer includes a first plurality of
components having a first area; and a second mixer configured to
upconvert the transmit signal using a second clock signal, wherein
the second mixer includes a second plurality of components having a
second area that is greater than the first area, wherein the
control module is configured to activate the first mixer when the
transmit signal is transmitted at a first power level, and
deactivate the first mixer and activate the second mixer when the
transmit signal is transmitted at a second power level that is
greater than the first power level.
17. The system of claim 16, wherein: the first clock signal
includes the first signal generated by the first divider and the
third signal generated by the third divider when the transmit
signal is transmitted at the first power level in a first frequency
band; the first clock signal includes the second signal generated
by the second divider and the fourth signal generated by the fourth
divider when the transmit signal is transmitted at the first power
level in a second frequency band that is different than the first
frequency band; the second clock signal includes the first signal
generated by the first divider and the third signal generated by
the third divider when the transmit signal is transmitted at the
second power level in the first frequency band; and the second
clock signal includes the second signal generated by the second
divider and the fourth signal generated by the fourth divider when
the transmit signal is transmitted at the second power level in the
second frequency band.
18. The system of claim 17, wherein the control module is
configured to: activate the first and third dividers and deactivate
the second and fourth dividers when the transmit signal is
transmitted in the first frequency band, and activate the first,
second, third, and fourth dividers when the transmit signal is
transmitted in the second frequency band.
19. A method comprising: dividing an input frequency of an input
signal to generate a first signal having a first frequency and a
first phase using a first frequency divider, wherein the first
frequency divider includes a first plurality of components;
dividing the input frequency of the input signal using each of a
plurality of second frequency dividers to generate a second signal
having the first frequency and a second phase, wherein each of the
second frequency dividers includes a second plurality of
components; and connecting the second plurality of components of
one of the second frequency dividers to the first plurality of
components of the first frequency divider.
20. The method of claim 19, further comprising sequentially
connecting the plurality of second frequency dividers in parallel
to the first frequency divider, wherein in response to sequentially
connecting the plurality of second frequency dividers in parallel
to the first frequency divider, the second phase of the second
signal generated by each of the plurality of second frequency
dividers matches the first phase of the first signal generated by
the first frequency divider.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 61/368,935, filed on Jul. 29, 2010 and U.S.
Provisional Application No. 61/480,335, filed on Apr. 28, 2011. The
disclosures of the above applications are incorporated herein by
reference in their entirety.
FIELD
[0002] The present disclosure relates generally to communication
systems and more particularly to modular frequency dividers used in
transmitters.
BACKGROUND
[0003] The background description provided herein is for the
purpose of generally presenting the context of the disclosure. Work
of the presently named inventors, to the extent the work is
described in this background section, as well as aspects of the
description that may not otherwise quality as prior art at the time
of filing, are neither expressly nor impliedly admitted as prior
art against the present disclosure.
[0004] Referring now to FIG. 1A, a transmitter 100 of a wireless
device is shown for example only. The transmitter 100 includes a
baseband processing module 102, an upconverter module 104, a power
amplifier module 106, and an antenna 108. While a single antenna is
shown, the transmitter 100 may include multiple antennas. For
example only, the multiple antennas may be arranged in a
multiple-input multiple-output (MIMO) configuration. The baseband
processing module 102 generates baseband signals that include data
to be transmitted by the transmitter 100. The upconverter module
104 upconverts the baseband signals to radio frequency (RE)
signals. The power amplifier module 106 amplifies the RF signals
and transmits the amplified RF signals via the antenna 108.
[0005] Referring, now to FIG. 1B, an example of the transmitter 100
is shown. The baseband processing module 102 outputs an in-phase
(I) signal and a quadrature phase (Q) signal that include the data
to be transmitted by the transmitter 100. The upconverter module
104 includes low-pass filter (LPF) modules 110 and 112 to remove
high-frequency noise in the I and Q channels, respectively. The
filtered I and Q signals are input to mixers 114 and 116. The
mixers 114, 116 may be called I-channel and Q-channel mixers (or I
and Q mixers), respectively.
[0006] The I and Q mixers 114, 116 upconvert the I and Q signals
from baseband frequency to radio frequency (RF). The I and Q mixers
114, 116 are driven by clock signals having a predetermined
reference frequency. The clock signals are generated by a local
oscillator (OSC) 118, a frequency divider (DIV) 120, and a
-90.degree. phase shifter 120. A summer 122 combines upconverted RF
outputs of the I and Q mixers 114, 116 into a signal that is input
the power amplifier module 106. The power amplifier module 106
amplifies the signal and drives the antenna 108, which transmits
the signal.
SUMMARY
[0007] A system comprising a first frequency divider, a plurality
of second frequency dividers, and a control module. The first
frequency divider includes a first plurality of components and is
configured to divide an input frequency of an input signal to
generate a first signal having a first frequency and a first phase.
Each of the plurality of second frequency dividers includes a
second plurality of components and is configured to divide the
input frequency of the input signal to generate a second signal
having the first frequency and a second phase. The control module
is configured to connect the second plurality of components of one
of the second frequency dividers to the first plurality of
components of the first frequency divider.
[0008] In another feature, in response to the control module
sequentially connecting the second plurality of components of the
one of the second frequency dividers to the first plurality of
components of the first frequency divider, the second phase of the
second signal generated by the one of the second frequency dividers
matches the first phase of the first signal generated by the first
frequency divider.
[0009] In another feature, the first plurality of components of the
first frequency divider has a first area, and the second plurality
of components of each of the second frequency dividers has a second
area that is less than the first area.
[0010] In another feature, the control module is configured to
connect the second plurality of components of the one of the second
frequency dividers to the first plurality of components of the
first frequency divider via a plurality of pass transistors and by
turning on the plurality of pass transistors at a same time.
[0011] In another feature, the system further comprises a mixer
configured to upconvert a transmit signal using a clock signal,
wherein the clock signal includes the first signal generated by the
first frequency divider and the second signal generated by the one
of the second frequency dividers.
[0012] In other features, the system further comprises a first
mixer and a second mixer. The first mixer is configured to
upconvert a transmit signal using a first clock signal, where the
first clock signal includes the first signal generated by the first
frequency divider. The second mixer is configured to upconvert the
transmit signal using a second clock signal, where the second clock
signal includes the first signal generated by the first frequency
divider and the second signal generated by each of the plurality of
second frequency dividers connected to the first frequency divider.
The control module is further configured to activate the first
mixer when the transmit signal is transmitted at a first power
level and to deactivate the first mixer and activate the second
fixer when the transmit signal is transmitted at a second power
level that is greater than the first power level. The first mixer
includes components having a first area. The second mixer includes
components having a second area that is greater than the first
area. A number of the second frequency dividers connected in
parallel to the first frequency divider depends on the first and
second power levels.
[0013] In still other features, a system comprises a first
frequency divider, a second frequency divider and a control module.
The first frequency divider includes a first divider and a second
divider. The first divider includes first components and is
configured to divide an input frequency of an input signal and
generate a first signal. The second divider includes second
components and is configured to divide the first signal and
generate a second signal. The second frequency divider includes a
third divider and a fourth divider. The third divider includes
third components and is configured to divide the input frequency
and generate a third signal. The fourth divider includes fourth
components and is configured to (i) divide the third signal and
generate a fourth signal. The control module is configured to
selectively activate the first and third dividers, deactivate the
second and fourth dividers, and sequentially connect the third
components of the third divider to the first components of the
first divider, or (ii) selectively activate the first, second,
third, and fourth dividers sequentially connect the third
components of the third divider to the first components of the
first divider, and sequentially connect the fourth components of
the fourth divider to the second components of the second
divider.
[0014] In other features, the system further comprises a first
mixer and a second mixer. The first mixer includes a first
plurality of components having a first area and is configured to
upconvert a transmit signal using a first clock signal. The second
mixer includes a second plurality of components having a second
area that is greater than the first area and is configured to
upconvert the transmit signal using a second clock signal. The
control module is configured to activate the first mixer when the
transmit signal is transmitted at a first power level and to
deactivate the first mixer and activate the second mixer when the
transmit signal is transmitted at a second power level that is
greater than the first power level.
[0015] In other features, the first clock signal includes the first
signal generated by the first divider and the third signal
generated by the third divider when the transmit signal is
transmitted at the first power level in a first frequency band. The
first clock signal includes the second signal generated by the
second divider and the fourth signal generated by the fourth
divider when the transmit signal is transmitted at the first power
level in a second frequency band that is different than the first
frequency band. The second clock signal includes the first signal
generated by the first divider and the third signal generated by
the third divider when the transmit signal is transmitted at the
second power level in the first frequency band. The second clock
signal includes the second signal generated by the second divider
and the fourth signal generated by the fourth divider when the
transmit signal is transmitted at the second power level in the
second frequency hand.
[0016] In other features, the control module is configured to
activate the first and third dividers and deactivate the second and
fourth dividers when the transmit signal is transmitted in the
first frequency band and to activate the first, second, third, and
fourth dividers when the transmit signal is transmitted in the
second frequency band.
[0017] In still other features, a method comprises dividing an
input frequency of an input signal to generate a first signal
having a first frequency and a first phase using a first frequency
divider, where the first frequency divider includes a first
plurality of components. The method further comprises dividing the
input frequency of the input signal using each of a plurality of
second frequency dividers to generate a second signal having, the
first frequency and a second phase, where each of the second
frequency dividers includes a second plurality of components. The
method further comprises connecting the second plurality of
components of one of the second frequency dividers to the first
plurality of components of the first frequency divider.
[0018] In another feature, the method further comprises
sequentially connecting the plurality of second frequency dividers
in parallel to the first frequency divider, wherein in response to
sequentially connecting the plurality of second frequency dividers
in parallel to the first frequency divider, the second phase of the
second signal generated by each of the plurality of second
frequency dividers matches the first phase of the first signal
generated by the first frequency divider.
[0019] Further areas of applicability of the present disclosure
will become apparent from the detailed description, the claims and
the drawings. The detailed description and specific examples are
intended for purposes of illustration only and are not intended to
limit the scope of the disclosure.
BRIEF DESCRIPTION OF DRAWINGS
[0020] The present disclosure will become more fully understood
from the detailed description and the accompanying drawings,
wherein:
[0021] FIG. 1A is a functional block diagram of a transmitter;
[0022] FIG. 1B depicts an example of a transmitter;
[0023] FIG. 2A is a functional block diagram of a transmitter
including, a main frequency divider and a plurality of auxiliary
frequency dividers;
[0024] FIG. 2B is a functional block diagram of a frequency divider
of a transmitter;
[0025] FIG. 2C is a functional block diagram of a frequency divider
including two frequency dividers that can be used in parallel to
increase or decrease the size of the frequency divider;
[0026] FIG. 3A is functional block diagram of a transmitter
including a frequency divider and two mixers;
[0027] FIG. 3B is a simplified block diagram of the transmitter of
FIG. 3A;
[0028] FIG. 4 is a functional block diagram of the main frequency
divider of FIG. 3A;
[0029] FIG. 5 is a functional block diagram of an auxiliary
frequency divider of FIG. 3A;
[0030] FIG. 6 depicts connections between the main frequency
divider and an auxiliary frequency divider of FIG. 3A.
[0031] FIG. 7 is a flowchart of a method for connecting outputs of
main and auxiliary frequency dividers;
[0032] FIG. 8 is a flowchart of a method for connecting multiple
frequency dividers in parallel;
[0033] FIG. 9A is a functional block diagram of a receiver; and
[0034] FIG. 9B depicts an example of a receiver.
DESCRIPTION
[0035] Referring nosy to FIG. 2A, a transmitter 150 including a
frequency divider 152 is shown. The frequency divider 152 includes
a main frequency divider 154 and a plurality of auxiliary frequency
dividers e.g., a first auxiliary frequency divider 156-1, a second
auxiliary frequency divider 156-2, and so on (collectively
auxiliary dividers 156)), and a control module 158. The control
module 158 turns on the main frequency divider 154 when the
transmitter 150 is turned on. As the power requirement increases,
the control module 158 turns on one or more of the auxiliary
frequency dividers 156.
[0036] Phase noise is an important consideration in transmitter
design. Phase noise is a frequency-domain representation of rapid,
short-term, random fluctuations in a phase of a waveform caused by
time-domain instabilities (jitter). Generally, in the analog
domain, phase noise refers to phase noise of an oscillator, whereas
in the digital domain, phase noise refers to jitter of a clock.
[0037] When a transmitter is set to operate at a maximum output
power level, phase noise performance at frequencies far away from a
carrier frequency of the transmitter can adversely impact data
transmitted by the transmitter. Often, however, transmitters
operate at power levels below maximum output power levels, where
phase noise performance can be relaxed.
[0038] In most transmitters, local oscillators include a crystal
oscillator, which generates a signal at a natural frequency of the
crystal oscillator (typically few tens of a megahertz), a
Phase-Locked Loop (PLL) that generates a higher tunable frequency
(typically few gigahertz), and one or more frequency dividers
(e.g., the main frequency divider 154 and one or more of the
auxiliary frequency dividers 156). The frequency dividers generate
a clock of a desired frequency. The clock, which is typically
called LO, is then used to drive mixers (not shown).
[0039] The frequency dividers are generally used in parallel as
shown. Initially, only the main frequency divider 154 is turned on
when the transmitter 150 is turned on. When the output power
requirement of the transmitter 150 increases and the phase noise
performance starts becoming critical, one or more auxiliary
frequency dividers 156 are turned on and added in parallel to the
main frequency divider 154 by the control module 158. Thereafter,
when the output power requirement of the transmitter 150 decreases
and the phase noise performance becomes less critical, one or more
of the auxiliary frequency dividers 156 are turned off and
disconnected from the main frequency divider 154.
[0040] When the main frequency divider is turned on the initial
phase of the main frequency divider is unknown. Accordingly, when
an auxiliary frequency divider is subsequently turned on and added
in parallel to the main frequency divider the phase of the
auxiliary frequency divider may be in phase or delayed by 180
degrees relative to the phase of the main frequency divider since
it is impossible to set the initial phase of either frequency
dividers.
[0041] Frequency dividers contribute substantially to the overall
far away phase noise performances (e.g., 20-50 MHz far away from
the carrier frequency) at the maximum output power level of the
power amplifier (PA) stage of the transmitters. Phase noise
decreases as the size of components of the frequency dividers
increases. Increasing the size of the components, however, also
increases power consumption.
[0042] The present disclosure relates to a system to synchronize
the phase of each frequency divider added to the main frequency
divider to the phase of the main frequency divider. Specifically,
multiple switches are used to connect internal nodes of an
additional frequency divider to internal nodes of the main
frequency divider when the additional frequency divider is
connected in parallel to the main frequency divider. The switches
are closed simultaneously. The phase of the additional frequency
divider is synchronized to the phase of the first frequency divider
by synchronizing the operation of the switches.
[0043] Further, when multiple frequency dividers are added to the
main frequency divider, only one additional frequency divider is
connected in parallel to the main frequency divider at a time. A
plurality of frequency dividers are not connected in parallel to
the main frequency divider at the same time. For example, a first
additional frequency divider is connected to the main frequency
divider at a first time; a second additional frequency divider is
connected to the main frequency divider at a second time following
the first time, and so on. In other words, each additional
frequency divider is sequentially connected to the main frequency
divider. When any additional frequency divider is connected to the
main frequency divider, the switches that connect the internal
nodes of the additional frequency divider to the internal nodes of
the main frequency divider are closed simultaneously.
[0044] Additionally, each frequency divider connected to the main
frequency divider includes components that are smaller in size
(area) than the components of the main frequency divider. For
ample, the length of the metal-oxide semiconductor (MOS) devices
used in the main frequency divider and each additional frequency
divider is kept the same, and the width of the MOS devices used in
each additional frequency divider is less relative to the width of
the MOS devices used in the main frequency divider. Accordingly,
the components of each additional frequency divider connected to
the main frequency divider have smaller power ratings and smaller
parasitic capacitances than the components of the main frequency
divider. The sequential operation of the switches and the smaller
area of components of each added frequency divider ensure that each
added frequency divider has substantially the same phase as the
main frequency divider when each additional frequency divider is
connected to the main frequency divider in parallel. That is, the
phase of each frequency divider added to the main frequency divider
follows the phase of the main frequency divider.
[0045] Referring now to FIG. 2B, a frequency divider 200 is shown
for example only. The frequency divider 200 divides the frequency
of a clock signal CK generated by a crystal oscillator (not shown).
The frequency of the clock signal CK depends on the frequency band
in which the transmitter operates. When the transmitter can operate
in more than one frequency band, the clock signal CK can be
switched depending on the frequency band in which the transmitter
operates.
[0046] The frequency divider 200 includes a master-slave flip-flop
and four switches (SW) arranged as shown. The four switches are
clocked by the clock signal CK and by a complement of the clock
signal CK (CK_b) as shown. By dividing the clock signal CK, the
frequency divider 200 generates four output clock signals LOQ_n.
LOI_n. LOI_p, and LOQ_p (collectively I and Q channel clock
signals) that are used to drive I and Q mixers of a
transmitter.
[0047] In a frequency divider, the phase noise can be decreased by
increasing the size (area) of the components of the frequency
divider. When the size of the components is increased, however, the
power consumed by the components increases. Further, when the
transmitter is turned on (i.e., when power is supplied to the
transmitter), the frequency divider turns on, and the initial phase
of the frequency divider is unknown since states of the
master-slave flip-flops when the power is turned on are unknown.
Accordingly, when an additional frequency divider is added to the
main frequency divider in parallel, the phase of the additional
frequency divider can be different than the phase of the main
frequency divider and can have 180 degrees of phase delay and can
corrupt the LO signal.
[0048] Referring now to FIG. 2C, a frequency divider 250 includes a
main frequency divider 252, an auxiliary frequency divider 254, a
control module 256, switches 258, and switches 260. The main
frequency divider 252 includes components having a greater size
(area) than the components of the auxiliary frequency divider 254.
For example only, let 2X and X respectively denote the sizes of the
components of the first and second frequency dividers 252, 254.
Each of the first and second frequency dividers 252, 254 has the
structure of the frequency divider 200 shown in FIG. 2B.
Accordingly, each of the first and second frequency dividers 252,
254 has flip-flop internal nodes AA, BB, CC, and DD.
[0049] When the transmitter is turned on, only the main frequency
divider 252 turns on, and the main frequency divider 252 divides
the clock signal CK and generates the I and Q channel clock signals
used to drive I and Q mixers of the transmitter (e.g., mixers 114,
116 shown in FIG. 1B). In the example shown, the I and Q channel
clock signals are inverted versions of the flip-flop internal nodes
AA through DD.
[0050] When the transmitter is turned on, the auxiliary frequency
divider 254 is kept off and is not connected to the main frequency
divider 252. Specifically, when power is initially supplied to the
transmitter, the control module 256 does not turn on the switches
258 that supply the clock signals CK and CK_b to the auxiliary
frequency divider 254. Additionally, the control module 256 does
not turn on the switches 260 that connect the auxiliary frequency
divider 254 in parallel to the main frequency divider 252.
[0051] When the auxiliary frequency divider 254 is to be connected
in parallel to the main frequency divider 252, the control module
256 turns on the auxiliary frequency divider 254. Additionally, the
control module 256 turns on the switches 258, which supply the
clock signals CK and CK_b to the auxiliary frequency divider 254.
The control module 256 sequentially turns on the switches 260 to
connect the flip-flop internal nodes AA, BB, CC and DD of the
auxiliary frequency divider 254 to the corresponding flip-flop
internal nodes AA, BB, CC, and DD of the main frequency divider 2.
The switches 260 simultaneously connect the flip-flop internal
nodes AA. BB, CC, and DD of the auxiliary frequency divider 254 to
the flip-flop internal nodes AA, BB, CC, and DD of the main
frequency divider 252, respectively.
[0052] The switches 260 include pass transistors, which have a
small area (size) and a small parasitic capacitance. The pass
transistors therefore do not load the flip-flop internal nodes AA,
BB, CC, and DD of the main frequency divider 252 when connecting,
the flip-flop internal nodes AA, BB, CC, and DD of the auxiliary
frequency divider 254 to the flip-flop internal nodes AA, BB, CC,
and DD of the main frequency divider 252, respectively.
[0053] When the switches 260 connect the respective flip-flop
internal nodes of the first and second frequency dividers 252, 254
as described above, the flip-flop outputs of the auxiliary
frequency divider 254 have substantially the same phase as the
phase of the flip-flop outputs of the main frequency divider 252,
respectively. In other words, the flip-flop outputs of the main
frequency divider 252, which has larger components than the
auxiliary frequency divider 254, force the flip-flop outputs of
auxiliary frequency divider 254 to have the same phase as the phase
of the flip-flop outputs of the main frequency divider 252 when the
auxiliary frequency divider 254 is connected to the main frequency
divider 252 as described above. The phase of the flip-flop outputs
of the auxiliary frequency divider 254 follows the phase of the
flip-flop outputs of the main frequency divider 252 regardless of
the order in which the main frequency divider 252 and the auxiliary
frequency divider 254 are turned on.
[0054] In some implementations, the main frequency divider 252 may
include components having a smaller size (area) than the components
of the auxiliary frequency divider 254. For example only, suppose
that X and 2X respectively denote the sizes of the components of
the first and second frequency dividers 252, 254. Suppose further
that the main frequency divider 252 is initially turned on when the
power is supplied to the transmitter and that the auxiliary
frequency divider 254 is added as described above.
[0055] In this example, when the switches 260 connect the flip-flop
internal nodes of the auxiliary frequency divider 254 to the
respective flip-flop internal nodes of the main frequency divider
252 as described above, the flip-flop outputs of the main frequency
divider 252 have substantially the same phase as the phase of the
flip-flop outputs of the auxiliary frequency divider 254. In other
words, the flip-flop outputs of the auxiliary frequency divider
254, which has larger components than the main frequency divider
252, force the flip-flop outputs of main frequency divider 252 to
have the same phase as the phase of the flip-flop outputs of the
auxiliary frequency divider 254 when the auxiliary frequency
divider 254 is connected to the main frequency divider 252 as
described above.
[0056] In some applications, more than two frequency dividers may
be used in parallel. When the transmitter is turned on, a main
frequency divider turns on. Subsequently, as power requirement of
the transmitter increases, one or more frequency dividers may be
turned on and connected in parallel to the main frequency divider.
Each additional frequency divider has a smaller area than the main
frequency divider and is turned on sequentially. The additional
frequency dividers may be disconnected from the main frequency
divider as the power requirement of the transmitter decreases.
Components of the additional frequency dividers have smaller areas
(and therefore smaller power ratings and parasitic capacitances)
than the components of the main frequency divider. For example
only, the main frequency divider may have components having an area
of 2X, and each of the additional frequency dividers may have
components having an area of X.
[0057] Further, the transmitter may include two mixers. A first
mixer is used when the transmitter operates in a low-power mode and
is called a low-power mixer. A second mixer is used when the
transmitter operates in a high-power mode and is called a
high-power mixer. The area (size) of the components of the
low-power mixer is less than the area of the components of the
high-power mixer.
[0058] Referring now to FIG. 3A, a transmitter 300 includes a
frequency divider 302, a first mixer 304, and a second mixer 306.
Throughout the present disclosure (e.g., iii FIGS. 2A, 2C, and
3A-6), only clock inputs to the mixers are shown, and baseband
inputs to the mixers are omitted for simplicity of illustration.
The first mixer 304 is a low-power mixer that is used when the
transmitter 300 operates in a low-power mode. The second mixer 306
is a high-power mixer that is used when the transmitter 300
operates in a high-power mode. The area (size) of the components of
the first mixer 304 is less than the area of the components of the
second mixer 306. For example only, the area of the components of
the first mixer 304 may be 3X, and the area of the components of
the second mixer 306 may be 20.
[0059] The frequency divider 302 includes a main frequency divider
308; a plurality of auxiliary frequency dividers 310-1, 310-2, . .
. , and 310-N, where N is an integer greater than 1 (collectively
auxiliary frequency dividers 310); switches 312-1, 312-2, . . . ,
and 312-N (collectively switches 312); and a control module 314.
The main frequency) divider 308 includes components having area
greater (e.g., 2X) than the components of each of the auxiliary
frequency dividers 310 (e.g., X). The components of each of the
auxiliary frequency) dividers 310 have the same area (e.g., X).
[0060] In some implementations, components of each of the auxiliary
frequency dividers 310 have different area. For example, the
components of a first one of the auxiliary frequency dividers 310
may have a different area than the components of a second one of
the auxiliary frequency dividers 310. The area of the components of
each of the first and second ones of the auxiliary frequency
dividers 310, how ever, should be less than the area of the
components of the main frequency divider 308. For example only, the
area of the components of the main frequency divider 308 may be 4X.
The area of the components of the first one of the auxiliary
frequency dividers 310 may be X. The area of the components of the
second one of the auxiliary frequency dividers 310 may be 2X.
[0061] The control module 314 controls the switches 312 and the
switch 316. Additionally, the control module 314 turns on and off
the auxiliary frequency dividers 310 and the first and second
mixers 304, 306. As used herein, activating or turning on a device
can include supplying power and/or clock to the device, and
deactivating or turning off a device can include disconnecting
power supply and/or clock from the device. A device is said to be
in an active mode when turned on and in an inactive mode (also
called a power-save mode or sleep mode) when turned off.
[0062] When the transmitter 300 is turned on, the main frequency
divider 308 turns on. The control module 314 turns on the first
mixer 304 and does not turn on the frequency dividers 310 and the
second mixer 306. Accordingly, at power on, the transmitter 300
operates in the low-power mode. The main frequency divider 308
divides the clock signal CK and generates the I and Q channel clock
signals. The first mixer 304 upconverts the baseband signals using
the I and Q channel clock signals.
[0063] For simplicity of illustration, only CK is used to show the
clock signal. It should be understood that the clock signal
includes the clock signals CK and CK-b as shown in FIGS. 2A and 2B.
Further, it should be understood that different clock signals may
be selected depending on the frequency band in which the
transmitter 300 operates (e.g., 2G, 3G, etc.).
[0064] Subsequently, when more power is needed, the control module
314 turns off the first mixer 304 and turns on the second mixer 306
using the switch 316. Additionally, using the switches 312, the
control module 314 turns on one or more of the auxiliary frequency
dividers 310 and sequentially connects the one or more auxiliary
frequency dividers 310 in parallel to the main frequency divider
308 as described above. For example, switches 312-1 connect the
first auxiliary frequency divider 310-1 to the main frequency
divider 308 at a first time; switches 312-2 connect the second
auxiliary frequency divider 310-2 to the main frequency divider 308
at a second time; and so on. Each of the switches 312-1, 312-2,
etc, includes a set of switches that simultaneously connect the
internal nodes of a selected one of the auxiliary frequency
dividers 310 to the internal nodes of the main frequency divider
308 as described above when the selected one of the auxiliary
frequency dividers 310 is connected to the main frequency divider
308 in parallel. This is shown and described in further detail with
reference to FIG. 6 below.
[0065] The control module 314 supplies the clock signal CK to the
one or more of the auxiliary frequency dividers 310 that are turned
on. The transmitter 300 now operates in the high-power mode. The
main frequency divider 308 and the one of more of the auxiliary
frequency dividers 310 that are sequentially connected to the main
frequency divider 308 divide the clock signal CK and generate the I
and Q channel clock signals. The second mixer 306 upconverts the
baseband signals using the I and Q channel clock signals generated
by the main frequency divider 308 and the one or more of the
auxiliary frequency dividers 310. The sequential operation of the
switches 312 and the smaller area of components of the auxiliary
frequency dividers 310 ensure that each added auxiliary frequency
divider 310 has substantially the same phase as the main frequency
divider 308 when each auxiliary frequency divider 310 is connected
to the main frequency divider 308 in parallel.
[0066] When the power requirement of the transmitter 300 decreases,
depending on the power requirement of the transmitter 300, the
control module 314 disconnects and turns off (i.e., deactivates)
one or more of the auxiliary frequency dividers 310 from the main
frequency divider 308. For example only, using the switches 312,
the control module 314 may sequentially disconnect one or more of
the auxiliary frequency dividers 310 from the main frequency
divider 308 in an opposite order than the order in which the one or
more of the auxiliary frequency dividers 310 were connected to the
main frequency divider 308 (e.g., divider connected last is
disconnected first etc.).
[0067] The control module 314 may keep the second mixer 306 turned
on until at least one of the auxiliary frequency dividers 310 is
connected to the main frequency divider 308. When a last one of the
auxiliary frequency dividers 310 is disconnected from the main
frequency divider 308, the control module 314 turns on the first
mixer 304 and turns off the second mixer 06. The transmitter 300
now operates in the low-power mode.
[0068] Referring now to FIG. 3B a simplified block diagram of the
transmitter 300 is shown. As described above, the main frequency
divider 308 drives the first mixer 304 when the transmitter 300
operates in the low-power mode and drives the second mixer 306 when
the transmitter 300 operates in the high-power mode. Accordingly,
the main frequency divider 308 outputs two sets of I and Q channel
clock signals. A first set of I and Q channel clock signals drives
the first mixer 304 when the transmitter 300 operates in the
low-power ode. A second set of I and Q channel clock signals drives
the second 306 when the transmitter 300 operates in the high-power
mode. The second set of I and Q channel clock signals are combined
shorted) with respective I and Q channel clock signals generated by
the one or more of the auxiliary frequency dividers 310 when the
one or more of the auxiliary frequency dividers 310 are connected
in parallel to the main frequency divider 308. The second set of I
and Q channel clock signals, combined with the I and Q channel
clock signals generated by the one or more of the auxiliary
frequency dividers 310, drive the second mixer 306 when the
transmitter 300 operates in the high-power mode.
[0069] Referring now to FIG. 4 the main frequency divider 308 is
shown in detail. The main frequency divider 308 includes a first
divider 350, a second divider 352, a first buffer 354, a second
buffer 356, a third buffer 358, and a selection module 360. Each of
the first and second dividers 350, 352 has the structure of the
frequency divider 200 shown in FIG. 2B.
[0070] The transmitter 300 can operate in a high-frequency band or
a low-frequency band. The control module 314 detects whether the
transmitter 300 operates in the high-frequency band or the
low-frequency band. The selection module 360 communicates with the
control module 314. When the transmitter 300 operates in the
low-frequency band, the selection module 360 selects only the first
divider 350 to divide the clock signal CK (e.g., to divide by 2).
When the transmitter 300 operates in the high-frequency band, the
selection module 360 selects the first and second dividers 350, 352
to divide the clock signal CK to divide by 4).
[0071] In either frequency band, the main frequency divider 308
outputs the first and second sets of I and Q channel clock signals
to the first and second mixers 304, 306, respectively. The
selection module 360 selects/deselects the second divider 352
depending on the frequency band in which the transmitter 300
operates. In either frequency band, the selection module 360
selects the first second and third buffers 354, 356, 358 to output
the first and second sets of I and Q channel clock signals to the
first and second mixers 304, 306, respectively. The control module
314 operates the switches 312 to connect the flip-flop internal
nodes of the first and second dividers 350, 352 to corresponding
flip-flop internal nodes of one or more of the auxiliary frequency
dividers 310. The control module 314 activates/deactivates the
first and second mixers 304, 306 depending on whether the
transmitter 300 operates in the low-power or high-power mode.
[0072] Referring now to FIG. 5, one of the auxiliary frequency
dividers 310 (e.g., the first auxiliary frequency divider 310-1) is
shown in detail. The first auxiliary frequency) divider 310-1
includes a first divider 380, a second divider 382, a first buffer
384, a second buffer 386, and a selection module 388. Each of the
first and second dividers 380, 382 has the structure of the
frequency) divider 200 shown in FIG. 2B.
[0073] The selection module 388 communicates with the control
module 314. When the transmitter 300 operates in the low-frequency
band, the selection module 388 selects only the first divider 380
to divide the clock signal CK (e.g., to divide by 2). When the
transmitter 300 operates in the high-frequency band, the selection
module 388 selects the first and second dividers 380, 382 to divide
the clock signal CK (e.g., to divide 4).
[0074] In either frequency band, the first auxiliary frequency
divider 310-1 outputs the I and Q channel clock signals to the
second mixer 306. The selection module 388 selects/deselects the
second divider 382 depending on the frequency band in which the
transmitter 300 operates. In either frequency hand, the selection
module 388 selects the first and second buffers 384, 386 to output
the I and Q channel clock signals to the second mixer 306. The
control module 314 operates the switches 312 to connect the
flip-flop internal nodes of the first and second dividers 380, 382
to corresponding flip-flop internal nodes of the main frequency
divider 308. The control module 314 activates/deactivates the first
and second mixers 304, 306 depending on whether the transmitter 300
operates in the low-power or high-power mode.
[0075] Referring now to FIG. 6, examples of connections between the
first and second dividers of the main frequency divider 308 and one
of the auxiliary frequency dividers 310 (e.g., the first auxiliary
frequency divider 310-1) are shown in detail. The flip-flop
internal nodes AA, BB, CC, and DD of the first divider 350 are
simultaneously connected to the respective flip-flop internal nodes
AA, BB, CC, and DD of the first divider 380 via the switches 312-1a
when the first auxiliary frequency divider 310-1 is connected in
parallel to the main frequency divider 308. The flip-flop internal
nodes AA, BB, CC, and DD of the second divider 352 are
simultaneously connected to the respective flip-flop internal nodes
AA, BB, CC, and DD of the second divider 382 via the switches
312-1b when the first auxiliary frequency divider 310-1 is
connected in parallel to the main frequency divider 308.
[0076] In the main frequency divider 308, the first divider 350
receives the clock signals CK and CK_b. The first divider 350
divides the clock signals CK and CK_b and generates the divided
signals LOI_p, LOQ_p, LOI_n, and LOQ_n. The LOI_p and LOI_n outputs
of the first divider 350 are input to the inputs CK and CK_b of the
second divider 352, respectively. The second divider 352 divides
the LOI_p and LOI_n outputs of the first divider 350 and generates
the divided signals LOI_p, LOQ_p, LOI_n, and LOQ_n.
[0077] In the first auxiliary frequency divider 310-1 the first
divider 380 receives the clock signals CK and CK_b. The first
divider 380 divides the clock signals CK and CK_b and generates the
divided signals LOI_, LOQ_p, LOI_n, and LOQ_n. The LOI_p and LOI_n
outputs of the first divider 380 are input to the inputs CK and
CK_b of the second divider 382, respectively. The second divider
382 divides the LOI_p and LOI_n outputs of the first divider 350
and generates the divided signals LOI_, LOQ_p, LOI_n, and
LOQ_n.
[0078] When the first auxiliary frequency divider 310-1 is
connected in parallel to the main frequency divider 308 and when
the transmitter 300 operates in the first frequency hand, the I and
Q channel clock signals are generated as follows: Only the first
dividers 350, 380 of the main and first auxiliary frequency
dividers 308 and 310-1 are selected. The signals LOI_p LOQ_p,
LOI_n, and LOQ_ generated by the first dividers 350, 380 of the
main and first auxiliary frequency dividers 308 and 310-1 are
combined. The combined signals LOI_p, LOQ_p, LOI_n, and LOQ_n are
used to drive the first and/or second mixers 304, 306. The
procedure is repeated when each one of the auxiliary frequency
dividers 310 is connected in parallel to the main frequency divider
308.
[0079] When the first auxiliary frequency divider 310-1 is
connected in parallel to the main frequency divider 308 and when
the transmitter 300 operates in the second frequency band, the I
and Q channel clock signals are generated as follows: The first and
second dividers 350, 380, 352, 382 of the main and first auxiliary
frequency dividers 308 and 310-1 are selected. The signals LOI_p,
LOQ_p, LOI_n, and LOQ_n generated by the second dividers 352, 382
of the main and first auxiliary frequency dividers 308 and 310-1
are combined. The combined signals LOI_p, LOQ_p, LOI_n, and LOQ_n
are used to drive the first and/or second mixers 304, 306. The
procedure is repeated when each one of the auxiliary frequency
dividers 310 is connected in parallel to the main frequency divider
308.
[0080] Referring now to FIG. 7, an example of a method 400 for
operating a transmitter is shown. Control begins at 402. At 404
control turns on only the frequency divider having a component size
2X and does not turn on any frequency dividers having a component
size 1X, for example. At 406, control drives a mixer using clock
signals generated by the 2X frequency divider. At 408 control
determines if high transmit power is needed. Control ends at 410 if
high transmit power is not needed.
[0081] At 412, if high transmit power is needed, control turns on a
first 1X frequency divider and sequentially connects flip-flop
internal nodes AA, BB, CC, and DD of the 2X frequency divider to
flip-flop internal nodes AA, BB, CC, and DD of the first 1X
frequency divider. Control combines the clock signals generated by
the 2X frequency divider and the clock signals generated by the
first 1X frequency divider, and control drives the mixer using, the
combined clock signals.
[0082] At 414, control determines if additional transmit power is
needed. Control ends at 410 if additional transmit power is not
needed. At 416, if additional transmit power is needed, control
determines if any additional 1X frequency dividers can be used.
Control ends at 410 if no additional 1X frequency dividers can be
used. At 418, if any additional 1X frequency dividers can be used,
control turns on a next 1X frequency) divider and sequentially
connects flip-flop internal nodes AA, BB, CC, and DD of the
2.times. frequency) divider to flip-flop internal nodes AA, BB, CC
and DD of the next 1.times. frequency) divider. Control combines
the clock signals generated by the 2X frequency divider, the first
1X frequency divider, and the next 1X frequency) divider and drives
the mixer using, the combined clock signals. Control returns to
414.
[0083] Referring, now to FIG. 8, an example of a method 450 for
operating a transmitter is shown. Control begins at 452. At 454,
control turns on only the frequency divider having a component size
2X and does not turn on any frequency dividers having a component
size 1X, for example. At 456, control turns on and drives only a
low-power mixer (e.g., having component size 1X) using, clock
signals generated by the 2X frequency divider. At 458, control
determines if high transmit power is needed. Control ends at 460 if
high transmit power is not needed.
[0084] At 462, if high transmit power is needed, control turns on
and connects a first 1X divider in parallel to the 2X divider,
turns on a high-power mixer, hay component size 10X), and turns off
the low-power mixer. At 464, control combines the clock signals
generated by the 2X frequency divider and the clock signals
generated by the first 1X frequency divider, and control drives the
high-power mixer using the combined clock signals.
[0085] At 466, control determines if additional transmit power is
needed. Control ends at 460 if additional transmit power is not
needed. At 468, if additional transmit power is needed, control
determines if any additional 1X frequency dividers can be used.
Control ends at 460 if no additional 1X frequency dividers can be
used. At 470, if any additional 1X frequency dividers can be used,
control turns on and connects a next 1X divider in parallel to the
2X divider. Control combines the clock signals the clock signals
generated by the 2X frequency divider, the first 1X frequency
divider, and the next 1X frequency divider and drives the
high-power mixer using the combined clock signals. Control returns
to 466.
[0086] Referring now to FIGS. 9A and 9B, the teachings of the
present disclosure can be applied to frequency dividers used in
receivers as well. In FIG. 9A, a receiver 500 includes an antenna
502, a front-end processing module 504, a downconverter module 506,
and a baseband processing module 508. While a single antenna is
shown, the receiver 500 may include multiple antennas. For example
only, the multiple antennas may be arranged in a multiple-input
multiple-output (IMO) configuration. The front-end processing
module 504 processes (e.g., amplifies, filters, demodulates, etc.)
signals received via the antenna 502. The downconverter module 506
downconverts the signals from radio frequency (RF) to baseband
frequency. The baseband processing module 508 performs further
processing.
[0087] In FIG. 9B, the downconverter module 506 includes
downconversion mixers 510, 512; a local oscillator (OSC) 514; a
frequency divider (DIV) 516; and a -90.degree. phase shifter 518.
The downconversion mixers 510, 512 downconvert the output of the
front-end processing module 504 from RF to baseband frequency and
generate I and Q channel baseband signals. The downconversion
mixers 510, 512 are driven by clock signals having a predetermined
reference frequency. The clock signals are generated by the local
oscillator (OSC) 514, the frequency divider (DIV) 516, and the
-90.degree. phase shifter 518. The teachings disclosed in reference
to FIGS. 2A-8 can be implemented in the downconverter module 506 of
the receiver 500.
[0088] The modular frequency dividers disclosed herein can be
combined with modular mixer configurations. For example, just as a
larger frequency divides (e.g., the main frequency divider 308)
achieves better phase noise than a smaller frequency divider (e.g.,
one of the auxiliary frequency dividers 310), a larger mixer (e.g.,
the second mixer 306) can yield larger output power in a
transmitter and higher linearity in a transmitter and a receiver.
The modular frequency dividers can be combined with parallel
mixers, which may differ in size, as follows.
[0089] In a transmitter (e.g., the transmitter 300), when multiple
frequency dividers are used to achieve low phase noise, a large
mixer (e.g., the second mixer 306) may be used for high output
power and high linearity. As phase noise requirements are reduced
as output power is reduced, linearity requirements may also reduce
and a smaller mixer (the first mixer 304) may be used with a
smaller frequency divider (e.g., one of the auxiliary frequency
dividers 310) to save current in both the frequency dividers and
the mixer at lower output power levels.
[0090] For example, in FIG. 3A, when the power requirement of the
transmitter 300 decreases, depending on the power requirement of
the transmitter 300, the control module 314 disconnects and turns
off (i.e., deactivates) one or more of the auxiliary frequency
dividers 310 from the main frequency divider 308. For example only,
using the switches 312, the control module 314 may sequentially
disconnect one or more of the auxiliary frequency dividers 310 from
the main frequency divider 308. Additionally, when the power
requirement of the transmitter 300 decreases to less than or equal
to a predetermined power level, the control module 314 may turn on
the first mixer 304 and turn off the second mixer 306 while at
least one of the auxiliary frequency dividers 310 is still
connected to the main frequency divider 308. The transmitter 300
now operates in the low-power mode.
[0091] In a receiver (e.g., the receiver 500), when multiple
frequency dividers are used to achieve low phase noise a larger
mixer (e.g., the second mixer 306) may be used for high linearity.
As phase noise and linearity requirements are reduced as received
power is increased, a smaller mixer (e.g., the first mixer 304) may
be used with a smaller frequency divider (e.g., one of the
auxiliary frequency dividers 310) to save current in both the
frequency) dividers and the mixer at higher received power
levels.
[0092] The foregoing description is merely illustrative in nature
and is in no way) intended to limit the disclosure, its
application, or uses. The broad teachings of the disclosure can be
implemented in a variety of forms. Therefore, while this disclosure
includes particular examples, the true scope of the disclosure
should not be so limited since other modifications will become
apparent upon a study of the drawings, the specification, and the
following claims. For purposes of clarity, the same reference
numbers will be used in the drawings to identify similar elements.
As used herein, the phrase at least one of A, B, and C should be
construed to mean a logical (A or B or C), using a non-exclusive
logical OR. It should be understood that steps within a method may
be executed in different order without altering the principles of
the present disclosure.
[0093] As used herein, the term module may refer to be part oil or
include an Application Specific Integrated Circuit (ASIC); an
electronic circuit; a combinational logic circuit; a field
programmable gate array (FPGA); a processor (shared, dedicated, or
group) that executes code; other suitable components that provide
the described functionality; or a combination of some or all of the
above, such as in a system-on-chip. The term module may include
memory (shared, dedicated, or group) that stores code executed by
processor.
[0094] The term code, as used above, may include software,
firmware, and/or microcode, and may refer to programs, routines,
functions, classes, and/or objects. The term shared, as used above,
means that some or all code from multiple modules may be executed
using a single (shared) processor. In addition, some or all code
from multiple modules may be stored by a single (shared) memory.
The term group, as used above, means that some or all code from a
single module may be executed using a group of processors. In
addition, some or all code from a single module may be stored
using, a group of memories.
[0095] The apparatuses and methods described herein may be
implemented by one or more computer programs executed by one or
more processors. The computer programs include processor-executable
instructions that are stored on a non-transitory tangible computer
readable medium. The computer programs may also include stored
data. Non-limiting, examples of the non-transitory tangible
computer readable medium are nonvolatile memory, magnetic storage,
and optical storage.
* * * * *