U.S. patent application number 13/229347 was filed with the patent office on 2012-01-05 for hdp-cvd system.
This patent application is currently assigned to MACRONIX INTERNATIONAL CO., LTD.. Invention is credited to Kuang-Chao Chen, Shing-Ann Luo, Tuung Luoh, Chin-Ta Su, Ta-Hung Yang.
Application Number | 20120000423 13/229347 |
Document ID | / |
Family ID | 41681559 |
Filed Date | 2012-01-05 |
United States Patent
Application |
20120000423 |
Kind Code |
A1 |
Luoh; Tuung ; et
al. |
January 5, 2012 |
HDP-CVD SYSTEM
Abstract
An HDP-CVD system is described, including an HDP-CVD chamber for
depositing a material on a wafer, and a pre-heating chamber
disposed outside of the HDP-CVD chamber to pre-heat the wafer,
before the wafer is loaded in the HDP-CVD chamber, to a temperature
higher than room temperature and required in the deposition step to
be conducted in the HDP-CVD chamber. The pre-heating chamber is
equipped with a heating lamp for the pre-heating. The wafer has
been formed with a trench before being pre-heated.
Inventors: |
Luoh; Tuung; (Hsinchu,
TW) ; Su; Chin-Ta; (Hsinchu, TW) ; Yang;
Ta-Hung; (Hsinchu, TW) ; Chen; Kuang-Chao;
(Hsinchu, TW) ; Luo; Shing-Ann; (Hsinchu,
TW) |
Assignee: |
MACRONIX INTERNATIONAL CO.,
LTD.
Hsinchu
TW
|
Family ID: |
41681559 |
Appl. No.: |
13/229347 |
Filed: |
September 9, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12193442 |
Aug 18, 2008 |
8034691 |
|
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13229347 |
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Current U.S.
Class: |
118/719 |
Current CPC
Class: |
H01L 21/02274 20130101;
H01L 21/02164 20130101; H01L 21/02304 20130101; H01L 21/31608
20130101; C23C 16/0209 20130101; H01L 21/76224 20130101; C23C
16/401 20130101; C23C 16/045 20130101 |
Class at
Publication: |
118/719 |
International
Class: |
C23C 16/50 20060101
C23C016/50 |
Claims
1. An HDP-CVD system, comprising: an HDP-CVD chamber for depositing
a material on a wafer; and a pre-heating chamber disposed outside
of the HDP-CVD chamber to pre-heat the wafer, before the wafer is
loaded into the HDP-CVD chamber, to a temperature higher than room
temperature and required in an deposition step to be conducted in
the HDP-CVD chamber, wherein the pre-heating chamber is equipped
with a heating lamp for the pre-heating, and the wafer has been
formed with a trench before being pre-heated.
2. The HDP-CVD system of claim 1, wherein the pre-heating chamber
and the HDP-CVD chamber are integrated in a cluster tool.
3. The HDP-CVD system of claim 1, wherein the pre-heating chamber
is capable of pre-heating only one wafer each time.
4. The HDP-CVD system of claim 1, wherein the pre-heating chamber
is capable of pre-heating two or more wafers simultaneously.
5. The HDP-CVD system of claim 1, wherein the material deposited is
an insulating material.
6. The HDP-CVD system of claim 5, wherein the insulating material
is silicon oxide.
7. The HDP-CVD system of claim 6, wherein the temperature to which
the wafer is pre-heated is between 300.degree. C. and 800.degree.
C.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional application of and claims
priority benefit of U.S. application Ser. No. 12/193,442 filed on
Aug. 18, 2008 and now allowed. The entirety of the above-mentioned
patent application is hereby incorporated by reference herein and
made a part of this specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] This invention relates to a semiconductor process, and more
particularly relates to a high-density-plasma CVD (HDP-CVD)
process, to a filling-in process utilizing HDP-CVD, and to an
HDP-CVD system applicable to the HDP-CVD process.
[0004] 2. Description of Related Art
[0005] As the linewidth of integrated circuit (IC) fabricating
process is much reduced, the HDP-CVD technique is widely used in
depositions of various materials, especially insulating materials,
due to its gap-filling capability. An HDP-CVD process has both a
deposition effect and an etching effect, wherein the etching effect
is largest at the gap corners so that the material is well filled
in the gaps.
[0006] Moreover, to improve the quality of the deposited film, a
wafer is usually pre-heated in-situ in the HDP-CVD chamber before
the deposition is started. However, since plasma is generated in
the pre-heating step in the HDP-CVD chamber, the wafer surface is
easily damaged by the ion bombardment from the plasma.
SUMMARY OF THE INVENTION
[0007] Accordingly, this invention provides an HDP-CVD process that
can improve the quality of the material deposited without damaging
the wafer surface.
[0008] This invention also provides a filling-in process utilizing
HDP-CVD, which can also improve the quality of the deposited
material without damaging the wafer surface.
[0009] This invention also provides an HDP-CVD system applicable to
an HDP-CVD process of this invention.
[0010] The HDP-CVD process of this invention includes a deposition
step conducted in an HDP-CVD chamber and a pre-heating step that is
conducted outside of the HDP-CVD chamber before the deposition step
and pre-heats a wafer to a temperature higher than room temperature
and required in the deposition step.
[0011] In an embodiment, the wafer is pre-heated in a pre-heating
chamber, possibly together with at least one other wafer.
[0012] The filling-in process of this invention is described as
follows. A liner layer is formed on a wafer having recesses
thereon. An HDP-CVD process is then performed to the wafer,
including a deposition step conducted in an HDP-CVD chamber and a
pre-heating step conducted in the HDP-CVD chamber before the
deposition step to pre-heat the wafer to a temperature higher than
room temperature and required in the deposition step. The liner
layer is formed outside of the HDP-CVD chamber.
[0013] The HDP-CVD system of this invention includes an HDP-CVD
chamber for depositing a material on a wafer and pre-heating means
outside of the HDP-CVD chamber. The pre-heating means is for
pre-heating the wafer, before the wafer is loaded into the chamber,
to a temperature higher than room temperature and required in an
HDP-CVD process to be conducted in the HDP-CVD chamber.
[0014] In an embodiment, the pre-heating means is a pre-heating
chamber, which may be one capable of pre-heating only one wafer
each time or one capable of pre-heating two or more wafers
simultaneously.
[0015] Since the wafer is pre-heated before being subjected to
HDP-CVD, the film quality is improved. Meanwhile, since the wafer
is pre-heated outside of the HDP-CVD chamber or is formed with a
liner layer thereon before the pre-heating step conducted in the
HDP-CVD chamber, device damage due to plasma ion bombardment is
prevented. Moreover, in an embodiment where the wafer is pre-heated
outside of the HDP-CVD chamber together with at least one other
wafer, not only plasma damage is prevented in the pre-heating step
of the HDP-CVD process, but also the time required for separately
pre-heating the wafers in the HDP-CVD chamber in the prior art can
be saved so that the wafer-per-hour (WPH) value is increased.
[0016] In order to make the aforementioned and other objects,
features and advantages of the present invention comprehensible, a
preferred embodiment accompanied with figures is described in
detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1(a) illustrates an HDP-CVD system according to a first
embodiment of this invention and FIG. 1(b) a cluster tool
incorporating the HDP-CVD system.
[0018] FIGS. 2A-2C illustrate an exemplary application of an
HDP-CVD process of this invention to a shallow trench isolation
(STI) process according to an example of the first embodiment of
this invention.
[0019] FIGS. 3A-3C illustrate an exemplary application of an
HDP-CVD process of this invention to an inter-layer dielectric
(ILD) process according to another example of the first embodiment
of this invention.
[0020] FIG. 4(a) illustrates a system for conducting a filling-in
process according to a second embodiment of this invention and FIG.
4(b) a cluster tool including the system.
[0021] FIGS. 5A-5C illustrate an exemplary application of a
filling-in process of this invention to a shallow trench isolation
(STI) process according to an example of the second embodiment of
this invention.
[0022] FIGS. 6A-6C illustrate an exemplary application of a
filling-in process of this invention to an inter-layer dielectric
(ILD) process according to another example of the second embodiment
of this invention.
DESCRIPTION OF EMBODIMENTS
[0023] FIG. 1(a) illustrates an HDP-CVD system according to the
first embodiment of this invention and FIG. 1(b) a cluster tool
incorporating the HDP-CVD system.
[0024] Referring to FIG. 1(a), the HDP-CVD system includes an
HDP-CVD chamber 100 for conducting a deposition step that deposits
a material, such as an insulating material like silicon oxide, on a
wafer, a pre-heating chamber 102 as pre-heating means for
conducting a pre-heating step outside of the HDP-CVD chamber 100,
and wafer transfer means 104. The pre-heating chamber 102 is for
pre-heating the wafer, before the wafer is loaded into the HDP-CVD
chamber 100, to a temperature higher than room temperature and
required in the deposition step to be conducted in the chamber
100.
[0025] The pre-heating chamber 102 may be equipped with a heating
plate 106 or a heating lamp 108 for pre-heating the wafer, and may
have a capacity of only one wafer 10 or a capacity allowing two or
more wafers 10 of the same lot to be pre-heated therein
simultaneously. For example, when the pre-heating chamber 102 allow
N wafers to be pre-heated therein at the same time and the
pre-heating of each wafer takes M minutes, about (N-1).times.M
minutes can be saved as compared with the prior art where each
wafer is pre-heated in the HDP-CVD chamber for M minutes. In
addition, the wafer transfer means 104 is usually a robot.
[0026] The material of the heating plate 106 may be a ceramic
material selected from the group consisting of aluminum nitride
(AlN), Si.sub.3N.sub.4 and Al.sub.2O.sub.3. The heating lamp 108 is
often an IR lamp that provides a clean heat source not contacting
the wafer. For example, a quartz halogen lamp can reach 90% of the
full operating temperature within 3 seconds from a cold start and
cool down instantly in response to power control signals, wherein
the radiant energy lowers to 10% at 5 seconds after the power is
disconnected. The lamp power and heating time are two critical
parameters in the recipe. The power must be high enough to heat the
wafer to the target temperature, but must not be too high for rapid
heating may alter electrical characteristics of existing films. A
common recipe used in the fab where this study was conducted heated
the wafer at 350-600.degree. C.
[0027] Referring to FIG. 1(b), the HDP-CVD chamber 100 and the
pre-heating chamber 102 may be integrated in a cluster tool 110
while the wafer transfer means 104 placed in a loading room 112 of
the cluster tool 110. Thus, a wafer 10 can be prevented from
contacting the outer atmosphere during its transfer and is
protected from contamination and/or oxidation thereby.
[0028] FIGS. 2A-2C illustrate an exemplary application of an
HDP-CVD process of this invention to an STI process according to an
example of the first embodiment.
[0029] Referring to FIG. 2A, a wafer 200 formed with a mask layer
220 thereon and with trenches 230 of an STI structure therein is
loaded into the pre-heating chamber 102 and subjected to
pre-heating 20/20' in the pre-heating step. The trenches 230 were
previously defined with the mask layer 220 as a mask, the mask
layer 220 may include silicon nitride, and a pad oxide layer 210
may be formed on the wafer 200 before the mask layer 220 is formed.
In the pre-heating chamber 102, the wafer 200 may be subjected to
pre-heating 20 from above or pre-heating 20' from under, which may
be applied by a heating lamp or a heating plate described
above.
[0030] In the pre-heating step, the wafer 200 is pre-heated to have
a temperature higher than room temperature and required in the
deposition step to be conducted in the HDP-CVD chamber 100. For
example, when the insulating material to be deposited as the STI
material is silicon oxide, the temperature to which the wafer 200
is pre-heated is usually between 300.degree. C. and 800.degree. C.
The pre-heating chamber 102 may have a capacity of only one wafer
or a capacity of two or more wafers. With a pre-heating chamber 102
having a capacity of two or more wafers, it is possible to pre-heat
the wafer 200 together with at least one other wafer simultaneously
to reduce the pre-heating time.
[0031] Referring to FIGS. 2B and 2C, after the wafer 200 is
pre-heated to a required temperature, it is transferred into the
HDP-CVD chamber 100, in which a deposition step is conducted to
deposit an insulating layer 250 on the wafer 200 filling up the
trenches 230. In some cases, a liner layer 240 is formed on the
wafer 200 in an initial deposition stage of the deposition step
before the main deposition stage of the same, as shown in FIG. 2B,
wherein the etching rate in the initial deposition stage is lower
than that in the main deposition stage so that the surface of the
wafer 200 is further prevented from plasma damage. As silicon oxide
is to be deposited, the reaction gas may include SiH.sub.4, O.sub.2
and Ar, and the temperature to which the wafer 200 is pre-heated is
usually 300.degree.-800.degree. C., preferably 350-500.degree. C.
and particularly preferably 400-450.degree. C.
[0032] FIGS. 3A-3C illustrate an exemplary application of an
HDP-CVD process of this invention to an ILD process according to
another example of the first embodiment.
[0033] Referring to FIG. 3A, a wafer 300 formed with conductive
lines 310 thereon is loaded in the pre-heating chamber 102 and
subjected to pre-heating 20/20' in the pre-heating step, wherein
the trenches 320 are present between the conductive lines 310. The
conductive lines 310 may include a metal. In the pre-heating
chamber 102, the wafer 300 may be subjected to pre-heating 20 from
above or pre-heating 20' from under, which may applied by a heating
lamp or a heating plate mentioned above.
[0034] The wafer 300 is pre-heated to have a temperature higher
than room temperature and is required in the deposition step to be
conducted in the HDP-CVD chamber 100. For example, when the
conductive lines 310 include metal and the insulating material to
be deposited as an ILD material is SiO, the temperature to which
the wafer 300 is pre-heated is 300-500.degree. C. Moreover, the
pre-heating chamber 102 may have a capacity of only one wafer or a
capacity of two or more wafers. By using a pre-heating chamber 102
with a capacity of two or more wafers, it is possible to pre-heat
the wafer 300 together with at least one other wafer simultaneously
to save the pre-heating time.
[0035] Referring to FIGS. 3B and 3C, after the wafer 300 is
pre-heated to a required temperature, it is transferred into the
HDP-CVD chamber 100, in which a deposition step is conducted to
deposit an insulating layer 350 on the wafer 300 filling in the
trenches 320. In a case, the etching rate in an initial deposition
stage of the deposition step is lower than that in a main
deposition stage of the same, so that a liner layer 340 is formed
on the wafer 300 in the initial deposition stage, as shown in FIG.
3B, and thus the surface of the wafer 300 is further prevented from
damage caused by plasma.
[0036] FIG. 4(a) illustrates a system for conducting a filling-in
process according to the second embodiment of this invention and
FIG. 4(b) a cluster tool including the system.
[0037] Referring to FIG. 4(a), the system includes an HDP-CVD
chamber 100 for conducting a pre-heating step and a deposition
step, a chamber 114 for forming a liner layer on a wafer 10 before
the pre-heating step, and wafer transfer means 104. In this
embodiment, the HDP-CVD chamber 100 is set to pre-heat the wafer 10
to a temperature required in the deposition step to be conducted
therein.
[0038] When the material to be deposited with HDP-CVD is silicon
oxide, the chamber 114 may be one capable of depositing
high-temperature oxide (HTO) or one capable of depositing silicon
oxide through plasma-enhanced chemical vapor deposition (PECVD).
The HTO may be formed through low-pressure chemical vapor
deposition (LPCVD). As in the first embodiment, the wafer transfer
means 104 is usually a robot.
[0039] Referring to FIG. 4(b), the HDP-CVD chamber 100 and the
chamber 114 may also be integrated in a cluster tool 110' while the
wafer transfer means 104 placed in a loading room 112 of the
cluster tool 110' as in the first embodiment. Thus, a wafer 10 can
be prevented from contacting the outer atmosphere during its
transfer and is protected from contamination and/or oxidation
thereby.
[0040] FIGS. 5A-5C illustrate an exemplary application of a
filling-in process of this invention to an STI process according to
an example of the second embodiment.
[0041] Referring to FIG. 5A, a wafer 200 formed with a mask layer
220 thereon and with trenches 230 of an STI structure therein is
provided, wherein a pad oxide layer 210 may be formed on the wafer
200 before the mask layer 220 is formed. After the wafer 200 is
loaded into the chamber 114, a liner layer 240 is formed thereon.
When the material to be deposited with HDP-CVD is silicon oxide,
the material of the liner layer 240 may be high-temperature oxide
(HTO) or silicon oxide formed through PECVD.
[0042] The HTO may be formed through LPCVD using SiH.sub.4 and
N.sub.2O as reaction gases at a temperature of 550-850.degree. C.,
preferably 650-800.degree. C. and more preferably 700-800.degree.
C., under a pressure of 0.1-400 Torr, preferably 0.5-300 Torr and
more preferably 50-200 Torr. The PECVD process may use SiH.sub.4
and N.sub.2O as reaction gases and may be conducted with a power of
50-1000 W, preferably 50-500 W and more preferably 100-300 W, at
250-550.degree. C., preferably 300-500.degree. C. and more
preferably 375-425.degree. C., under a pressure of 0.1-100 Torr,
preferably 2-20 Torr and more preferably 4-15 Torr.
[0043] Referring to FIG. 5B, the wafer 200 is then moved out of the
chamber 114 and loaded into the HDP-CVD chamber 100, and a
pre-heating step 20' inherently with plasma generation and ion
bombardment 22 is conducted in the HDP-CVD chamber 100 to pre-heat
the wafer 10 to a temperature required in the deposition step to be
conducted in the HDP-CVD chamber 100. For example, when the
insulating material to be deposited on the wafer 200 as the
material of the STI structure is silicon oxide, the temperature to
which the wafer is pre-heated is usually between 300.degree. C. and
800.degree. C. Since a liner layer 240 has been formed on the wafer
200, the devices on the wafer 200 are prevented from being damaged
by the plasma ion bombardment 22.
[0044] Referring to FIGS. 5B-5C, after the wafer 200 is pre-heated
to the required temperature, a deposition step is conducted in the
HDP-CVD chamber 100 to deposit an insulating layer 250 on the wafer
200 filling up the trenches 230. When silicon oxide is to be
deposited, the reaction gas may include SiH.sub.4, O.sub.2 and
Ar.
[0045] FIGS. 6A-6C illustrate an exemplary application of a
filling-in process of this invention to an ILD process according to
another example of the second embodiment.
[0046] Referring to FIG. 6A, a wafer 300 formed with conductive
lines 310 thereon is provided, wherein trenches 320 are present
between the conductive lines 310 and the conductive lines 310 may
include metal. After the wafer 200 is loaded in the chamber 114, a
liner layer 240 is formed on the wafer 200. When the material to be
deposited with HDP-CVD is silicon oxide, the material of the liner
layer 240 may be silicon oxide formed with a PECVD process, which
may use SiH.sub.4 and N.sub.2O as reaction gases and may be done
with a power of 30-2000 W, preferably 50-500 W and more preferably
100-300 W, at 250-550.degree. C., preferably 300-500.degree. C. and
more preferably 375-425.degree. C., under a pressure of 0.1-100
Torr, preferably 2-20 Torr and more preferably 4-15 Torr.
[0047] Referring to FIG. 6B, the wafer 300 is moved out of the
chamber 114 and loaded in the HDP-CVD chamber 100, in which a
pre-heating step is conducted to pre-heat the wafer 300 to a
temperature required in the deposition step to be conducted in the
HDP-CVD chamber 100. For example, when the conductive lines 310
include metal and the insulating material to be deposited as the
material of the ILD layer is silicon oxide, the temperature to
which the wafer 300 is pre-heated is between 300.degree. C. and
500.degree. C.
[0048] Referring to FIGS. 6B-6C, after the wafer 300 is pre-heated
to the required temperature, a deposition step is conducted in the
HDP-CVD chamber 100 to deposit an insulating layer 350 on the wafer
300 filling in the trenches 320.
[0049] Since the wafer is pre-heated before being loaded into the
HDP-CVD chamber or is formed with a liner layer thereon before the
pre-heating step conducted in the HDP-CVD chamber, the film quality
is improved. Meanwhile, since the wafer is pre-heated outside of
the HDP-CVD chamber, device damage due to plasma ion bombardment is
prevented. Moreover, in cases where the wafer is pre-heated outside
of the HDP-CVD chamber together with at least one other wafer, not
only plasma damage is prevented in the pre-heating step of the
HDP-CVD process, but also the time required for separately
pre-heating the wafers in the HDP-CVD chamber in the prior art can
be saved so that the wafer-per-hour (WPH) value is increased.
[0050] This invention has been disclosed above in the preferred
embodiments, but is not limited to those. It is known to persons
skilled in the art that some modifications and innovations may be
made without departing from the spirit and scope of this invention.
Hence, the scope of this invention should be defined by the
following claims.
* * * * *