U.S. patent application number 12/824536 was filed with the patent office on 2011-12-29 for testing die-to-die bonding and rework.
This patent application is currently assigned to XILINX, INC.. Invention is credited to Arifur Rahman.
Application Number | 20110316572 12/824536 |
Document ID | / |
Family ID | 43877276 |
Filed Date | 2011-12-29 |
United States Patent
Application |
20110316572 |
Kind Code |
A1 |
Rahman; Arifur |
December 29, 2011 |
TESTING DIE-TO-DIE BONDING AND REWORK
Abstract
A method of testing a multi-die integrated circuit (IC) can
include testing an inter-die connection of the multi-die IC. The
inter-die connection can include a micro-bump coupling a first die
to a second die. The method can include detecting whether a fault
occurs during testing of the inter-die connection. Responsive to
detecting the fault, the multi-die integrated circuit can be
designated as including a faulty inter-die connection. Also
described is an integrated circuit that includes a first die, a
second die on which the first die may be disposed, a plurality of
inter-die connections coupling the first die to the second die, and
a plurality of probe pads, where each probe pad is coupled to at
least one of the inter-die connections.
Inventors: |
Rahman; Arifur; (San Jose,
CA) |
Assignee: |
XILINX, INC.
San Jose
CA
|
Family ID: |
43877276 |
Appl. No.: |
12/824536 |
Filed: |
June 28, 2010 |
Current U.S.
Class: |
324/754.03 ;
257/48; 257/E23.141; 324/762.03 |
Current CPC
Class: |
H01L 24/16 20130101;
H01L 2225/06541 20130101; H01L 2924/01033 20130101; H01L 2924/157
20130101; H01L 2924/01075 20130101; G01R 31/2853 20130101; H01L
2225/06513 20130101; H01L 25/0657 20130101; H01L 2924/14 20130101;
H01L 2924/1433 20130101; H01L 2924/014 20130101; H01L 22/22
20130101; H01L 25/0655 20130101; H01L 2924/1434 20130101; H01L
22/14 20130101; H01L 25/0652 20130101; H01L 2924/14335 20130101;
H01L 22/32 20130101; H01L 22/20 20130101; H01L 2224/16145 20130101;
H01L 2224/16225 20130101; H01L 2224/97 20130101; H01L 2225/06517
20130101; G01R 31/318513 20130101; H01L 2924/01005 20130101; H01L
2924/15192 20130101; H01L 2924/15311 20130101; H01L 24/97 20130101;
H01L 2224/023 20130101; H01L 2224/97 20130101; H01L 2924/15311
20130101; H01L 2224/023 20130101; H01L 2924/0001 20130101 |
Class at
Publication: |
324/754.03 ;
257/48; 257/E23.141; 324/762.03 |
International
Class: |
G01R 31/02 20060101
G01R031/02; H01L 23/58 20060101 H01L023/58; G01R 31/20 20060101
G01R031/20; G01R 31/26 20060101 G01R031/26 |
Claims
1. A method of testing a multi-die integrated circuit, the method
comprising: testing an inter-die connection of the multi-die
integrated circuit, wherein the inter-die connection comprises a
bump coupling a first die to a second die; wherein the testing the
inter-die connection includes: providing a first probe pad disposed
on the second die, wherein the first probe pad is coupled to a
first bump coupling the first die to the second die; providing a
second probe pad disposed on the second die, wherein the second
probe pad is coupled to a second bump coupling the first die to the
second die; and loading configuration data into configuration
memory cells in the first die, wherein the configuration memory
cells having the configuration data establish an internal
connection in the first die, coupling the first bump to the second
bump; detecting whether a fault occurs during testing of the
inter-die connection; and responsive to detecting the fault,
designating the multi-die integrated circuit as including a faulty
inter-die connection.
2. The method of claim 1, further comprising: selecting the second
die to be an interposer consisting essentially of at least one
passive metal layer.
3. (canceled)
4. The method of claim 1, wherein detecting whether a fault occurs
comprises: determining whether a test signal propagates from the
first probe pad to the second probe pad.
5. The method of claim 1, wherein testing the inter-die connection
comprises: disposing the first die on the second die, wherein the
second die comprises a first through silicon via (TSV) coupled to
the first die through a first bump and a second TSV coupled to the
first die through a second bump; and within the first die,
establishing an internal connection coupling the first bump to the
second bump.
6. The method of claim 5, wherein detecting whether a fault occurs
comprises: determining whether a test signal provided to the first
TSV propagates to the second TSV.
7. The method of claim 6, wherein: the first TSV is coupled to the
first bump at a first end of the first TSV and is coupled to a
first package bump at a second end of the first TSV; the second TSV
is coupled to the second bump at a first end of the second TSV and
is coupled to a second package bump at a second end of the second
TSV; and detecting whether a fault occurs further comprises
determining whether a test signal provided to the first package
bump propagates to the second package bump.
8. The method of claim 5, wherein testing the inter-die connection
further comprises: providing a first probe pad and a second probe
pad disposed on the second die, wherein the first probe pad is
coupled to the first TSV and the second probe pad is coupled to the
second TSV.
9. The method of claim 1, wherein testing the inter-die connection
further comprises: providing a first probe pad disposed on the
second die, wherein the first probe pad is coupled to a first bump;
providing a through silicon via (TSV) within the second die,
wherein a first end of the TSV couples to a second bump; and within
the first die, establishing an internal connection coupling the
first bump to the second bump.
10. The method of claim 9, wherein detecting whether a fault occurs
comprises: determining whether a test signal propagates from the
first probe pad to the TSV.
11. The method of claim 1, wherein the first die is bonded to the
second die using a semi-permanent bonding technique, the method
further comprising: re-processing, when the multi-die integrated
circuit is designated as including a faulty inter-die connection,
the inter-die connection.
12. An integrated circuit, comprising: a first die; a second die,
wherein the first die is disposed on the second die; a third die
disposed on the second die; wherein the first die and the third die
are in substantially a same horizontal plane; a plurality of
inter-die connections coupling the first die to the second die; and
a plurality of probe pads, wherein each probe pad is coupled to at
least one of the inter-die connections, wherein at least one of the
plurality of probe pads is located between the first die and the
third die.
13. The integrated circuit of claim 12, wherein the plurality of
probe pads are distributed along at least one edge of the second
die.
14. The integrated circuit of claim 12, wherein the plurality of
probe pads are distributed along each edge of the second die and
encompass the first die.
15. (canceled)
16. An integrated circuit, comprising: a first die that includes
configuration memory cells; a second die, wherein the first die is
stacked on the second die; a plurality of inter-die connections,
wherein each inter-die connection comprises a bump disposed between
the first die and the second die coupling the first die to the
second die; a first probe pad disposed on the second die, wherein
the first probe pad is coupled to a first bump; and a second probe
pad disposed on the second die, wherein the second probe pad is
coupled to a second bump, wherein the configuration memory cells of
the first die are configured with configuration data to establish
an internal connection coupling the first bump to the second
bump.
17-18. (canceled)
19. The integrated circuit of claim 16, wherein the first die is
permanently bonded to the second die only after determining that
the plurality of inter-die connections are fault free.
20. The integrated circuit of claim 16, wherein: at least one of
the plurality of inter-die connections comprises a through silicon
via (TSV) within the second die; a first end of the TSV is coupled
to the first bump and a second end of the TSV extends through the
second die to a surface of the second die opposite a surface upon
which the first and second probe pads are disposed; and the first
probe pad couples to the first bump using the TSV.
Description
FIELD OF THE INVENTION
[0001] One or more embodiments disclosed within this specification
relate to integrated circuits (ICs). More particularly, one or more
embodiments relate to testing ICs that include multiple dies.
BACKGROUND
[0002] The probability that a flaw will occur in a die when
manufacturing an integrated circuit (IC) generally increases as the
size of the die used to implement the IC increases. The occurrence
of a manufacturing flaw, also referred to as a "fault," within an
IC can result in a reduction, or complete failure, in the
operability of the IC. For this reason, it can be more cost
effective to implement an IC in the form of a multi-die IC as
opposed to a single, monolithic die.
[0003] A multi-die IC, in general, is formed using a plurality of
dies coupled together and disposed within a single package. A
manufacturing fault occurring within any one of the dies of a
multi-die IC renders only that die inoperable. Thus, within a
multi-die IC, a manufacturing fault renders less die area unusable
than when a fault occurs within an IC formed of a single, larger
die.
[0004] While the use of multi-die ICs can increase yield with
respect to the final product, multi-die ICs still must undergo
thorough testing. For example, the connectivity among the different
dies that are combined to form the multi-die IC structure must be
robust and reliable. Otherwise, the entire multi-die IC, referring
to each constituent die, becomes unusable.
SUMMARY
[0005] One or more embodiments disclosed within this specification
relate to integrated circuits (ICs) and, more particularly, to
testing ICs that include multiple dies. One or more embodiments can
include a method of testing a multi-die IC. The method can include
testing an inter-die connection of the multi-die IC, wherein the
inter-die connection includes a micro-bump coupling a first die to
a second die. The method also can include detecting whether a fault
occurs during testing of the inter-die connection. Responsive to
detecting the fault, the multi-die IC can be designated as
including a faulty inter-die connection.
[0006] The method can include selecting the second die to be an
interposer consisting essentially of at least one passive metal
layer.
[0007] Testing the inter-die connection can include providing a
first probe pad disposed on top of the second die, wherein the
first probe pad is coupled to a first micro-bump coupling the first
die to the second die. A second probe pad can be provided and
disposed on top of the second die. The second probe pad can be
coupled to a second micro-bump coupling the first die to the second
die. The method can include, within the first die, establishing an
internal connection coupling the first micro-bump to the second
micro-bump.
[0008] Detecting whether a fault occurs can include determining
whether a test signal propagates from the first probe pad to the
second probe pad.
[0009] Testing the inter-die connection also can include disposing
the first die on top of the second die, wherein the second die
includes a first through silicon via (TSV) coupled to the first die
through a first micro-bump and a second TSV coupled to the first
die through a second micro-bump. Within the first die, an internal
connection can be established coupling the first micro-bump to the
second micro-bump.
[0010] Detecting whether a fault occurs can include determining
whether a test signal provided to the first TSV propagates to the
second TSV.
[0011] In one or more aspects, the first TSV can be coupled to the
first micro-bump at a first end of the first TSV and can be coupled
to a first package bump at a second end of the first TSV. The
second TSV can be coupled to the second micro-bump at a first end
of the second TSV and coupled to a second package bump at a second
end of the second TSV. Accordingly, detecting whether a fault
occurs can include determining whether a test signal provided to
the first package bump propagates to the second package bump.
[0012] Testing the inter-die connection further can include
providing a first probe pad and a second probe pad disposed on top
of the second die. The first probe pad can be coupled to the first
TSV. The second probe pad can be coupled to the second TSV.
[0013] Testing the inter-die connection also can include providing
a first probe pad disposed on top of the second die. The first
probe pad can be coupled to a first micro-bump. A TSV can be
provide within the second die. A first end of the TSV can be
coupled to a second micro-bump. Within the first die, an internal
connection can be established coupling the first micro-bump to the
second micro-bump.
[0014] Detecting whether a fault occurs further can include
determining whether a test signal propagates from the first probe
pad to the TSV.
[0015] The first die can be bonded to the second die using a
semi-permanent bonding technique. In that case, when the multi-die
integrated circuit is designated as including a faulty inter-die
connection, the inter-die connection can be re-processed.
[0016] One or more other embodiments can include an IC. The IC can
include a first die, a second die, and a plurality of inter-die
connections coupling the first die to the second die. The IC also
can include a plurality of probe pads, wherein each probe pad is
coupled to an inter-die connection.
[0017] In one or more aspects, the plurality of probe pads can be
distributed along at least one edge of the second die. In one or
more other aspects, the plurality of probe pads can be distributed
along each edge of the second die and encompass the first die.
[0018] The first die can be disposed on top of the second die.
Accordingly, the IC can include a third die disposed on top of the
second die. The first die and the third die can be in substantially
a same horizontal plane. At least one of the probe pads can be
located between the first die and the third die.
[0019] One or more other embodiments can include an IC having a
first die and a second die stacked on top of the first die. The IC
can include a plurality inter-die connections, wherein each
inter-die connection includes a micro-bump disposed between the
first die and the second die that couples the first die to the
second die. The IC can include a first probe pad disposed on top of
the second die, wherein the first probe pad can be coupled to a
first micro-bump. The IC can include a second probe pad disposed on
top of the second die, wherein the second probe pad can be coupled
to a second micro-bump. The second die can be configured to
establish an internal connection coupling the first micro-bump to
the second micro-bump.
[0020] In one or more aspects, the internal connection can be
fixed. In one or more other aspects, the internal connection can be
formed using programmable circuitry of the second die by loading
configuration data into the second die.
[0021] The first die can be bonded on top of the second die using a
semi-permanent bonding technique. For example, the first die can be
permanently bonded to the second die only after determining that
the plurality of inter-die connections are fault free.
[0022] One or more of the plurality of inter-die connections can
include a TSV within the second die. A first end of the TSV can be
coupled to the first micro-bump. A second end of the TSV can extend
through the second die to a surface of the second die opposite a
surface upon which the first and second probe pads are disposed.
The first probe pad can couple to the first micro-bump using the
TSV.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a first block diagram illustrating a multi-die
integrated circuit (IC) in accordance with one or more embodiments
disclosed within this specification.
[0024] FIG. 2 is a first cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification.
[0025] FIG. 3 is a second cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification.
[0026] FIG. 4 is a third cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification.
[0027] FIG. 5 is a fourth cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification.
[0028] FIG. 6 is a fifth cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification.
[0029] FIG. 7 is a sixth cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification.
[0030] FIG. 8 is a flow chart illustrating a method of testing
inter-die connections within a multi-die IC in accordance with one
or more other embodiments disclosed within this specification.
DETAILED DESCRIPTION
[0031] While the specification concludes with claims defining
features of one or more embodiments that are regarded as novel, it
is believed that the one or more embodiments will be better
understood from a consideration of the description in conjunction
with the drawings. As required, one or more detailed embodiments
are disclosed within this specification. It should be appreciated,
however, that the one or more embodiments are merely exemplary of
the inventive arrangements, which can be embodied in various forms.
Therefore, specific structural and functional details disclosed
within this specification are not to be interpreted as limiting,
but merely as a basis for the claims and as a representative basis
for teaching one skilled in the art to variously employ the one or
more embodiments in virtually any appropriately detailed structure.
Further, the terms and phrases used herein are not intended to be
limiting, but rather to provide an understandable description of
the one or more embodiments disclosed herein.
[0032] One or more embodiments disclosed within this specification
relate to integrated circuits (ICs) and, more particularly, to
testing ICs that include multiple dies (referred to herein as
"multi-die ICs"). In accordance with one or more embodiments
disclosed within this specification, the physical connections that
facilitate communication between dies of a multi-die IC can be
tested. Various testing techniques are disclosed that facilitate
testing of inter-die connections and the identification of faulty
inter-die connections. Circuit structures are also disclosed that
facilitate testing of the inter-die connections.
[0033] Conventional multi-die ICs are usually formed using small
sized dies. In consequence, the number of inter-die connections
that are formed when the dies are bonded together is typically
small enough that the inter-die connections are not tested. For
example, conventional multi-die ICs are constructed using small die
sizes that are joined through only a limited number of inter-die
connections. In such cases, independent testing of the inter-die
connections and structures used to create the inter-die connections
is not performed because the cost of each individual die is so
small that the cost of even the entire multi-die IC is of little
consequence should one need to be discarded due to faults in the
inter-die connections.
[0034] When multi-die ICs are created using larger, more expensive
die sizes, however, discarding even a single die in consequence of
a faulty inter-die connection can be costly since two or more
larger and more expensive dies that are known to be good or fault
free are effectively discarded. Moreover, the number of inter-die
connections that are formed when bonding two or more larger dies
together to form a multi-die IC is significantly larger. The larger
number of inter-die connections merits the added time and expense
of testing. For example, with larger die sizes, the number of
inter-die connections can be approximately 100 times that typically
found in smaller, conventional multi-die ICs.
[0035] FIG. 1 is a first block diagram illustrating a multi-die IC
100 in accordance with one or more embodiments disclosed within
this specification. As shown, multi-die IC 100 includes die 105 and
die 110 disposed on a top surface of an interposer 115. For
example, die 105 and die 110 can be in direct physical contact with
interposer 115 or can be coupled through one or more intervening IC
manufacturing process layers that can include one or more circuit
structures.
[0036] Each of dies 105 and 110 can implement any of a variety of
different types of circuits or chips. For example, each of dies 105
and 110 can be implemented as a memory, a processor, or a
programmable IC. In another example, die 105 can implement a memory
and die 110 can implement a processor or a programmable IC. In
still another example, one or both of dies 105 and 110 can
implement application specific ICs or a mixed signal IC. The
examples presented are for purposes of illustration and are not
intended to limit the one or more embodiments disclosed within this
specification.
[0037] Programmable ICs are a well-known type of IC that can be
programmed to perform specified logic functions. One type of
programmable IC, the field programmable gate array (FPGA),
typically includes an array of programmable tiles. These
programmable tiles can include, for example, input/output blocks
(IOBs), configurable logic blocks (CLBs), dedicated random access
memory blocks (BRAM), multipliers, digital signal processing blocks
(DSPs), processors, clock managers, delay lock loops (DLLs), and so
forth.
[0038] Each programmable tile typically includes both programmable
interconnect and programmable logic circuitry. The programmable
interconnect circuitry typically includes a large number of
interconnect lines of varying lengths interconnected by
programmable interconnect points (PIPs). The programmable logic
circuitry implements the logic of a user design using programmable
elements that can include, for example, function generators,
registers, arithmetic logic, and so forth.
[0039] The programmable interconnect circuits and programmable
logic circuits are typically programmed by loading a stream of
configuration data into internal configuration memory cells that
define how the programmable elements are configured. The
configuration data can be read from memory (e.g., from an external
PROM) or written into the FPGA by an external device. The
collective states of the individual memory cells then determine the
function of the FPGA.
[0040] Another type of programmable IC is the complex programmable
logic device, or CPLD. A CPLD includes two or more "function
blocks" connected together and to input/output (I/O) resources by
an interconnect switch matrix. Each function block of the CPLD
includes a two-level AND/OR structure similar to those used in
programmable logic arrays (PLAs) and programmable array logic (PAL)
devices. In CPLDs, configuration data is typically stored on-chip
in non-volatile memory. In some CPLDs, configuration data is stored
on-chip in non-volatile memory, then downloaded to volatile memory
as part of an initial configuration (programming) sequence.
[0041] For all of these programmable ICs, the functionality of the
device is controlled by data bits provided to the device for that
purpose. The data bits can be stored in volatile memory (e.g.,
static memory cells, as in FPGAs and some CPLDs), in non-volatile
memory (e.g., FLASH memory, as in some CPLDs), or in any other type
of memory cell.
[0042] Other programmable ICs are programmed by applying a
processing layer, such as a metal layer, that programmably
interconnects the various elements on the device. These
programmable ICs are known as mask programmable devices.
Programmable ICs can also be implemented in other ways, e.g., using
fuse or antifuse technology.
[0043] The phrase "programmable IC" can include, but is not limited
to these devices and further can encompass devices that are only
partially programmable. For example, one type of programmable IC
includes a combination of hard-coded transistor logic and a
programmable switch fabric that programmably interconnects the
hard-coded transistor logic. Referring to FIG. 1, die 105, die 110,
or both dies 105 and 110, for example can be implemented as a
programmable IC.
[0044] Continuing with FIG. 1, interposer 115 can communicatively
link die 105 and die 110 by coupling selected pads of die 105 with
selected pads of die 110. A connection between die 105 and die 110,
in this case facilitated by interposer 115, can be referred to as
an inter-die connection. An inter-die connection refers to a signal
path that begins in a first die and traverses a boundary between
the first die a second die. The inter-die connection can traverse
further boundaries between dies, whether continuing into a third
die or looping back from the second die to the first die. In
traversing a boundary between two dies, whether the boundary is
formed between die 105 and die 110, between die 105 and interposer
115, between die 110 and interposer 115, or any other combination
thereof, the inter-die connection includes the particular circuit
structure used to communicatively link the two dies.
[0045] For purposes of illustration, only two dies are shown on top
of interposer 115. The one or more embodiments described within
this specification, however, are not intended to be limited by the
number of dies disposed upon interposer 115. For example, three or
more dies can be disposed on top of interposer 115. Further, other
multi-die configurations can be used as will be described within
this specification in greater detail.
[0046] Multi-die IC 100 further can include a plurality of probe
pads 120. Each of probe pads 120 can be disposed on interposer 115.
The connectivity of different ones of probe pads 120 will be
described in greater detail with reference to the remaining
figures. Probe pads 120 can be distributed on a top surface of
interposer 115. As illustrated, probe pads 120 are disposed on the
same surface upon which die 105 and die 110 are disposed.
Accordingly, die 105, die 120, and probe pads 120 can be
implemented substantially within a same horizontal plane that is
parallel to the top surface of interposer 115. Probe pads 120 can
be arranged in a variety of different configurations including, for
example, being disposed around the outer edge of interposer 115,
e.g., surrounding each of dies 105 and 110, and between dies 105
and 110.
[0047] It should be appreciated that while probe pads 120 are shown
as being distributed across the top surface of interposer 115,
probe pads 120 can be distributed in a more limited fashion. For
example, probe pads 120 can be distributed along only one edge of
interposer 115, along only two edges of interposer 115, along only
three edges of interposer 115, or along all four edges of
interposer 115. In each of these examples, probe pads 120 can be
located between die 105 and die 110 or not.
[0048] The existence of probe pads 120 upon interposer 115 does not
preclude the use of additional probe pads (not shown) upon die 105
and/or die 110 or additional probe pads (not shown) dedicated for
testing selected features solely within interposer 115, e.g.,
features other than inter-die connections. Such probe pads,
however, are considered to be a separate class of probe pads, and
thus, independent of probe pads 120, which facilitate more direct
testing of inter-die connections.
[0049] In one or more embodiments, the distribution of probe pads
120 across interposer 115 can improve power distribution in
multi-die IC 100. Within larger dies, for example, when power is
supplied from the periphery of the die, a voltage drop can be seen
from the periphery of the die to the center of the die. The
distribution of probe pads 120 can reduce the size of the voltage
drop seen across each of the dies, e.g., across die 105 and/or die
110. The addition of probe pads 120 on the periphery of interposer
115, with power and ground grids coupled to probe pads 120, can
reduce the effective resistance from pad to transistor in multi-die
IC 100. Reduction in effective resistance translates into less
voltage drop from pad to transistor.
[0050] FIG. 2 is a first cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification. FIG. 2 illustrates multi-die IC 100 of
FIG. 1 in cross-section taken along cut-line 2 of FIG. 1.
Accordingly, like numbers will be used to refer to the same items
throughout this specification.
[0051] Interposer 115 can be implemented as a die formed of one or
more layers of an IC manufacturing process. Interposer 115 can
include at least one metallization layer, but can include a
plurality of metallization layers separated by appropriate
insulating or non-conductive layers. The metallization layer, or
layers as the case may be, implements inter-die wires 205 that
couple selected pads of die 105 to selected pads of die 110.
[0052] In one or more embodiments, interposer 115 can be configured
as an entirely passive structure within which inter-die wires 205
are implemented. In one or more other embodiments, interposer 115
can include one or more active devices and, thus, be considered an
active structure. The one or more embodiments described within this
specification are not intended to be limited to either passive or
active interposers. In one or more embodiments, interposer 115 can
be considered a third die reserved for implementing the necessary
signaling between dies 105 and 110.
[0053] Die 105 and die 110 can be coupled to interposer 115 through
a plurality of micro bumps 210. Micro bumps 210 generally are
solder balls that electrically couple pads (not shown) of each of
dies 105 and 110 to pads (not shown) of interposer 115. The pads of
interposer 115 coupled to micro bumps 210 can couple to inter-die
wires 205 or through silicon vias (TSVs) 215. Inter-die wires 205
are effectively long interconnect lines within interposer 115 that
couple different dies. For example, inter-die wires 205 can couple
one or more pads of die 105 with one or more pads of die 110. As
shown, inter-die wires 205 can be disposed beneath the top surface,
e.g., within, interposer 115.
[0054] Each TSV 215, in contrast to a vertical portion of each
inter-die wire 205, can extend completely through interposer 115
extending from a pad disposed immediately below the top surface of
interposer 115 through to a pad exposed through the bottom surface
of interposer 115. Each TSV 215 can couple a pad of one of dies 105
or 110, via a micro bump 210, for example, to one of the plurality
of package bumps 220. Package bumps 220, also referred to as "C4
bumps," generally are solder balls that couple pads on the bottom
portion of interposer 115 to the package of multi-die IC 100, and
thus, to external pins of the package. One or more pads of die 105
and one or more pads of die 110 can be coupled to external pins of
the package of multi-die IC 100 by coupling the pads to micro bumps
210, to TSVs 215, to package bumps 220, and to external package
pins.
[0055] Die 105, die 110, and interposer 115 can be manufactured
separately, e.g., each as part of its own distinct wafer. Die 105,
die 110, and interposer 115 can be tested while still in wafer
form, e.g., prior to dicing and prior to bonding die 105 and die
110 to the top surface of interposer 115. Testing while still in
wafer form ensures that known bad dies are not used in implementing
multi-die IC 100. Thus, die 105 and die 110 each is a "known good
die." Only dies that are determined via testing to be known good
dies can be bonded to an interposer.
[0056] FIG. 3 is a second cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification. FIG. 3 illustrates a test example in
which one or more of probe pads 120 of multi-die IC 100 are coupled
to inter-die wires 205 to facilitate testing of inter-die
connections. FIG. 3 illustrates a test case in which die 105, die
110, and interposer 115 each is a known good die, or fault free.
Die 105 and die 110 can be diced and mounted upon interposer 115.
Interposer 115 can exist in wafer form. Alternatively, interposer
115 can be diced.
[0057] As shown, probe pad 120A can be coupled to inter-die wire
205A via pad coupling circuitry 305. Probe pad 120B can be coupled
to inter-die wire 205B via pad coupling circuitry 310. Depending
upon whether interposer 115 is implemented as a passive structure
or an active structure, pad coupling circuitry 305 and pad coupling
circuitry 310 can be implemented as passive structures, e.g.,
wires, capacitors, and/or the like, or as a combination of passive
and active structures, e.g., one or more switches that selectively
couple probe pads to the target inter-die wire.
[0058] FIG. 3 illustrates a test case in which micro-bumps 210 that
bond and communicatively link die 110 to interposer 115 are tested.
Die 110 can be configured to form an internal connection 315
between inter-die wire 205A and inter-die wire 205B.
[0059] In one or more embodiments, for example, in the case where
die 110 is implemented as a programmable IC, configuration data can
be loaded into die 110 to instantiate or form connection 315 using
the programmable circuitry available within the programmable IC.
Implementing connection 315 using programmable circuitry can entail
utilization of significant physical wires, transistors, nets, and
micro-bumps. Different configuration memory will enable different
sets of programmable connections.
[0060] Though one internal connection is illustrated, it should be
appreciated that the loading of configuration data within one or
both of dies 105 and 110 can implement a plurality of internal
connections to facilitate the testing of many inter-die connections
while utilizing a minimum of probe pads 120, e.g., two. This type
of approach, e.g., maximizing the connections while minimizing
usage of probe pads 120, requires fewer test patterns due to the
increased number of micro-bumps that are tested for a given set of
configuration data and the corresponding programmable nets that are
created. In one or more other embodiments, however, internal
connection 315 can be fixed as opposed to being implemented using
programmable circuitry requiring the loading of configuration
data.
[0061] A probe 320 can output a test signal, e.g., a test vector,
to probe pad 120A. Probe 320 can monitor probe pad 120B to
determine whether the test signal is received. When the test signal
is received through probe pad 120B, the inter-die connection
between die 110 and interposer 115, at least with respect to the
particular micro-bumps that couple to inter-die wire 205A and
inter-die wire 205B to die 110, can be determined to be fault free.
The process can be repeated to test further inter-die connections
between die 105 and interposer 115 and between die 110 and
interposer 115. In one or more embodiments, different pairs of
micro-bumps can be tested sequentially until all, or substantially
all, micro-bumps that couple die 105 and die 110 to interposer 115
are tested.
[0062] Within this specification, reference is made to a probe that
can provide test signals and monitor for the receipt of the test
signals provided as output from the particular device under test.
It should be appreciated that the probe can be part of a larger IC
testing system. The IC testing system can include a processing
system that can control probe 320 to implement the various test
functions described herein. In one or more embodiments, the
processing system can be implemented as a computer system or any
other data processing system that can execute programmatic
instructions. Using probe 320 in combination with the processing
system and any other components, e.g., IC handling subsystems, of
the IC testing system, faulty inter-die connections can be
identified and multi-die ICs having faulty inter-die connections
can be tagged or otherwise identified.
[0063] FIG. 4 is a third cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification. FIG. 4 illustrates another test example
in which one or more of probe pads 120 of multi-die IC 100 are
coupled to inter-die wires 205 to facilitate testing of inter-die
connections.
[0064] FIG. 4 illustrates a test case in which die 105, die 110,
and interposer 115 each is a known good die. Die 105 and die 110
can be diced and mounted upon interposer 115. Interposer 115 can
exist in wafer form or can be diced.
[0065] As shown, probe pad 120A can be coupled to inter-die wire
205A via pad coupling circuitry 305. Probe pad 120B can be coupled
to inter-die wire 205B via pad coupling circuitry 310. Depending
upon whether interposer 115 is implemented as a passive structure
or an active structure, coupling circuitry 305 and 310 can be
implemented as passive structures or a combination of passive and
active structures. Probe pad 120C can be coupled to inter-die wire
205C via pad coupling circuitry 405. Probe pad 120D can be coupled
to inter-die wire 205D via pad coupling circuitry 410.
[0066] Die 105 can be configured to implement internal connections
415 and 420. Internal connection 415 couples inter-die wire 205B to
inter-die wire 205C within die 105. Internal connection 420 couples
inter-die wire 205A to inter-die wire 205D within die 105.
Accordingly, probe 320 can output a test signal to probe pad 120A.
The test signal can propagate through probe coupling circuitry 305
to inter-die wire 205A, through micro-bump(s) coupling inter-die
wire 205A to die 105, through internal connection 420, through
micro-bump(s) coupling die 110 to inter-die wire 205D, through
probe coupling circuitry 410 to probe pad 120D. When probe 320
detects the test signal on probe pad 120D, the described signal
path can be determined to be fault free. Thus, micro-bumps 210 that
couple inter-die wires 205A and 205D to die 105 can be determined
to be fault free.
[0067] Similarly, probe 320 can output a test signal to probe pad
1208. The test signal can propagate through probe coupling
circuitry 310 to inter-die wire 2058, through micro-bumps coupling
inter-die wire 2058 to die 105, through internal connection 415 and
micro-bump(s) coupling die 105 to inter-die wire 205C, to pad
coupling circuitry 405 to probe pad 120C. When probe 320 detects
the test signal on probe pad 120C, the described signal path can be
determined to be fault free. Accordingly, micro-bumps 210 that
couple inter-die wires 205B and 205C to die 105 can be determined
to be fault free.
[0068] FIG. 5 is a fourth cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification. FIG. 5 illustrates another test example
in which one or more of probe pads 120 of multi-die IC 100 are
coupled to TSVs 215 to facilitate testing of inter-die connections.
FIG. 5 illustrates a test case in which die 105, die 110, and
interposer 115 each is a known good die. Die 105 and die 110 can be
diced and mounted upon interposer 115. Interposer 115 can exist in
wafer form or can be diced.
[0069] As shown, probe pad 120A can be coupled to TSV 215A via pad
coupling circuitry 505. Probe pad 120E can be coupled to TSV 215B
via pad coupling circuitry 510. Depending upon whether interposer
115 is implemented as a passive structure or an active structure,
pad coupling circuitry 505 and 510 can be implemented as passive
structures or a combination of passive and active structures.
[0070] Die 110 can be configured to implement internal connection
515. Internal connection 515 couples TSV 215A to TSV 215B via
micro-bumps 210. Accordingly, probe 320 can output a test signal to
probe pad 120A. The test signal can propagate through pad coupling
circuitry 505 to TSV 215A, through micro-bump(s) coupling TSV 215A
to die 110, through internal connection 515 and micro-bump(s) 210
coupling die 110 to TSV 215B, and through pad coupling circuitry
510 to probe pad 120E. When probe 320 detects the test signal on
probe pad 120E, the described signal path can be determined to be
fault free. It should be appreciated that successfully testing the
aforementioned signal path requires micro-bump(s) coupling die 110
to TSVs 215A and 2158 to be fault free.
[0071] FIG. 6 is a fifth cross-sectional side view of a multi-die
IC in accordance with one or more other embodiments disclosed
within this specification. FIG. 6 illustrates another test example
in which inter-die connections are tested by probing package bumps
220 of multi-die IC 100. FIG. 6 illustrates a test case in which
die 105, die 110, and interposer 115 each is a known good die. Die
105 and die 110 can be diced and mounted upon interposer 115.
Interposer 115 can exist in wafer form or can be diced.
[0072] For ease of illustration, the probe is not shown within FIG.
6. In any case, die 110 can be configured to implement internal
connection 515. Internal connection 515 can couple TSV 215A to TSV
2158 through micro-bumps 210. Accordingly, a test signal can be
output to package bump 220A, or alternatively, to the pad of
interposer 115 beneath package bump 220A in the event package bumps
have not yet been formed. The test signal can propagate through TSV
215A, micro-bump(s) 210 that couple die 110 to TSV 215A, through
internal connection 515, out through micro-bump(s) 210 that couple
die 110 to TSV 2158, and through TSV 2158. The probe can determine
whether the test signal is received by probing either the pad
beneath package bump 220B or package bump 220B if formed. When the
probe detects the test signal being output from multi-die IC 100
via TSV 2158, the described signal path can be determined to be
fault free.
[0073] FIG. 7 is a sixth cross-sectional side view of a multi-die
IC 700 in accordance with one or more other embodiments disclosed
within this specification. FIG. 7 illustrates a stacked die
configuration in which three or more dies, e.g., die 705, die 710,
and die 715, can be vertically stacked. Rather than using a die as
a dedicated transport mechanism, e.g., an interposer, to convey
signals among two or more dies, the dies can be stacked vertically
as shown so that no pair of dies is on a same horizontal plane as
was the case with multi-die IC 100. Rather, each of dies 705-715 is
on a unique horizontal plane.
[0074] Within multi-die IC 700, inter-die signals can be conveyed
through the use of a plurality of TSVs. Each die, with the
exception of the top die, e.g., 705, can include one or more TSVs
720. Die 710 can include TSV 720A and TSV 720B. Die 715 can include
TSVs 720C, 720D, 720E, and 720F. Multi-die IC 700 can include a
plurality of package bumps 725A-725D. Dies 705, 710, and 715 can be
coupled via a plurality of micro-bumps 730 substantially as
described within this specification.
[0075] With this configuration, die 705 can communicate with die
710 via one or more micro-bumps 730 coupling die 705 and die 710.
Similarly, die 710 can communicate with die 715 via one or more of
micro-bumps 730 coupling die 710 to die 715. Die 705 can
communicate directly with die 715 through signals passed via
micro-bump(s) 730 coupling die 705 to TSV 720A and/or TSV 720B and
through micro-bump(s) coupling TSV 720A and/or TSV 720B.
[0076] In one or more embodiments, die 705 can be coupled to
package bump 725B and/or 725C via micro-bump(s) 730 coupling die
705 to TSV 720A and/or TSV 720B, micro-bump(s) 730 coupling TSV
720A to TSV 720D and/or micro-bump(s) 730 coupling TSV 720B to TSV
720E. Similarly, die 710 can be coupled to package bumps 725A-725D
via micro-bump(s) 730 coupling die 710 to TSVs 720C-720F
respectively.
[0077] It should be appreciated that the number of micro-bumps,
TSVs, and package-bumps illustrated within FIGS. 1-7 are provided
for purposes of illustration only and are not intended to be
limiting or to suggest a particular number of the aforementioned
circuit structures. Regarding FIG. 7, for example, die 705 can be
coupled to package bumps, to die 710, as well as to die 715 using
any combination of the different connections described. With each
of dies 705-715 being larger in size, thousands of micro-bumps, for
example, can be used to form inter-die connections.
[0078] In testing the inter-die connections of multi-die IC 700,
package bumps 725 (or the pads beneath package bumps 725) can be
probed as described with reference to FIG. 6. Die 715, die 710,
and/or die 705 can be configured to form one or more internal
connections to route any received test signals back out so that a
probe can determine whether the signal path inclusive of any
intervening micro-bumps 730 and/or TSVs 720 is fault free.
[0079] In one or more embodiments, probe pads 735 can be disposed
on top of die 705. Each probe pad 735 can be coupled to, for
example, an internal node of die 705 that can, through proper
configuration of die 705, be coupled to any one of micro-bumps 730
disposed between die 705 and die 710. Accordingly, a combination of
probing package bumps 725 (or the pads disposed beneath the package
bumps 725 when not yet formed) and probe pads 735 can be
implemented to test different inter-die connections. As an example,
a signal path from package bump 725D to TSV 720F, through an
internal connection within die 710, to TSV 720E to package bump
725C can be tested. In another example, a signal path from a probe
pad 735 through die 705 to TSVs 720A and 720D, to package bump 725B
can be tested. As noted, the pads beneath each respective package
bump can be probed in the event the package bump has not yet been
formed.
[0080] FIG. 8 is a flow chart illustrating a method 800 of testing
inter-die connections within a multi-die IC in accordance with one
or more other embodiments disclosed within this specification.
Method 800 can be implemented using an IC testing system that can
perform the various functions described within this specification.
For example, the IC testing system can probe various probe pads
disposed on the dies and/or interposer of the multi-die ICs
undergoing testing, determine whether conductive paths are fault
free according to test vectors provided and received out of the
device under test, and track those particular dies and/or multi-die
ICs for which faults have been identified.
[0081] In step 805, the system can identify known good dies and
interposers. The dies and interposers, while still in wafer form,
can be tested. Dies and interposers, for example, can be tested
under different operating conditions to detect open circuits, close
circuits, or the like. For example, test circuit designs can be
instantiated within the dies. Test signals can be provided to the
dies. The output from each die can be compared with expected output
to determine whether the actual output matches the expected output
indicating a fault free state. From this sort of testing, known
good dies and known good interposers can be identified.
[0082] In step 810, the die wafers and interposer wafers can be
micro-bumped. The dies and interposers can undergo a bump formation
process where micro-bumps are formed on exposed pads of the dies
and exposed pads of the interposers. It should be appreciated that,
in some cases, testing of dies and/or interposers can be performed
subsequent to micro-bumping. In step 815, interposer wafers can be
processed for die bonding. For example, interposer wafers may have
been thinned as part of the manufacturing process to expose TSVs on
the top and on the bottom surfaces. Accordingly, the interposer
wafers can be mounted to a carrier facilitate the bonding of dies.
In step 820, the dies can be diced, e.g., separated into individual
dies. The interposers can remain in wafer form.
[0083] In step 825, known good dies can be bonded to known good
interposers. In one or more embodiments, a semi-permanent bonding
process can be used where dies are bonded by aligning micro-bumps
on the bottom of the dies with micro-bumps on the top of the
interposers. The bottom of each die can be placed on top of the top
surface of the interposer using the correct alignment, i.e., where
each micro-bump of the die is aligned with the intended or correct
micro-bump of the interposer. A semi-permanent bonding process that
causes the micro-bumps to reflow. The reflow process effectively
causes each pair of micro-bumps to form a single micro-bump,
thereby bonding the dies to the interposers.
[0084] In step 830, the system can test inter-die connections.
Inter-die connections can be tested using any of the various
testing techniques described within this specification. The
inter-die connections can be tested for faults. For example,
inter-die connections including only micro-bumps can be tested.
Inter-die connections including both micro-bumps and TSVs can be
tested. Various combinations of inter-die connections can be
tested. In step 835, the system can identify the inter-die
connections with faults. The system can determine which of the
inter-die connections experienced a fault during the testing. In
step 840, responsive to detecting a fault in an inter-die
connection, each multi-die IC determined to include a faulty
inter-die connection can be identified, or otherwise designated, as
including a faulty inter-die connection.
[0085] In step 845, multi-die ICs with faulty inter-die connections
can be reprocessed. Reprocessing can be available in selected IC
manufacturing technologies such as semi-permanent process
technologies as described with reference to step 825. For example,
faulty inter-die connections, i.e., micro-bumps, can be reflowed.
In step 850, the multi-die ICs that were reprocessed can be
retested. In step 855, an IC processing step can be implemented to
make any semi-permanent bonds between dies and interposer permanent
for those multi-die ICs that are determined to be fault free,
whether reprocessed or not. For example, a process such as
thermo-compression bonding can be implemented to make
semi-permanent inter-die connections permanent.
[0086] In step 860, those multi-die ICs that do not have faulty
inter-die connections, whether reworked or not, can undergo an
under-fill process. The under-fill process under-fills the
die-on-wafer interface of fault-free multi-die ICs. The under-fill
process can add strength to the die-on-wafer bonding achieved via
the micro-bumps. In step 865, interposer wafers can be diced to
form a plurality of separate multi-die ICs. Prior to step 865, for
example, while the multi-die ICs are formed, the multi-die ICs are
not separate and distinct since the interposers are still in wafer
form.
[0087] In step 870, packaging and assembly of the multi-die ICs can
be performed. It should be appreciated that only those multi-die
ICs formed of known good dies and known good interposers that have
been identified as having no inter-die connection faults are
packaged. In step 875, further testing of each multi-die IC in
package form can be performed.
[0088] Within this specification, the same reference characters are
used to refer to terminals, signal lines, wires, and their
corresponding signals. In this regard, the terms "signal," "wire,"
"connection," "terminal," and "pin" may be used interchangeably,
from time-to-time, within the this specification. It also should be
appreciated that the terms "signal," "wire," or the like can
represent one or more signals, e.g., the conveyance of a single bit
through a single wire or the conveyance of multiple parallel bits
through multiple parallel wires. Further, each wire or signal may
represent bi-directional communication between two, or more,
components connected by a signal or wire as the case may be.
[0089] The flowchart in the figures illustrates the architecture,
functionality, and operation of possible implementations of
systems, methods and computer program products according to one or
more embodiments disclosed within this specification. In this
regard, each block in the flowchart may represent a module,
segment, or portion of code, which comprises one or more portions
of executable program code that implements the specified logical
function(s).
[0090] It should be noted that, in some alternative
implementations, the functions noted in the blocks may occur out of
the order noted in the figures. For example, two blocks shown in
succession may, in fact, be executed substantially concurrently, or
the blocks may sometimes be executed in the reverse order,
depending upon the functionality involved. It also should be noted
that each block of the flowchart illustrations, and combinations of
blocks in the flowchart illustrations, can be implemented by
special purpose hardware-based systems that perform the specified
functions or acts, or combinations of special purpose hardware and
executable instructions.
[0091] One or more embodiments can be realized in hardware or a
combination of hardware and software. One or more embodiments can
be realized in a centralized fashion in one system or in a
distributed fashion where different elements are spread across
several interconnected systems. Any kind of data processing system
or other apparatus adapted for carrying out at least a portion of
the methods described herein is suited.
[0092] One or more embodiments further can be embedded in a device
such as a computer program product, which comprises all the
features enabling the implementation of the methods described
herein. The device can include a data storage medium, e.g., a
computer-usable or computer-readable medium, storing program code
that, when loaded and executed in a system having memory and a
processor, causes the system to perform at least a portion of the
functions described within this specification. Examples of data
storage media can include, but are not limited to, optical media,
magnetic media, magneto-optical media, computer memory such as
random access memory or hard disk(s), or the like.
[0093] The terms and/or phrases "computer program," "software,"
"application," "computer-usable program code," "program code,"
"executable code," variants and/or combinations thereof, in the
present context, mean any expression, in any language, code or
notation, of a set of instructions intended to cause a system
having an information processing capability to perform a particular
function either directly or after either or both of the following:
a) conversion to another language, code, or notation; b)
reproduction in a different material form. For example, program
code can include, but is not limited to, a subroutine, a function,
a procedure, an object method, an object implementation, an
executable application, an applet, a servlet, a source code, an
object code, a shared library/dynamic load library and/or other
sequence of instructions designed for execution on a computer
system.
[0094] The terms "a" and "an," as used herein, are defined as one
or more than one. The term "plurality," as used herein, is defined
as two or more than two. The term "another," as used herein, is
defined as at least a second or more. The terms "including" and/or
"having," as used herein, are defined as comprising, i.e., open
language. The term "coupled," as used herein, is defined as
connected, whether directly without any intervening elements or
indirectly with one or more intervening elements, unless otherwise
indicated. Two elements also can be coupled mechanically,
electrically, or communicatively linked through a communication
channel, pathway, network, or system.
[0095] One or more embodiments disclosed within this specification
can be embodied in other forms without departing from the spirit or
essential attributes thereof. Accordingly, reference should be made
to the following claims, rather than to the foregoing
specification, as indicating the scope of the one or more
embodiments.
* * * * *