SiC Crystals Having Spatially Uniform Doping Impurities

Abstract

A sublimation-grown silicon carbide (SiC) single crystal boule includes a deep level dopant introduced into the SiC single crystal boule during sublimation-growth thereof such that in a continuous section of the boule that is not less than 50% of a continuous length of said boule, the deep level dopant concentration at the boule center varies by not more than 25% from the average concentration of the deep level dopant in the continuous section of the boule.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of co-pending U.S. patent application Ser. No. 12/573,288, filed Oct. 5, 2009, which is a divisional of U.S. patent application Ser. No. 11/405,368, filed Apr. 17, 2006, now U.S. Pat. No. 7,608,524, which claims priority from U.S. Provisional Patent Application No. 60/672,945, filed Apr. 19, 2005, all of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] Unique electronic properties of silicon carbide (SiC) make it a very desirable material for state-of-the-art semiconductor devices that can operate at high frequencies, high voltages and current densities, and in harsh conditions. In many such devices, silicon carbide is utilized as a substrate on which the semiconductor device structure is formed using epitaxy, photolithography and metallization. Depending on the device design, the substrate must possess specified electronic parameters, such as conductivity type and resistivity. While devices operating at high and microwave frequencies (RF devices) require semi-insulating (SI) substrates with very high resistivity, for other devices, such as high power switching devices, low-resistivity n-type and p-type substrates are needed.

[0003] Presently, SiC single crystals are grown on the industrial scale by a sublimation technique called Physical Vapor Transport (PVT). A schematic diagram of a typical prior art PVT arrangement is shown in FIG. 1. In PVT, polycrystalline grains of silicon carbide (SiC source) 1 are loaded on the bottom of a growth container 2 and a SiC seed crystal 4 is attached to a top of growth container 2. Desirably, growth container 2 is made of a material, such as graphite, that is not reactive with SiC or any dopant (discussed hereinafter) added thereto. The loaded growth container 2 is evacuated, filled with inert gas to a certain, desired pressure and heated via at least one heating element 3 (e.g., an RF coil) to a growth temperature, e.g., between 1900.degree. C. and 2400.degree. C. Growth container 2 is heated in such a fashion that a vertical temperature gradient is created making the SiC source 1 temperature higher than that of the SiC seed 4. At high temperatures, silicon carbide of the SiC source 1 sublimes releasing a spectrum of volatile molecular species to the vapor phase. The most abundant of these gaseous species are Si, Si.sub.2C and SiC.sub.2. Driven by the temperature gradient, they are transported to the SiC seed 4 and condense on it causing growth of a SiC single crystal 5 on the SiC seed 4. Prior art patents in this area include, for example, U.S. Pat. Nos. 6,805,745; 5,683,507; 5,611,955; 5,667,587; 5,746,827; and Re. 34,861, which are all incorporated herein by reference.

[0004] Those skilled in the art of semiconductor materials know that production of SiC substrates with desirable electronic properties is impossible without purposeful introduction of certain impurities in a process known as doping. In silicon carbide, the chemical bonds are so exceptionally strong and solid-state diffusion of impurities is so slow that doping in the bulk can be accomplished only at the stage of crystal growth, when the doping element (dopant) incorporates directly into the lattice of the growing SiC crystal 5.

[0005] As a particular example of SiC doping during growth, n-type SiC crystals are produced by adding small amounts of gaseous nitrogen (N.sub.2) to growth container 2 atmosphere. Nitrogen-doped SiC single crystals with very uniform electrical properties can be readily grown by maintaining appropriate partial pressure of N.sub.2 during growth.

[0006] With the exception of the nitrogen-doped crystals, attaining uniform electrical properties in other types of SiC crystals, including semi-insulating, p-type and phosphorus doped n-type crystals, is much more difficult because the doping compounds are not gaseous but solid. Vanadium is one particularly important dopant, which is used to produce a high-resistivity semi-insulating SiC crystal. Aluminum is another important dopant used for the growth of conductive crystals of p-type. Other solid dopants include boron, phosphorus, heavy metals and rare earth elements.

[0007] Prior art doping of SiC crystals using a solid dopant is carried out by admixing small amounts of impurity directly to the SiC source 1. For instance, vanadium can be introduced in the form of elemental vanadium, vanadium carbide or vanadium silicide. Aluminum can be introduced in the elemental form, aluminum carbide or aluminum silicide. Other suitable solid dopants, such as boron or phosphorus, can be similarly introduced as elements, carbides or silicides. The doping compound can be in the physical form of powder, pieces or chips.

[0008] During SiC crystal 5 sublimation growth, multi-step chemical reactions take place between the SiC source 1 and the dopant admixed directly in the SiC source. These reactions proceed through several stages and lead to the formation of multiple intermediary compounds. In the case of vanadium doping, thermodynamic analysis shows that the product of reaction between SiC and vanadium dopant (whether elemental, carbide or silicide) depends on the stoichiometry of SiC. That is, when the SiC source 1 is Si-rich and its composition corresponds to the two-phase equilibrium between SiC and Si, formation of vanadium silicide (VSi.sub.2) is likely. When the SiC source is C-rich and its composition corresponds to the two-phase equilibrium between SiC and C, formation of vanadium carbide (VC.sub.x) is likely.

[0009] It is known that freshly synthesized SiC source 1 is, typically, Si-rich. Due to the incongruent character of SiC sublimation, the initially silicon-rich SiC source 1 gradually becomes carbon-rich. This change in the stoichiometry of the SiC source 1 during sublimation growth causes the following sequence of reactions:

[0010] During initial stages of growth, when the SiC source 1 is Si-rich, reaction between vanadium dopant and SiC yields vanadium silicide VSi.sub.2.

[0011] As the growth progresses and the SiC source 1 becomes more carbon-rich, vanadium silicide converts to intermediate carbo-silicide VC.sub.xSi.sub.y.

[0012] During final stages of growth, when the SiC source 1 is carbon-rich, vanadium carbo-silicide converts into vanadium carbide VC.sub.x.

[0013] Accordingly, the partial pressure of vanadium-bearing species in the vapor phase decreases from high at the beginning of growth to low at the end. The change in the vanadium partial pressure results in the characteristic concentration profile with too much vanadium in the first-to-grow portions of the SiC crystal 5 boule and too little in the last-to-grow portions. For this reason, electrical properties of SiC crystals grown using the doping technique of prior art are spatially nonuniform and the yield of high electronic quality substrates is low.

[0014] The above case of vanadium doping was given for the purpose of example only. Similar problems exist in the cases when other solid dopants are added to the SiC source 1 directly, including, but not limited to aluminum, boron and phosphorus.

SUMMARY OF THE INVENTION

[0015] The present invention is a system for producing spatially uniform and controlled concentration of a dopant throughout a SiC crystal boule that avoids or eliminates the too high dopant concentration in the first-to-grow boule portions and the too low dopant concentration in the last-to-grow portions. The dopant concentration can be sufficiently high to achieve the desired electronic properties of the SiC material while, at the same time, the dopant concentration can be low enough to avoid generation of crystal defects. Moreover, the dopant concentration does not change appreciably as the crystal grows. Therefore, longer boules with spatially uniform electrical properties can be grown resulting in higher quality of the SiC substrates, higher yields and productivity.

[0016] More specifically, the invention is a sublimation-grown silicon carbide (SiC) single crystal boule including a deep level dopant introduced into the SiC single crystal boule during sublimation-growth thereof such that in a continuous section of the boule that is not less than 50% of a continuous length of said boule, the deep level dopant concentration at the boule center varies by not more than 25% from the average concentration of the deep level dopant in said continuous section of the boule.

[0017] The invention is also a sublimation-grown silicon carbide (SiC) single crystal boule including a deep level dopant introduced into the SiC single crystal boule during sublimation-growth thereof such that in a sublimation-growth direction of the SiC single crystal boule a concentration of the deep level dopant in a plurality of at least 10 consecutive wafers obtained from the SiC single crystal boule varies by not more than 25% from the average concentration of the deep level dopant in any one of the plurality of wafers.

[0018] Last, the invention is a pair of silicon carbide (SiC) wafers obtained from first and second parts of a sublimation-grown SiC single crystal boule that are spaced from each other a distance no less than a thickness of at least eight other SiC wafers, wherein one of the pair of wafers has a concentration of the deep level dopant that is different from the concentration of the deep level dopant in the other of the pair of wafers by not more than 25%.

[0019] The deep level dopant is desirably vanadium. The concentration of vanadium can be between 2.times.10.sup.6 cm.sup.-3 and 2.times.10.sup.7 cm.sup.-3.

[0020] The resistivity of each of the plurality of wafers is desirably greater than about 5.times.10.sup.9 ohm-cm, is more desirably greater than about 1.times.10.sup.10 ohm-cm, is even more desirably greater than about 5.times.10.sup.10 ohm-cm, and is most desirably greater than about 1.times.10.sup.11 ohm-cm.

[0021] The plurality of wafers is desirably at least 13 wafers and is most desirably at least 17 wafers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 is a cross section of a prior art physical vapor transport arrangement;

[0023] FIG. 2 is a cross section of a time-release capsule in accordance with the present invention for use in the physical vapor transport arrangement shown in FIG. 1;

[0024] FIGS. 3a-3c are cross-sectional views of one or more capsules of FIG. 2 positioned in different locations within the physical vapor transport arrangement shown in FIG. 1;

[0025] FIG. 4 is a graph of resistivity versus wafer number for wafers sliced from a boule grown in accordance with the prior art;

[0026] FIG. 5 is a low magnification optical view of the first wafer utilized to form the plot shown in FIG. 4;

[0027] FIG. 6 is a plot of the resistivity of each wafer sliced from a boule grown in accordance with the present invention; and

[0028] FIG. 7 is another plot of the resistivity of each wafer sliced from another boule grown in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0029] With reference to FIG. 2, the advantages of spatially uniform and controlled doping are realized using a time-release capsule 14, which is loaded with a stable form of solid dopant, and placed inside growth container 2. Capsule 14 is desirably made of an inert material, which is reactive with neither SiC nor the dopant. For a majority of applications, dense and low-porosity graphite is a preferred material for capsule 14. Other possible materials include refractory metals, their carbides and nitrides. However, this is not to be construed as limiting the invention.

[0030] Capsule 14 includes a tight lid 15 having one or more calibrated through-holes or capillaries 16 of predetermined diameter and length. There are no limitations on the dimensions of capsule 14 except that it should fit inside growth container 2 and not restrict the flow of vapor to the SiC seed 4.

[0031] At a suitable time, capsule 14 is loaded with the proper amount of solid dopant 17. Dopant 17 must be either in a stable chemical form that is not reactive with the material of capsule 14 or in a form that upon reaction with the material forming capsule 14 produces a stable compound. For the majority of practical applications, the preferred forms of solid dopant are: (i) elemental form, (ii) carbide and (iii) silicide. However, this is not to be construed as limiting the invention.

[0032] During sublimation growth of the SiC crystal 5, capsule 14 is situated inside growth container 2. In one embodiment, shown in FIG. 3a, a single capsule 14 is positioned on the top surface of the SiC source 1 near the axis of growth container 2. In another embodiment, shown in FIG. 3b, several capsules 14 are positioned on the top surface of the SiC source 1 near the wall of growth container 2. In yet another embodiment, shown FIG. 3c, capsule 14 is buried within the material forming the SiC source 1.

[0033] The principle of operation of capsule 14 is based on the well-known phenomenon of effusion, i.e., the slow escape of vapor from a sealed vessel through a small orifice. At high temperatures, the vapor pressure of dopant 17 inside capsule 14 forces it to escape through each capillary 16. If the cross section of each capillary 16 is sufficiently small, the vapor pressure of dopant 17 in capsule 14 does not differ substantially from the equilibrium value.

[0034] The laws of effusion are well-known and, for given growth conditions (temperature, vapor pressure of the inert gas, volatility of the substance contained in capsule 14, capillary 16 diameter and capillary 16 length), the flux of the molecules of dopant 17 escaping capsule 14 via each capillary 16 can be readily calculated. Thus, the dimension of each capillary 16 and number of capillaries 16 can be tailored to achieve a steady and well-controlled flux of the impurity dopant 17 atoms from capsule 14 to the growing SiC crystal 5.

[0035] For relatively small doping levels, a capsule 14 having a single capillary 16 can be used (see embodiment in FIG. 3a). For higher doping levels or doping with multiple dopants 17, multiple capsules 14 can be used (see embodiment in FIG. 3b), as well as a capsule 14 with multiple capillaries. For special purposes, such as programmable or delayed doping, one or more time-release capsules 14 buried in the depth of the SiC source 1 can be utilized (see embodiment in FIG. 3c).

[0036] According to prior art SiC doping, a small amount of dopant is admixed directly to the SiC source 1 material, leading to chemical reactions between the dopant and SiC source 1. These reactions, combined with changes in the stoichiometry of the SiC source 1 material, lead to progressive changes in the partial pressure of the dopant. As a result, prior art doping produces initially high concentrations of dopant in the crystal followed by a decrease in the dopant concentration over the SiC crystal 5 length. Crystals grown according to the prior art have too high a degree of dopant in the first-to-grow sections and insufficient dopant in the last-to-grow sections. The dopant level in the first-to-grow boule sections can be so high that second-phase precipitates form in the crystal bulk leading to the generation of crystal defects.

[0037] The present invention eliminates the problems of the prior art by using one or more time-release capsules 14 for the doping of SiC crystals 5 during crystal growth. The invention has two distinct advantages:

[0038] First, the present invention eliminates direct contact between the dopant 17 and the SiC source 1. This is accomplished by placing the dopant 17 inside of a capsule 14 made of an inert material.

[0039] Second, the present invention offers a means for precise control of the dopant 17 concentration. This is achieved by choosing the number of capsules 14, the number and dimensions of the capillaries 16, and the position of each capsule 14 within growth container 2.

[0040] The present invention offers the following technical advantages over the prior art. First, it eliminates direct contact between the dopant 17 and the SiC source 1, so the transient processes associated with the chemical reactions between the dopant 17 and SiC source 1 are avoided or eliminated. Secondly, the present invention provides a means to precisely control the flux of the dopant 17 to the SiC seed 4. These technical advantages lead to the production of precisely and uniformly doped SiC crystals 5.

[0041] The direct consequence of precise and spatially uniform doping is SiC single crystals 5 with spatially uniform and controllable electrical properties. In addition to the superior electrical properties, the invention avoids or eliminates the formation of impurity precipitates and associated defects and, thus, leads to the improvement in the SiC crystal 5 quality and wafer yield.

[0042] Specifically, for a vanadium doped SiC crystal 5, the application of the present invention increases the yield of usable prime quality SiC wafers by as much as 50%. This in-turn leads to reduced costs and improved profitability.

[0043] The present invention has been applied to the growth of semi-insulating 6H--SiC single crystals doped during growth with vanadium. However, this is not to be construed as limiting the invention since it is envisioned that the invention can also be applied to the growth of 4H--SiC, 3C--SiC or 15R--SiC single crystals doped during growth with a suitable dopant. In Examples 2 and 3 below, a single time-release capsule 14 made of pure dense graphite was used. All other parameters of the SiC growth process, such as temperature, pressure, temperature gradient, etc., were in accordance with existing growth techniques used for the production of SiC crystals 5.

Example 1

[0044] In accordance with the prior art SiC crystal growth method, an appropriate amount of elemental vanadium was admixed to the SiC source 1. The SiC source/vanadium mixture and a SiC seed 4 were loaded into growth container 2 which was then evacuated and filled with an inert gas to a desired pressure. Following this, the temperature of growth container 2 was raised to a temperature sufficient to cause the growth of the SiC crystal 5.

[0045] Thereafter, the grown SiC crystal 5 boule was sliced into wafers and the impurity content for vanadium and other elements was measured using Secondary Ion Mass Spectroscopy (SIMS) in wafer #2 and wafer #17 (the last wafer in the boule). The results showed that wafer #2 contained vanadium at about 1.4.times.10.sup.17 cm.sup.-3 while wafer #17 contained vanadium at about 2.times.10.sup.14 cm.sup.-3.

[0046] With reference to FIG. 4, the resistivity of each wafer obtained from the grown boule was measured and plotted. In the plot, each point represents an average resistivity for the particular wafer. As can be seen, the resistivity of the first-to-grow wafers is very high (on the order of 2.times.10.sup.11 .OMEGA.cm) while the resistivity of the last-to-grow wafers is low, below 10.sup.5 .OMEGA.cm. One skilled in the art would immediately recognize that only those wafers that have the resistivity above 10.sup.5 .OMEGA.cm are semi-insulating and can be used in the manufacturing of RF devices, while wafers with the resistivity below 10.sup.5 .OMEGA.cm would be rejected.

[0047] Investigation under a low-magnification optical microscope of the first-to-grow wafers sliced from this boule showed that at least three of them contained precipitates of V-rich second phase (see FIG. 5). The precipitates caused generation of defects such as dislocations and micropipes, which spread from the area populated by precipitates into other parts of the boule.

[0048] Thus, prior art SiC doping causes nonuniform distribution of dopant, spatially nonuniform electrical properties, and formation of crystal defects.

Example 2

[0049] In accordance with a SiC crystal growth method of the present invention, a capsule 14 having a capillary 16 of 1.5 mm in diameter and 6 mm long was loaded with 1 g of pure vanadium carbide (VC.sub.0.88, 99.999+%). Capsule 14 was positioned atop the SiC source 1 in growth container 2. All other parameters of this growth run were in accordance with existing standard technological procedures.

[0050] After finishing this growth run and cooling to room temperature, capsule 14 was recovered and its content investigated. A pellet of sintered vanadium carbide was found inside capsule 14. Chemical analysis of the pellet showed that it consisted of vanadium and carbon in the stoichiometric ratio of VC.sub.x (x.apprxeq.0.8) with traces of silicon accounting for less than 3 weight %. Thus, there was no major chemical transformation in capsule 14 during growth, and vanadium was preserved in its stable form of vanadium carbide. The traces of silicon could be a result of silicon diffusion through the capsule wall or silicon vapor back streaming through the capillary 16. Both these marginal processes could not change significantly the composition of the dopant 17 in capsule 14.

[0051] The grown boule was sliced into wafers, two of which, wafer #03 (near the SiC seed 4) and wafer #15 (near the boule dome), were analyzed for impurity content using SIMS. The results showed that wafer #03 contained vanadium at a level of 2.90.times.10.sup.16 cm.sup.-3 while wafer #15 contained vanadium at a level of 2.34.times.10.sup.16 cm.sup.-3. Investigation under a microscope found no precipitates of secondary phases. Moreover, the density of micropipes and other defects in this boule was observed to be low.

[0052] With reference to FIG. 6, the resistivity of each wafer obtained from the boule grown in accordance with this Example 2 was measured and plotted. In the plot, each point represents an average resistivity for the particular wafer. As can be seen, the resistivity of all 15 wafers sliced from this boule was close to 1.7.times.10.sup.11 .OMEGA.cm, with no visible decrease in the last-to-grow wafers.

Example 3

[0053] In accordance with a SiC crystal growth method of the present invention, a capsule 14 having a capillary 16 of 1.5 mm in diameter and 6 mm long was loaded with 1 g of elemental vanadium of 99.995% purity. Capsule 14 was positioned atop the SiC source 1 in growth container 2. All other parameters of this growth run were in accordance with existing standard technological procedures.

[0054] After finishing this growth run and cooling to room temperature, the capsule content was investigated. It was found that during heating to the growth temperature, vanadium melted and reacted with carbon of the capsule wall to form stable vanadium carbide, VC.sub.x with x.apprxeq.0.9. No further chemical transformations occurred during growth cycle.

[0055] The grown boule was sliced into wafers, two of which, wafer #03 and wafer #17 (the last wafer of the boule), were analyzed for impurity content using SIMS. The results showed that wafer #03 contained vanadium at a level of 3.4.times.10.sup.16 cm.sup.-3 while wafer #17 contained vanadium at a level of about 2.7.times.10.sup.16 cm.sup.-3.

[0056] The resistivity in the wafers sliced from this boule was so high that it exceeded the upper sensitivity limit of the measuring instrument. Accordingly, the resistivity data is plotted in FIG. 7 as empty circles at 10.sup.12 .OMEGA.cm indicating that the actual resistivity is higher. These values of resistivity exceeded by several orders of magnitude the current requirements for semi- insulating SiC substrates.

[0057] The level of vanadium in this boule was high enough to cause full electrical compensation, but much lower than the solubility limit, so no precipitates of secondary phases were formed. The grown boule was of good crystal quality with low densities of micropipes and other defects.

[0058] The invention has been described with reference to the preferred embodiments. Obvious modifications and alterations will occur to others upon reading and understanding the preceding detailed description. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A sublimation-grown silicon carbide (SiC) single crystal boule including a deep level dopant introduced into the SiC single crystal boule during sublimation-growth thereof such that in a continuous section of the boule that is not less than 50% of a continuous length of said boule, the deep level dopant concentration at the boule center varies by not more than 25% from the average concentration of the deep level dopant in said continuous section of the boule.

2. The SiC boule of claim 1, wherein the deep level dopant is vanadium.

3. The SiC boule of claim 2, wherein the concentration of vanadium is between 2.times.10.sup.6 cm.sup.-3 and 2.times.10.sup.7 cm.sup.-3.

4. The SiC boule of claim 1, wherein a resistivity of each of a plurality of wafers obtained from the boule is greater than about 5.times.10.sup.9 ohm-cm.

5. The SiC boule of claim 1, wherein a resistivity of each of a plurality of wafers obtained from the boule is greater than about 1.times.10.sup.10 ohm-cm.

6. The SiC boule of claim 1, wherein a resistivity of each of a plurality of wafers obtained from the boule is greater than about 5.times.10.sup.10 ohm-cm.

7. The SiC boule of claim 1, wherein a resistivity of each of a plurality of wafers obtained from the boule is greater than about 1.times.10.sup.11 ohm-cm.

8. The SiC boule of claim 1, wherein at least 10 wafers are obtained from the boule.

9. The SiC boule of claim 1, wherein at least 13 wafers are obtained from the boule.

10. The SiC boule of claim 1, wherein at least 17 wafers are obtained from the boule.

11. A sublimation-grown silicon carbide (SiC) single crystal boule including a deep level dopant introduced into the SiC single crystal boule during sublimation-growth thereof such that in a sublimation-growth direction of the SiC single crystal boule a concentration of the deep level dopant in a plurality of at least 10 consecutive wafers obtained from the SiC single crystal boule varies by not more than 25% from the average concentration of the deep level dopant in any one of the plurality of wafers.

12. The SiC boule of claim 11, wherein the deep level dopant is vanadium.

13. The SiC boule of claim 12, wherein the concentration of vanadium is between 2.times.10.sup.6 cm.sup.-3 and 2.times.10.sup.7 cm.sup.-3.

14. The SiC boule of claim 11, wherein the resistivity of each of the plurality of wafers is greater than about 5.times.10.sup.9 ohm-cm.

15. The SiC boule of claim 11, wherein the resistivity of each of the plurality of wafers is greater than about 1.times.10.sup.10 ohm-cm.

16. The SiC boule of claim 11, wherein the resistivity of each of the plurality of wafers is greater than about 5.times.10.sup.10 ohm-cm.

17. The SiC boule of claim 11, wherein the resistivity of each of the plurality of wafers is greater than about 1.times.10.sup.11 ohm-cm.

18. The SiC boule of claim 11, wherein the plurality of wafers is at least 13 wafers.

19. The SiC boule of claim 11, wherein the plurality of wafers is desirably at least 17 wafers.

20. A pair of silicon carbide (SiC) wafers obtained from first and second parts of a sublimation-grown SiC single crystal boule that are spaced from each other a distance no less than a thickness of at least eight other SiC wafers, wherein one of the pair of wafers has a concentration of the deep level dopant that is different from the concentration of the deep level dopant in the other of the pair of wafers by not more than 25%.

21. The SiC wafers of claim 20, wherein the deep level dopant is vanadium.

22. The SiC wafers of claim 21, wherein the concentration of vanadium is between 2.times.10.sup.6 cm.sup.-3 and 2.times.10.sup.7 cm.sup.-3.

23. The SiC boule of claim 20, wherein the resistivity of each of the plurality of wafers is greater than about 5.times.10.sup.9 ohm-cm.

24. The SiC boule of claim 20, wherein the resistivity of each of the plurality of wafers is greater than about 1.times.10.sup.10 ohm-cm.

25. The SiC boule of claim 20, wherein the resistivity of each of the plurality of wafers is greater than about 5.times.10.sup.10 ohm-cm.

26. The SiC boule of claim 20, wherein the resistivity of each of the plurality of wafers is greater than about 1.times.10.sup.11 ohm-cm.

27. The SiC boule of claim 20, wherein the plurality of wafers is at least 13 wafers.

28. The SiC boule of claim 20, wherein the plurality of wafers is desirably at least 17 wafers.