U.S. patent application number 12/750340 was filed with the patent office on 2011-10-06 for metal gate fill by optimizing etch in sacrificial gate profile.
This patent application is currently assigned to GLOBALFOUNDRIES Inc. Invention is credited to Man Fai Ng, Bin Yang.
Application Number | 20110241118 12/750340 |
Document ID | / |
Family ID | 44708643 |
Filed Date | 2011-10-06 |
United States Patent
Application |
20110241118 |
Kind Code |
A1 |
Ng; Man Fai ; et
al. |
October 6, 2011 |
METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
Abstract
A high-k metal gate electrode is formed with reduced gate voids.
An embodiment includes forming a replaceable gate electrode, for
example of amorphous silicon, having a top surface and a bottom
surface, the top surface being larger than the bottom surface,
removing the replaceable gate electrode, forming a cavity having a
top opening larger than a bottom opening, and filling the cavity
with metal. The larger top surface may be formed by etching the
bottom portion of the amorphous silicon at greater temperature than
the top portion, or by doping the top and bottom portions of the
amorphous silicon differently such that the bottom has a greater
lateral etch rate than the top.
Inventors: |
Ng; Man Fai; (Poughkeepsie,
NY) ; Yang; Bin; (Mahwah, NJ) |
Assignee: |
GLOBALFOUNDRIES Inc
Grand Cayman
KY
|
Family ID: |
44708643 |
Appl. No.: |
12/750340 |
Filed: |
March 30, 2010 |
Current U.S.
Class: |
257/364 ;
257/E21.158; 257/E29.134; 257/E29.255; 438/595 |
Current CPC
Class: |
H01L 29/66545 20130101;
H01L 29/6659 20130101; H01L 21/28114 20130101; H01L 29/7833
20130101; H01L 29/42376 20130101 |
Class at
Publication: |
257/364 ;
438/595; 257/E29.255; 257/E29.134; 257/E21.158 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 21/28 20060101 H01L021/28; H01L 29/78 20060101
H01L029/78 |
Claims
1. A method of fabricating a semiconductor device, the method
comprising: forming a replaceable gate electrode having a top
surface and a bottom surface, the top surface being larger than the
bottom surface; removing the replaceable gate electrode, forming a
cavity having a top opening larger than a bottom opening; and
filling the cavity with metal.
2. The method according to claim 1, comprising forming the
replaceable gate electrode by: forming a layer of amorphous silicon
on a substrate, the layer of amorphous silicon having a top surface
and a bottom surface; and etching the amorphous silicon layer such
that the top surface is larger than the bottom surface.
3. The method according to claim 2, comprising: etching the top
portion of the amorphous silicon at a first temperature; and
etching the bottom portion of the amorphous silicon at a second
temperature greater than the first.
4. The method according to claim 3, wherein the depth of the top
portion comprises about one half a thickness of the amorphous
silicon layer.
5. The method according to claim 3, wherein: the first temperature
is about room temperature; and the second temperature is about
350.degree. C. to about 400.degree. C.
6. The method according to claim 3, comprising etching the
amorphous silicon by reactive ion etching.
7. The method according to claim 3, further comprising forming an
oxide sidewall on the etched top portion prior to etching the
bottom portion.
8. The method according to claim 2, further comprising implanting
Boron (B) dopant increasing in concentration from a first
concentration, at the bottom surface, to a second concentration,
greater than the first, at the top surface.
9. The method according to claim 8, wherein the second
concentration is about four orders of magnitude greater than the
first concentration.
10. The method according to claim 9, further comprising applying
different energies for doping the top and bottom portions.
11. The method according to claim 2, the method further comprising
in-situ doping the amorphous silicon layer with a dopant to form a
concentration gradient of the dopant between the top surface and
the bottom surface.
12. The method according to claim 11, wherein the dopant comprises
B, and the concentration near the top surface is greater than the
concentration near the bottom surface.
13. The method according to claim 11, wherein the dopant comprises
phosphorus (P), and the concentration near the top surface is less
than the concentration near the bottom surface.
14. A semiconductor device comprising: a silicon substrate; and a
metal gate electrode formed on the silicon substrate, the metal
gate electrode having a top surface, a bottom surface smaller than
the top surface, and side surfaces.
15. The semiconductor device according to claim 14, wherein the
side surfaces of the metal gate electrode form an angle of about
80.degree. to about 85.degree. with the top surface.
16. The semiconductor device according to claim 14, further
comprising sidewall spacers on side surfaces of the metal gate
electrode, wherein the metal gate electrode comprises a replacement
gate electrode formed by depositing titanium nitride (TiN) or
aluminum (Al) between the sidewall spacers.
17. A method of fabricating a semiconductor, the method comprising:
forming a layer of amorphous silicon on a substrate, the amorphous
silicon layer having a top portion and a bottom portion, and side
surfaces; differentially etching the top portion and the bottom
portion to form a replaceable gate electrode having a top surface
larger than a bottom surface; forming sidewall spacers on the side
surfaces of the amorphous silicon layer; removing the amorphous
silicon, forming a cavity between the sidewall spacers having a top
opening larger than a bottom opening; and filling the cavity with
metal to form a high-k metal gate electrode.
18. The method according to claim 17, comprising: etching the top
portion at about room temperature; forming a protective oxide
sidewall at a thickness of about 1 nm to about 3 nm on the etched
top portion; and etching the second portion at about 350.degree. C.
to about 400.degree. C.
19. The method according to claim 17, comprising implanting a B
dopant in the amorphous silicon, prior to etching, such that the
top portion comprises a higher concentration of B than the bottom
portion.
20. The method according to claim 17, comprising doping the
amorphous silicon in situ with a dopant, such that the dopant
exhibits a concentration gradient between the top and bottom
surfaces of the amorphous silicon layer.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to semiconductor devices with
replacement metal gate electrodes. The present disclosure is
particularly applicable to 32 nanometer (nm) technology nodes and
beyond.
BACKGROUND
[0002] Gate last high-k metal gate (HKMG), also called replacement
gate, techniques have been developed to address problems attendant
upon substituting metal gate electrodes for polysilicon gate
electrodes. For example, an amorphous silicon (a-Si) or polysilicon
gate is used during initial processing until high temperature
annealing to activate source/drain implants has been implemented.
Subsequently, the a-Si or polysilicon is removed and replaced with
a metal gate.
[0003] Replacement gates are being employed, especially in 32 nm,
28 nm, and 22 nm technology nodes. However, "metal gate voids"
result from the gate metal fill processes, particularly at such
small pitches. Adverting to FIG. 1, after polysilicon has been
removed, the gate profile 101 exhibits a bottle-neck shape 103 at
the top. During the metal fill process, the bottle-neck part
"pinches-off" by the gate metal (titanium nitride (TiN) barrier 105
and aluminum (Al) 107) before the bottom of the gate is completely
filled with metal. Also, TiN and aluminum Al tend to fill thicker
at the top of the gate than at the bottom of the gate. This causes
incomplete metal-gate fill, or voids 109 in the metal gate. Voids
cause work function issues, such as variations in V.sub.t, as well
as high gate resistance and ac R.sub.eff penalty.
[0004] Attempts have been made to fabricate substantially vertical
gate profiles to eliminate voids. However, a vertical profile is
difficult to obtain with a reactive ion etch (RIE) process. Further
attempts have been made to fill the barrier metal and Al gate metal
substantially conformally to eliminate voids. However, TiN and Al
(especially Al) do not readily fill conformally.
[0005] A need therefore exists for improved methodology enabling
formation of void-free metal gates.
SUMMARY
[0006] An aspect of the present disclosure is a semiconductor
device having a gate electrode with a critical dimension larger at
a top surface than near a bottom surface.
[0007] Another aspect of the present disclosure is a method of
fabricating a semiconductor device having a gate electrode with a
critical dimension larger at a top surface than near a bottom
surface.
[0008] Additional aspects and other features of the present
disclosure will be set forth in the description which follows and
in part will be apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the present disclosure. The advantages of the present
disclosure may be realized and obtained as particularly pointed out
in the appended claims.
[0009] According to the present disclosure, some technical effects
may be achieved in part by a method comprising: forming a
replaceable gate electrode having a top surface and a bottom
surface, the top surface being larger than the bottom surface;
removing the replaceable gate electrode, forming a cavity having a
top opening larger than a bottom opening; and filling the cavity
with metal.
[0010] Aspects of the present disclosure include forming a layer of
amorphous silicon on a substrate, the layer of amorphous silicon
having a top surface and a bottom surface; and etching the
amorphous silicon layer such that the top surface is larger than
the bottom surface. Further aspects include etching the top portion
of the amorphous silicon at a first temperature; and etching the
bottom portion of the amorphous silicon at a second temperature
greater than the first. Other aspects include the depth of the top
portion comprising about one half a thickness of the amorphous
silicon layer. Additional aspects include the first temperature
being about room temperature; and the second temperature being
about 350.degree. C. to about 400.degree. C. Another aspect
includes etching the amorphous silicon by reactive ion etching.
Further aspects include forming an oxide sidewall on the etched top
portion prior to etching the bottom portion. Other aspects include
implanting Boron (B) dopant increasing in concentration from a
first concentration, at the bottom surface, to a second
concentration, greater than the first, at the top surface.
Additional aspects include the second concentration being about
four orders of magnitude greater than the first concentration.
Another aspect includes applying different energies for doping the
top and bottom portions. Other aspects include the amorphous
silicon layer having a top surface and a bottom surface, the method
further comprising in-situ doping the amorphous silicon layer with
a dopant to form a concentration gradient of the dopant between the
top surface and the bottom surface. Further aspects include the
dopant comprising B, and the concentration near the top surface
being greater than the concentration near the bottom surface.
Additional aspects include the dopant comprising phosphorus (P),
and the concentration near the top surface being less than the
concentration near the bottom surface.
[0011] Another aspect of the present disclosure is a device
comprising: a silicon substrate; and a metal gate electrode formed
on the silicon substrate, the metal gate electrode having a top
surface, a bottom surface smaller than the top surface, and side
surfaces.
[0012] Aspects include the side surfaces of the metal gate
electrode forming an angle of about 80.degree. to about 85.degree.
with the top surface. Further aspects include sidewall spacers on
side surfaces of the metal gate electrode, wherein the metal gate
electrode comprises a replacement gate electrode formed by
depositing titanium nitride (TiN) or aluminum (Al) between the
sidewall spacers.
[0013] Another aspect of the present disclosure is a method
comprising: forming a layer of amorphous silicon on a substrate,
the amorphous silicon layer having a top portion and a bottom
portion, and side surfaces; differentially etching the top portion
and the bottom portion to form a replaceable gate electrode having
a top surface larger than a bottom surface; forming sidewall
spacers on the side surfaces of the amorphous silicon layer;
removing the amorphous silicon, forming a cavity between the
sidewall spacers having a top opening larger than a bottom opening;
and filling the cavity with metal to form a high-k metal gate
electrode.
[0014] Further aspects include etching the top portion at about
room temperature; forming a protective oxide sidewall at a
thickness of about 1 nm to about 3 nm on the etched top portion;
and etching the second portion at about 350.degree. C. to about
400.degree. C. Additional aspects include implanting a B dopant in
the amorphous silicon, prior to etching, such that the top portion
comprises a higher concentration of B than the bottom portion.
Another aspect includes doping the amorphous silicon in situ with a
dopant, such that the dopant exhibits a concentration gradient
between the top and bottom surfaces of the amorphous silicon
layer.
[0015] Additional aspects and technical effects of the present
disclosure will become readily apparent to those skilled in the art
from the following detailed description wherein embodiments of the
present disclosure are described simply by way of illustration of
the best mode contemplated to carry out the present disclosure. As
will be realized, the present disclosure is capable of other and
different embodiments, and its several details are capable of
modifications in various obvious respects, all without departing
from the present disclosure. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The present disclosure is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawing and in which like reference numerals refer to similar
elements and in which:
[0017] FIG. 1 schematically illustrates a prior art gate electrode
with metal gate voids;
[0018] FIGS. 2A to 2G schematically illustrate sequential steps of
a method in accordance with an exemplary embodiment; and
[0019] FIGS. 3A to 3G schematically illustrate sequential steps of
a method in accordance with another exemplary embodiment.
DETAILED DESCRIPTION
[0020] In the following description, for the purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of exemplary embodiments. It
should be apparent, however, that exemplary embodiments may be
practiced without these specific details or with an equivalent
arrangement. In other instances, well-known structures and devices
are shown in block diagram form in order to avoid unnecessarily
obscuring exemplary embodiments.
[0021] The present disclosure addresses and solves the metal gate
void problems attendant upon forming replacement gate electrodes.
In accordance with embodiments of the present disclosure, a
sacrificial gate profile is formed with a larger critical dimension
at the top of the gate than at the bottom of the gate.
Consequently, after the sacrificial gate material is removed, a
bottleneck is not formed at the top, and the gate metal fills the
gate uniformly. Accordingly, voids in the metal gate can be
eliminated.
[0022] Methodology in accordance with embodiments of the present
disclosure includes forming a replaceable gate electrode having a
top surface and a bottom surface, the top surface being larger than
the bottom surface, removing the replaceable gate electrode,
forming a cavity having a top opening larger than a bottom opening,
and filling the cavity with metal.
[0023] Still other aspects, features, and technical effects will be
readily apparent to those skilled in this art from the following
detailed description, wherein preferred embodiments are shown and
described, simply by way of illustration of the best mode
contemplated. The disclosure is capable of other and different
embodiments, and its several details are capable of modifications
in various obvious respects. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
[0024] FIGS. 2A through 2G schematically illustrate sequential
steps of a method in accordance with an exemplary embodiment.
Adverting to FIG. 2A, after gate dielectric 201, for example an
oxide layer, TiN layer 203, and amorphous silicon (a-Si) layer 205
are formed on silicon substrate 207, a hard mask 209, for example
of silicon nitride (SiN) is formed and patterned on a-Si layer
205.
[0025] A first anisotropic RIE etches approximately half way into
the a-Si, using hard mask 209 as a mask, as illustrated in FIG. 2B.
The RIE process may take place with the chuck in the etch chamber
at about room temperature (between about 21.degree. C. and about
25.degree. C.).
[0026] As shown in FIG. 2C, a thin oxide 211, is formed on the side
surface of the etched a-Si. Oxide 211 may be formed, for example,
at a thickness of a few nanometers or less, e.g., about 1 nm to
about 3 nm. The oxide sidewall protects the top portion of the a-Si
to minimize lateral etch during subsequent etching. During the
sidewall thin oxide 211 formation, an oxide layer may also be
formed on the remaining silicon surface. However, the directional
nature of RIE will remove that layer but not the sidewall
oxide.
[0027] Etching of a-Si layer 205, as well as TiN layer 203 and gate
dielectric 201, continues with a second RIE step. A higher chuck
temperature, for example 350.degree. C. to about 400.degree. C., is
employed, thereby causing more lateral undercut to the bottom
portion of a-Si, i.e., the portion without oxide sidewall
protection. Accordingly, the resulting profile, illustrated in FIG.
2D, is narrower at the bottom than at the top. For example, the
bottom may be about 30 nm, and the sides of a-Si may form an angle
213 with substrate 207 of about 80.degree. to about 85.degree..
After the etching is complete, the oxide sidewall may be removed by
DHF clean.
[0028] Subsequently, conventional processing continues with the
formation of spacers 211 and source/drain 213 (shown in FIG. 2E),
removal of hard mask 209 and a-Si 205 (shown in FIG. 2F), and
filling of the gate with metal, such as aluminum. The larger
opening at the top of the gate makes the gate metal fill process
much easier, such that a void free gate 215 may be formed, as
illustrated in FIG. 2G.
[0029] FIGS. 3A to 3G schematically illustrate sequential steps of
a method in accordance with another exemplary embodiment. Adverting
to FIG. 3A, gate dielectric 301, for example an oxide layer, TiN
layer 303, and a-Si layer 305 are formed on silicon substrate 307.
As illustrated in FIG. 3B, a-Si layer 305 is implanted with a
dopant, for example B. Through single or multiple energy and dose
implants, a higher concentration of dopant in top portion 309 than
in bottom portion 311. Top portion 309 may be implanted with a B
concentration about four orders of magnitude greater than the
bottom portion, for example a concentration of about 1E21 to about
1E22, versus about 1E18 for the bottom portion.
[0030] A hard mask 313 is formed on doped a-Si layer 305, as
illustrated in FIG. 3C. a-Si layer 305 is then etched using hard
mask 313 as a mask. Since the silicon etch rate reduces
monotonously with increasing B concentration, by tailoring the
dopant profile implanted into the a-Si gate, a larger critical
dimension (via a smaller lateral etch) can be created at the top of
the gate than at the bottom of the gate. The result is illustrated
in FIG. 3D.
[0031] Alternatively, instead of doping a-Si layer 305 after
forming the layer, doping may be performed in situ during formation
of the layer. Relative dopant concentrations may be selected
according to whether the dopant enhances or reduces the lateral
etch rate. For example, top portion 309 may be doped with a higher
concentration of B dopant, which reduces the lateral etch rate, or
with a lower concentration of P dopant, which enhances lateral etch
rate. With the resultant concentration gradient of dopant, a-Si
layer 305 etches more at the bottom portion than at the top
portion, thereby creating a larger critical dimension at the top of
the gate than at the bottom of the gate, as shown in FIG. 3D.
[0032] After the a-Si gate is formed as illustrated in FIG. 3D,
conventional processing continues with the formation of spacers 315
and source/drain 317 (shown in FIG. 3E), removal of hard mask 313
and a-Si 305 (shown in FIG. 2F), and filling of the gate with
metal, such as aluminum. Because of the larger opening at the top
of the gate, the metal fills the opening more evenly such that a
void free gate 319 may be formed, as illustrated in FIG. 3G.
[0033] The embodiments of the present disclosure can achieve
several technical effects, including void free metal gates, which
in turn reduces V.sub.t variations, gate resistance, and ac
R.sub.eff penalty. The present disclosure enjoys industrial
applicability in any of various types of highly integrated
semiconductor devices, particularly 32 nm nodes and beyond.
[0034] In the preceding description, the present disclosure is
described with reference to specifically exemplary embodiments
thereof. It will, however, be evident that various modifications
and changes may be made thereto without departing from the broader
spirit and scope of the present disclosure, as set forth in the
claims. The specification and drawings are, accordingly, to be
regarded as illustrative and not as restrictive. It is understood
that the present disclosure is capable of using various other
combinations and embodiments and is capable of any changes or
modifications within the scope of the inventive concept as
expressed herein.
* * * * *