loadpatents
name:-0.10017418861389
name:-0.36360907554626
name:-0.034377098083496
NG; Man Fai Patent Filings

NG; Man Fai

Patent Applications and Registrations

Patent applications and USPTO patent grants for NG; Man Fai.The latest application filed is for "etsoi with reduced extension resistance".

Company Profile
0.22.20
  • NG; Man Fai - Niskayuna NY
  • Ng; Man Fai - Poughkeepsie NY US
  • Ng; Man-Fai - Plano TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Etsoi With Reduced Extension Resistance
App 20160260841 - YANG; Bin ;   et al.
2016-09-08
Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor material
Grant 8,987,110 - Ng , et al. March 24, 2
2015-03-24
Methods Of Manufacturing Integrated Circuits Having A Compressive Nitride Layer
App 20140183720 - Beasor; Scott ;   et al.
2014-07-03
Metal gate fill by optimizing etch in sacrificial gate profile
Grant 8,765,537 - Ng , et al. July 1, 2
2014-07-01
Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devices
Grant 8,680,624 - Ng , et al. March 25, 2
2014-03-25
Semiconductor devices having stressor regions and related fabrication methods
Grant 8,674,438 - Yang , et al. March 18, 2
2014-03-18
Etsoi With Reduced Extension Resistance
App 20130320447 - YANG; Bin ;   et al.
2013-12-05
Short Channel Semiconductor Devices With Reduced Halo Diffusion
App 20130249000 - Yang; Bin ;   et al.
2013-09-26
ETSOI with reduced extension resistance
Grant 8,518,758 - Yang , et al. August 27, 2
2013-08-27
Semiconductor Devices Having Stressor Regions And Related Fabrication Methods
App 20130153927 - Yang; Bin ;   et al.
2013-06-20
Short channel semiconductor devices with reduced halo diffusion
Grant 8,445,342 - Yang , et al. May 21, 2
2013-05-21
Semiconductor devices having stressor regions and related fabrication methods
Grant 8,394,691 - Yang , et al. March 12, 2
2013-03-12
Gate etch optimization through silicon dopant profile change
Grant 8,390,042 - Ng , et al. March 5, 2
2013-03-05
Metal Gate Fill By Optimizing Etch In Sacrificial Gate Profile
App 20130005128 - NG; Man Fai ;   et al.
2013-01-03
eFUSE enablement with thin polysilicon or amorphous-silicon gate-stack for HKMG CMOS
Grant 8,329,515 - Yang , et al. December 11, 2
2012-12-11
Methods For Forming Barrier Regions Within Regions Of Insulating Material Resulting In Outgassing Paths From The Insulating Material And Related Devices
App 20120235237 - NG; Man Fai ;   et al.
2012-09-20
Semiconductor Device Fabrication Method For Improved Isolation Regions And Defect-free Active Semiconductor Material
App 20120220095 - NG; Man Fai ;   et al.
2012-08-30
Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devices
Grant 8,222,093 - Ng , et al. July 17, 2
2012-07-17
Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor material
Grant 8,198,170 - Ng , et al. June 12, 2
2012-06-12
Gate Etch Optimization Through Silicon Dopant Profile Change
App 20120119308 - NG; Man Fai ;   et al.
2012-05-17
Semiconductor Device Fabrication Method For Improved Isolation Regions And Defect-free Active Semiconductor Material
App 20120094466 - NG; Man Fai ;   et al.
2012-04-19
Gate etch optimization through silicon dopant profile change
Grant 8,124,515 - Ng , et al. February 28, 2
2012-02-28
Short Channel Semiconductor Devices With Reduced Halo Diffusion
App 20110316093 - Yang; Bin ;   et al.
2011-12-29
Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
Grant 8,084,828 - Pal , et al. December 27, 2
2011-12-27
Semiconductor Devices Having Stressor Regions And Related Fabrication Methods
App 20110303954 - YANG; Bin ;   et al.
2011-12-15
Metal Gate Fill By Optimizing Etch In Sacrificial Gate Profile
App 20110241118 - Ng; Man Fai ;   et al.
2011-10-06
Etsoi With Reduced Extension Resistance
App 20110227157 - Yang; Bin ;   et al.
2011-09-22
Methods For Forming Barrier Regions Within Regions Of Insulating Material Resulting In Outgassing Paths From The Insulating Material And Related Devices
App 20110198694 - NG; Man Fai ;   et al.
2011-08-18
eFUSE ENABLEMENT WITH THIN POLYSILICON OR AMORPHOUS-SILICON GATE-STACK FOR HKMG CMOS
App 20110156146 - Yang; Bin ;   et al.
2011-06-30
Gate Etch Optimization Through Silicon Dopant Profile Change
App 20100295103 - Ng; Man Fai ;   et al.
2010-11-25
Methods For Protecting Gate Stacks During Fabrication Of Semiconductor Devices And Semiconductor Devices Fabricated From Such Methods
App 20100244156 - Pal; Rohit ;   et al.
2010-09-30
Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
Grant 7,763,508 - Pal , et al. July 27, 2
2010-07-27
Methods For Protecting Gate Stacks During Fabrication Of Semiconductor Devices And Semiconductor Devices Fabricated From Such Methods
App 20100109056 - PAL; Rohit ;   et al.
2010-05-06
Semiconductor Device With Improved Contact Plugs, And Related Fabrication Methods
App 20100072623 - PRINDLE; Christopher M. ;   et al.
2010-03-25
Microcell frequency planning
Grant 5,822,698 - Tang , et al. October 13, 1
1998-10-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed