U.S. patent application number 13/152971 was filed with the patent office on 2011-09-22 for semiconductor device and method for manufacturing a semiconductor device.
This patent application is currently assigned to INFINEON TECHNOLOGIES AG. Invention is credited to Christoph Kutter, Georg Meyer-Berg, Ewald Soutschek.
Application Number | 20110227204 13/152971 |
Document ID | / |
Family ID | 40719582 |
Filed Date | 2011-09-22 |
United States Patent
Application |
20110227204 |
Kind Code |
A1 |
Kutter; Christoph ; et
al. |
September 22, 2011 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR
DEVICE
Abstract
A semiconductor device includes a semiconductor chip including a
first conducting element, and a second conducting element arranged
outside the semiconductor chip and electrically connected to the
first conducting element at a first location. It further includes a
third conducting element arranged outside the semiconductor chip
and electrically connected to the first conducting element at a
second location, and a fourth conducting element arranged outside
the semiconductor chip. An encapsulating body encapsulates the
semiconductor chip. A vertical projection of the fourth conducting
element on the chip crosses the first conducting element between
the first location and the second location. At least one of the
second conducting element, third conducting element, and fourth
conducting element extend over the semiconductor chip and the
encapsulating body.
Inventors: |
Kutter; Christoph; (Munich,
DE) ; Soutschek; Ewald; (Neubiberg, DE) ;
Meyer-Berg; Georg; (Munich, DE) |
Assignee: |
INFINEON TECHNOLOGIES AG
Neubiberg
DE
|
Family ID: |
40719582 |
Appl. No.: |
13/152971 |
Filed: |
June 3, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11965081 |
Dec 27, 2007 |
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13152971 |
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Current U.S.
Class: |
257/666 ;
257/E21.508; 257/E21.702; 257/E23.033; 438/112; 438/123 |
Current CPC
Class: |
H01L 2924/01068
20130101; H01L 2924/014 20130101; H01L 24/19 20130101; H01L
2224/0401 20130101; H01L 23/50 20130101; H01L 21/568 20130101; H01L
23/48 20130101; H01L 2224/92 20130101; H01L 2924/01013 20130101;
H01L 2924/19042 20130101; H01L 2924/181 20130101; H01L 2224/12105
20130101; H01L 2924/15313 20130101; H01L 2224/20 20130101; H01L
2924/15174 20130101; H01L 2924/15311 20130101; H01L 23/12 20130101;
H01L 23/5389 20130101; H01L 2924/19104 20130101; H01L 24/14
20130101; H01L 2224/16235 20130101; H01L 24/06 20130101; H01L
2224/16227 20130101; H01L 2924/15312 20130101; H01L 24/96 20130101;
H01L 21/6835 20130101; H01L 23/5381 20130101; H01L 2924/01005
20130101; H01L 2924/01029 20130101; H01L 2224/04105 20130101; H01L
2924/19015 20130101; H01L 2224/92 20130101; H01L 2224/96 20130101;
H01L 2224/82 20130101; H01L 2924/181 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
257/666 ;
438/112; 438/123; 257/E23.033; 257/E21.508; 257/E21.702 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 21/786 20060101 H01L021/786; H01L 21/60 20060101
H01L021/60 |
Claims
1. A semiconductor device comprising: a semiconductor chip
comprising a first conducting element; a second conducting element
arranged outside the semiconductor chip and electrically connected
to the first conducting element at a first location; and a third
conducting element arranged outside the semiconductor chip and
electrically connected to the first conducting element at a second
location; and a fourth conducting element arranged outside the
semiconductor chip; an encapsulating body encapsulating the
semiconductor chip, wherein a vertical projection of the fourth
conducting element on the chip crosses the first conducting element
between the first location and the second location, and wherein at
least one of the second conducting element, third conducting
element and fourth conducting element extend over the semiconductor
chip and the encapsulating body.
2. The semiconductor device according to claim 1, further
comprising an insulating layer arranged between the first
conducting element and at least one of the second conducting
element, third conducting element and fourth conducting
element.
3. The semiconductor device according to claim 1, wherein the
second conducting element, third conducting element and fourth
conducting element are formed from a common conducting layer.
4. The semiconductor device according to claim 1, further
comprising external connection elements electrically connected to
at least one of the second conducting element, third conducting
element and fourth conducting element.
5. The semiconductor device according to claim 4, wherein the
external connection elements are solder bumps.
6. The semiconductor device according to claim 4, wherein the
external connection elements are located at positions defining an
array.
7. The semiconductor device according to claim 1, wherein at least
one of the first, second, third and fourth conducting elements
comprise a metal.
8. The semiconductor device according to claim 1, wherein at least
one of the first, second, third and fourth conducting elements are
a part of a coil.
9. A semiconductor device, comprising: a semiconductor chip
comprising at least two contact elements and a first conducting
element located in the chip, a layer of conducting elements
arranged adjacent the chip, comprising a contact region providing
an interface to the outside of the semiconductor device, and second
and third conducting elements, and a mold material covering a
backside and side faces of the semiconductor chip, wherein a part
of the layer of conducting elements projects vertically on the mold
material covering the side faces of the chip, wherein the second
conducting element and the third conducting element are connected
to the first conducting element located in the chip via contact
elements, so that the second and third conducting elements are
electrically connected via the first conducting element, and the
second conducting element is connected to the contact region.
10. The semiconductor device according to claim 9, wherein a
vertical projection of the first conducting element located in the
chip on the layer of conducting elements crosses a fourth
conducting element of the layer of conducting elements.
11. The semiconductor device according to claim 9, further
comprising a first dielectric layer arranged between the
semiconductor chip and the layer of conducting elements.
12. The semiconductor device according to claim 11, further
comprising a second dielectric layer arranged on a side of the
layer of conducting elements opposite the first dielectric
layer.
13. The semiconductor device according to claim 9, wherein the
contact region of the layer of conducting elements comprises a
solder ball.
14. The semiconductor device according to claim 9, wherein the
layer of conducting elements comprises a metal.
15. A method of manufacturing semiconductor devices, comprising:
providing at least two semiconductor chips that each comprise a
first conduction line; covering the at least two semiconductor
chips with mold material; applying a metallization layer over the
at least two semiconductor chips and the mold material such that
the metallization layer contacts each of the first conduction lines
at least two separated locations, wherein at least a part of the
metallization layer extends over the at least two semiconductor
chips and the mold material; and separating the at least two
semiconductor chips from each other after the application of the
metallization layer.
16. The method according to claim 15, wherein the semiconductor
chips are diced semiconductor chips.
17. The method according to claim 15, wherein a first dielectric
layer is applied on at least one of the semiconductor chips before
applying the metallization layer, and contact holes are
subsequently formed in the first dielectric layer.
18. The method according to claim 15, wherein a second dielectric
layer is applied after application of the metallization layer, and
wherein contact holes are subsequently formed in the second
dielectric layer.
19. The method according to claim 15, wherein the metallization
layer is etched using a mask so as to produce at least one
conduction line.
20. A method of manufacturing semiconductor devices, comprising:
providing a semiconductor chip having a first conducting element,
which is connected to two contact elements on a face of the chip;
and providing an encapsulating body, which encapsulates the
semiconductor chip, and providing a layer of conducting elements on
one side of the chip, wherein the layer of conducting elements at
least partially extends over the semiconductor chip and the
encapsulating body, wherein a second conducting element and a third
conducting element of the layer of conducting elements are
connected to the first conducting element located in the chip via
contact elements, so that the second and third conducting elements
are electrically connected via the first conducting element, and a
vertical projection of a fourth conducting element of the layer of
conducting elements crosses the first conducting element.
21. The method of claim 20, wherein the layer of conducting
elements is part of a substrate.
22. The method of claim 20, wherein the layer of conducting
elements is part of a printed circuit board.
Description
RELATED APPLICATION
[0001] This is a Continuation application of Ser. No. 11/965,081
filed Dec. 27, 2007, the disclosure of which is hereby incorporated
by reference in its entirety
[0002] This disclosure refers to embodiments of semiconductor
devices and methods for their production, particularly the
electrical connection between a semiconductor chip and its
supporting structure.
BACKGROUND
[0003] In the production of semiconductor devices, small contact
elements on the semiconductor chip have to be connected to
electrical terminals which provide a contact to the outside world.
These connections are generally realized as part of the package or
encapsulation of the semiconductor chip, e.g. by providing a
metallization layer on a face of the chip which provides conducting
elements or lines connecting the contact elements of the chip to
contact elements on an outer face of the package, e.g. solder
balls. Especially with high pin counts, the problem frequently
occurs that the high number of conducting lines in the layer cannot
be arranged without crossings between at least some of the lines.
In a single metallization layer, a crossing of two lines can not be
realized because this would cause an electrical shortcut between
the lines. Hence, in this case a second metallization layer has to
be provided in order to arrange the connections between the chip
and the contact elements to the outside.
SUMMARY
[0004] According to an embodiment, a semiconductor device is
provided. It includes a semiconductor chip which includes a first
conducting element. A second conducting element outside the
semiconductor chip is electrically connected to the first
conducting element arranged at a first location. A third conducting
element outside the semiconductor chip is electrically connected to
the first conducting element at a second location. A fourth
conducting element is also provided arranged outside the
semiconductor chip. In a vertical projection of the fourth
conducting element on the chip, the projection crosses the first
conducting element between the first location and the second
location.
[0005] According to a further embodiment, a semiconductor device is
provided. It includes a semiconductor chip including at least two
contact elements and a first conducting element located in the
chip, and a layer of conducting elements arranged adjacent the
chip, which include a contact region providing an interface to the
outside of the semiconductor device. It further includes second and
third conducting elements connected to the first conducting element
located in the chip via contact elements, so that the second and
third conducting elements are electrically connected via the first
conducting element, and wherein the second conducting element is
connected to the contact region. According to a further embodiment,
there is provided a method of manufacturing semiconductor devices,
which includes providing at least two semiconductor chips that each
comprise a first conduction line, covering the at least two
semiconductor chips with mold material, applying a metallization
layer over the at least two semiconductor chips and the mold
material such that the metallization layer contacts each of the
first conduction lines at least two separated locations, and
separating the at least two semiconductor chips from each other
after the application of the metallization layer.
[0006] According to a further embodiment, there is provided a
method of manufacturing semiconductor devices, which includes
providing a semiconductor chip having a first conducting element,
which is connected to two contact elements on a face of the chip,
and providing a layer of conducting elements on a face of the chip,
wherein a second conducting element and a third conducting element
of the layer of conducting elements are connected to the first
conducting element located in the chip via contact elements, so
that the second and third conducting elements are electrically
connected via the first conducting element, and a vertical
projection of a fourth conducting element of the layer of
conducting elements crosses the first conducting element.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0007] A full and enabling disclosure, including the best mode
thereof, to one of ordinary skill in the art, is set forth more
particularly in the remainder of the specification, including
reference to the accompanying figures. Therein:
[0008] FIGS. 1a-1b show a semiconductor device.
[0009] FIG. 2a shows a schematic cross-sectional view of the
semiconductor device.
[0010] FIG. 2b shows a schematic perspective view of the
semiconductor device.
[0011] FIG. 3a shows a cross-sectional view of a semiconductor
device according to an embodiment.
[0012] FIG. 3b shows a schematic view of a semiconductor device
according to an embodiment.
[0013] FIGS. 4a-4b show a further semiconductor device.
[0014] FIGS. 5a-5b show a detailed view of a semiconductor device
according to an embodiment.
[0015] FIGS. 6a-6b show a semiconductor wafer and a reconstituted
wafer according to an embodiment.
[0016] FIGS. 7a-7i show process steps according to an
embodiment.
[0017] FIG. 8 shows an embodiment of a semiconductor device
according to an embodiment.
[0018] FIG. 9 shows a further embodiment of a semiconductor device
according to an embodiment.
[0019] FIGS. 10a-10b show a further embodiment of a semiconductor
device according to an embodiment.
DETAILED DESCRIPTION
[0020] Reference will now be made in detail to various embodiments,
one or more examples of which are illustrated in the figures. Each
example is provided by way of explanation, and is not meant as a
limitation. For example, features illustrated or described as part
of one embodiment can be used on or in conjunction with other
embodiments to yield yet a further embodiment. It is intended that
the present disclosure includes such modifications and variations.
The examples are described using specific language which should not
be construed as limiting the scope of the appending claims. The
drawings are not scaled and are for illustrative purposes only.
[0021] The term "connected" is used in this context for a direct
connection of two elements, which includes that the elements are
electrically connected. The term "electrically connected" means
that two elements are in electrical contact, but can be connected
over an intermediate element, hence they need not be directly
connected. The terms "conducting element" and "conducting line" are
used interchangeably in this description.
[0022] A concept underlying the design of the embodiments below is
the functional separation between the layout of the semiconductor
chip and the layout of the package, printed circuit board or
substrate. This is achieved by using a conducting element in the
semiconductor chip to enable crossings of conducting lines in
redistribution layers, printed circuit boards or substrates without
the need of implementing further layers. In the following, this
concept is described for a number of embodiments.
[0023] FIGS. 1a and 1b show an example of a typical semiconductor
device 5 employing a fan-in wafer level ball grid array, also known
as wafer level package or WLP. The semiconductor chip 10 includes a
number of contact elements 20 on a face. A first dielectric layer
30, which typically includes silicone, is applied to the face of
the chip. A metallization layer including copper or aluminum is
provided on the first dielectric layer. The metallization layer is
structured by etching during the manufacturing process in order to
provide a number of conducting elements 50 (also referred to as
conducting lines in the following). In a typical manufacturing
process, the metal is sputtered on the first dielectric layer 30,
covered with a resist layer, and exposed to radiation employing an
exposure mask. After a development process, the produced structure
is plated and stripped. A typical thickness of the produced
structure of metallic conducting elements is in the range from 3 to
20 .mu.m, more preferred from 4 to 8 .mu.m. A typical width of the
resulting conducting lines is 20 .mu.m. Through contact holes 25 in
the first dielectric layer 30, the conducting lines are in contact
with the contact elements 20 or contact pads on the chip. A second
dielectric layer 60 on the metallization layer typically includes
polyimide. Via holes 65, the conducting lines 50 are in electrical
contact with solder balls 70, also referred to herein as external
connecting element, which are placed on holes of the second
dielectric layer 60. FIG. 1b shows a bottom view on the described
semiconductor device. In FIG. 2a, a more detailed sectional view of
the structure of FIG. 1a is shown. FIG. 2b shows a schematic view
of the semiconductor device, wherein only one conduction line 50
and solder ball 70 are shown out of the plurality of conducting
elements which form the layer of conducting elements.
[0024] FIG. 3a shows a further embodiment. Based on the
semiconductor device 5 as shown in FIGS. 1a, 1b, 2a and 2b, a
conducting line or conducting element 100, also referred to herein
as first conducting element, provided in the chip 10 serves as a
functional part of the layer of conducting elements, of which three
elements 110, 120, 130, also referred to herein as second, fourth,
and third conducting elements, respectively, are exemplarily
depicted in FIG. 3a. Conducting elements 110 and 130 are
electrically connected via the conducting element 100 in the chip.
Conducting element 110 is electrically connected to conducting
element 100 at a first location. Conducting element 130 is
electrically connected to conducting element 100 at a second
location 135. The electrical current flowing from element 110 to
element 130 or vice versa makes a detour around conducting element
120, which extends in a direction with an arbitrary angle to
elements 110 and 130. Hence, it becomes possible to provide a
crossing between the conducting path constituted by elements
110/130 and element 120 by maintaining a single layer of conducting
elements. An essential feature for enabling this is the conducting
element 100 in the chip, which forms a part of the electrical path
as described above. A vertical projection of the conducting element
120 onto the chip would cross the first conducting element 100
(located on the chip) between the first contact element 110 and the
second contact element 130. In a further embodiment, an insulating
layer 30, typically of silicone, is provided between the chip with
conducting element 100 and conducting elements 110, 120, 130.
Typically, elements 110, 120, 130 are formed from a common
conductive layer or metallization layer provided on the first
dielectric layer 30. FIG. 3b shows a schematic bottom view of the
device shown in FIG. 3a, wherein four crossings of conducting
elements are depicted, of which each crossing shows the
characteristics described above and depicted in FIG. 3a.
[0025] Conducting element 100 is typically a conducting structure
in one of the top layers of the semiconductor chip 10. It is
typically not part of the circuitry of the chip, but designed only
for the described purpose. It has two contact elements or contact
pads 20, typically at its ends, where it is connected to conducting
elements 110, 130.
[0026] During the design phase of the semiconductor device, the
routing of the conducting elements in the layer of conducting
elements is arranged. If it occurs that a crossing between two
conducting elements in the metallization layer is necessary, the
design according to the above described embodiments is employed.
That is, in the mask for the production of the layer of conducting
elements, one of the elements is separated at the location where
the crossing with another conducting element would be necessary.
Simultaneously, conducting element 100 is added to the layout of
the semiconductor chip, designated to connect the separated
conducting elements in the semiconductor device.
[0027] In a further embodiment, shown in FIGS. 5a and 5b, the above
described technique of using a conduction line 100 in the chip as a
functional element of the layer of conducting elements is applied
to a chip 10 which is additionally encapsulated in a body 150
including a mold mass 240. This kind of assembly is also known as
an embedded wafer level ball grid array (eWLB) and is shown in
FIGS. 4a and 4b. The mold mass is typically a polymer, e.g. a
polyimide or an epoxy resin, which includes a high amount of
SiO.sub.2 which may exceed 90 weight-percent. The mass covers a
face 160 of the chip opposite the conducting layer, as well as the
side faces 170. Typically, the conducting layer extends over the
semiconductor chip and the encapsulating body 150. One effect of
this structure is that the space available for the conducting layer
greatly exceeds, which is particularly useful for the packaging of
highly integrated semiconductor chips which require a high number
of external connections and thus a package with a high pin count.
For a given pitch of the printed circuit board to which the
semiconductor device shall be applied, only a limited number of
connections can be arranged under the footprint of the chip. Hence,
by adding the mold mass 240 and extending the layer of conducting
elements 50 and of solder balls 70 to the area of the encapsulating
body 150, this area is greatly increased in comparison to the
assembly without the encapsulating body, which is apparent from
FIGS. 4a and 4b.
[0028] In the following, the manufacturing method for the
aforementioned embedded wafer level ball grid array is described.
The procedure is based on the dicing of a readily fabricated and
tested wafer 200 into discrete semiconductor chips 10, the
relocation of the semiconductor chips in a larger spacing then they
have been in the wafer bond, and the addition of a molding compound
or mold mass to be a placeholder between the chips. FIG. 6a
schematically shows a semiconductor wafer 200 before undergoing
this process, and FIG. 6b the resulting reconstituted or
reconfigurated wafer 210. In order to produce the latter, the
following steps are carried out, which are depicted in FIGS. 7a to
7f:
[0029] 7a: dicing the fabricated and tested semiconductor wafer 200
shown in FIG. 6a in order to achieve single semiconductor chips
10.
[0030] 7b: Laminating a double sided adhesive tape 230 onto a metal
carrier plate 220 in order to support the assembly during molding,
wherein the tape 230 typically features thermo-release properties
which allow the removal of the tape after molding.
[0031] 7c: placing the diced chips 10 onto the mounted tape 230
with the active area facing down.
[0032] 7d: encapsulating the mounted chips 10 by molding by using a
molding compound 240.
[0033] 7e: releasing the molded, reconfigured wafer 210 from the
carrier plate 220.
[0034] 7f: pealing off the adhesive tape from the molded wafer
210.
[0035] Typically, a liquid mold compound is used as it can be
dispended and no melting time is needed. The reconfigured wafer 210
typically has a thickness similar to a normal wafer, i.e. about 300
.mu.m. Hence, further processing steps such as the application of
the metallization layer for the production of the layer of
conducting elements may be carried out using equipment designed for
wafer processing. Further processing steps in order to arrive at an
embodiment are described in the following with respect to FIGS. 7g
to 7i.
[0036] FIG. 7g shows how a first dielectric layer 30, which
typically includes silicone, is applied to the face of the
reconstituted wafer 210, wherein only a small segment of the wafer
210 is depicted. After contact holes 25 have been formed in the
first dielectric layer 30, a metallization layer including copper
or aluminium is provided on the first dielectric layer. FIG. 7h
shows the metallization layer which is structured by etching during
the manufacturing process in order to provide a number of
conducting elements 110, 120, 130 (also referred to as conducting
lines in the following). In a typical manufacturing process, the
metal is sputtered on the silicone layer 30, covered with a resist
layer, and exposed to radiation employing an exposure mask. After a
development process, the produced structure is plated and stripped.
A typical thickness of the produced structure of metallic
conducting elements is in the range from 3 to 20 .mu.m, more
preferred from 4 to 8 .mu.m. A typical width of the resulting
conducting lines is 20 .mu.m. Through contact holes 25 in the first
dielectric layer 30, the conducting lines are in contact with the
contact elements 20 or contact pads on the chips. A second
dielectric layer 60 provided on the metallization layer typically
includes polyimide. Via holes 65, the conducting lines 50 are in
electrical contact with solder balls 70 which are placed on holes
of the second dielectric layer 60.
[0037] In an embodiment shown in FIG. 8, the chip 10 is mounted on
a substrate 300 with solder balls 70 as a connection between chip
and substrate, respectively solderballs 310 between substrate and a
printed circuit board (not shown). The electrical path from
conduction element 350 to conduction element 360 is routed over
solder ball 370 to conduction element 320 located in the
semiconductor chip and to solder ball 380. By employing this
indirect routing, a crossing of the path from element 350 to
element 360 with the conduction element 330 is enabled, while the
substrate has only a single layer of conducting elements.
[0038] Additionally to the embodiments described herein in detail,
the concept of using a conducting element in the semiconductor chip
as a functional part of an external layer of conducting elements
may be applied to a variety of chip packaging technologies. These
include, as non-limiting examples, Flip Chip technology or Carrier
Wafer Level Ball grid arrays (CWLB). Thereby, a variety of contact
variants to the outside may be employed, such as (non-limiting) the
use of solder balls, pins or land grid arrays (LGA). A person
skilled in the art can easily transfer the concept applied in the
described embodiments to other technologies.
[0039] In an embodiment shown in FIG. 9, the chip 10 is mounted on
a printed circuit board 400 with solder balls 70 as a connection
between chip and board. The electrical path from conduction element
450 to conduction element 460 is routed over solder ball 470 to
conduction element 420 located in the semiconductor chip, and to
solder ball 480. By employing this indirect routing, a crossing of
the path from element 450 to element 460 with the conduction
element 430 is enabled at an arbitrary angle, while the printed
circuit board has only a single layer of conducting elements.
[0040] In an embodiment shown in FIGS. 10a and 10b, a coil 300 is
part of the semiconductor device. The coil is substantially formed
in the layer of conducting elements. In order to enable the coil to
be formed from a single layer of conducting elements, conducting
element 310 shown in FIG. 9 is provided as a part of the
semiconductor chip 10. Best, the coil is only partly overlying
semiconductor chip 10 and its main part overlies encapsulating body
150. Hence, undesirable interferences of the high frequency
electromagnetic field of the coil with the semiconductor chip can
be minimized.
* * * * *