U.S. patent application number 13/105866 was filed with the patent office on 2011-09-01 for chip package.
This patent application is currently assigned to Megica Corporation. Invention is credited to Jin-Yuan Lee, Hsin-Jing Lo.
Application Number | 20110210441 13/105866 |
Document ID | / |
Family ID | 39852974 |
Filed Date | 2011-09-01 |
United States Patent
Application |
20110210441 |
Kind Code |
A1 |
Lee; Jin-Yuan ; et
al. |
September 1, 2011 |
CHIP PACKAGE
Abstract
A chip package includes a semiconductor chip, a flexible circuit
film and a substrate. The substrate has a circuit structure in the
substrate. The flexible circuit film is connected to the circuit
structure of the substrate through metal joints, an anisotropic
conductive film or wireboning wires. The semiconductor chip has
fine-pitched metal bumps having a thickness of between 5 and 50
micrometers, and preferably of between 10 and 25 micrometers, and
the semiconductor chip is joined with the flexible circuit film by
the fine-pitched metal bumps using a chip-on-film (COF) technology
or tape-automated-bonding (TAB) technology. A pitch of the
neighboring metal bumps is less than 35 micrometers, such as
between 10 and 30 micrometers.
Inventors: |
Lee; Jin-Yuan; (Hsin-Chu,
TW) ; Lo; Hsin-Jing; (Taipei, TW) |
Assignee: |
Megica Corporation
Hsinchu
TW
|
Family ID: |
39852974 |
Appl. No.: |
13/105866 |
Filed: |
May 11, 2011 |
Related U.S. Patent Documents
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Application
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Filing Date |
Patent Number |
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12101127 |
Apr 10, 2008 |
7964961 |
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13105866 |
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60911512 |
Apr 12, 2007 |
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60914771 |
Apr 30, 2007 |
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Current U.S.
Class: |
257/737 ;
257/E23.068 |
Current CPC
Class: |
H01L 2224/05666
20130101; H01L 2924/01024 20130101; H01L 24/81 20130101; H01L
2224/0231 20130101; H01L 2224/73204 20130101; H01L 2224/81205
20130101; H01L 2924/01006 20130101; H01L 2924/01322 20130101; H01L
2924/04941 20130101; H01L 2924/1305 20130101; H01L 2224/05647
20130101; H01L 2224/48091 20130101; H01L 2924/01011 20130101; H01L
2224/81801 20130101; H01L 2924/0002 20130101; H01L 24/50 20130101;
H01L 2924/01015 20130101; H01L 2224/11912 20130101; H01L 2924/01022
20130101; H01L 2924/19043 20130101; H01L 2224/13155 20130101; H01L
2224/02377 20130101; H01L 2224/32225 20130101; H01L 2224/05147
20130101; H01L 2924/19042 20130101; H01L 2224/13144 20130101; H01L
2924/00013 20130101; H01L 2924/19041 20130101; H01L 2924/19105
20130101; H01L 24/03 20130101; H01L 2224/05671 20130101; H01L
2224/13147 20130101; H01L 2924/14 20130101; H01L 2924/15787
20130101; H01L 2224/05181 20130101; H01L 2224/0558 20130101; H01L
2924/01018 20130101; H01L 2224/05655 20130101; H01L 2224/131
20130101; H01L 2224/13111 20130101; H01L 2924/01029 20130101; H01L
2924/014 20130101; H01L 2924/04953 20130101; H01L 2224/16225
20130101; H01L 24/16 20130101; H01L 2224/45144 20130101; H01L
2924/19107 20130101; H01L 21/563 20130101; H01L 24/86 20130101;
H01L 2224/05124 20130101; H01L 2224/05171 20130101; H01L 2224/13164
20130101; H01L 2924/0105 20130101; H01L 2924/01074 20130101; H01L
2924/01082 20130101; H01L 2224/0401 20130101; H01L 2224/48644
20130101; H01L 2924/01013 20130101; H01L 23/49531 20130101; H01L
24/11 20130101; H01L 24/12 20130101; H01L 2224/05624 20130101; H01L
2924/01033 20130101; H01L 2924/01079 20130101; H01L 2224/05184
20130101; H01L 2224/13139 20130101; H01L 2924/01073 20130101; H01L
2924/01078 20130101; H01L 2924/10329 20130101; H01L 24/05 20130101;
H01L 2224/05681 20130101; H01L 2224/1147 20130101; H01L 2924/15311
20130101; H01L 2224/05166 20130101; H01L 2224/05644 20130101; H01L
2224/81203 20130101; H01L 23/3128 20130101; H01L 2924/01019
20130101; H01L 2924/12044 20130101; H01L 2924/181 20130101; H01L
25/0655 20130101; H01L 2924/01047 20130101; H01L 2224/05572
20130101; H01L 2924/01046 20130101; H01L 2224/131 20130101; H01L
2924/00014 20130101; H01L 2224/13144 20130101; H01L 2924/00014
20130101; H01L 2224/13147 20130101; H01L 2924/00014 20130101; H01L
2224/13139 20130101; H01L 2924/00014 20130101; H01L 2224/13111
20130101; H01L 2924/00014 20130101; H01L 2224/13155 20130101; H01L
2924/00014 20130101; H01L 2224/13164 20130101; H01L 2924/00014
20130101; H01L 2224/0558 20130101; H01L 2224/05644 20130101; H01L
2924/00013 20130101; H01L 2224/13099 20130101; H01L 2224/73204
20130101; H01L 2224/16225 20130101; H01L 2224/32225 20130101; H01L
2924/00 20130101; H01L 2224/16225 20130101; H01L 2224/13144
20130101; H01L 2924/00 20130101; H01L 2224/16225 20130101; H01L
2224/13147 20130101; H01L 2924/00 20130101; H01L 2224/16225
20130101; H01L 2224/13139 20130101; H01L 2924/00 20130101; H01L
2224/16225 20130101; H01L 2224/13111 20130101; H01L 2924/00
20130101; H01L 2224/16225 20130101; H01L 2224/13155 20130101; H01L
2924/00 20130101; H01L 2224/16225 20130101; H01L 2224/13164
20130101; H01L 2924/00 20130101; H01L 2924/15311 20130101; H01L
2224/73204 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2924/00 20130101; H01L 2224/48091 20130101; H01L
2924/00014 20130101; H01L 2224/45144 20130101; H01L 2924/00
20130101; H01L 2924/1305 20130101; H01L 2924/00 20130101; H01L
2924/0002 20130101; H01L 2224/05552 20130101; H01L 2924/15787
20130101; H01L 2924/00 20130101; H01L 2224/48644 20130101; H01L
2924/00 20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101;
H01L 2224/05624 20130101; H01L 2924/00014 20130101; H01L 2224/05644
20130101; H01L 2924/00014 20130101; H01L 2224/05647 20130101; H01L
2924/00014 20130101; H01L 2224/05655 20130101; H01L 2924/00014
20130101; H01L 2224/05666 20130101; H01L 2924/00014 20130101; H01L
2224/05671 20130101; H01L 2924/00014 20130101; H01L 2224/05681
20130101; H01L 2924/00014 20130101; H01L 2224/05124 20130101; H01L
2924/00014 20130101; H01L 2224/05147 20130101; H01L 2924/00014
20130101; H01L 2224/05166 20130101; H01L 2924/00014 20130101; H01L
2224/05171 20130101; H01L 2924/00014 20130101; H01L 2224/05181
20130101; H01L 2924/00014 20130101; H01L 2224/05184 20130101; H01L
2924/00014 20130101; H01L 2224/05124 20130101; H01L 2924/01029
20130101; H01L 2924/013 20130101; H01L 2224/05124 20130101; H01L
2924/01014 20130101; H01L 2924/01029 20130101; H01L 2924/013
20130101; H01L 2224/05166 20130101; H01L 2924/01074 20130101; H01L
2924/013 20130101; H01L 2224/05624 20130101; H01L 2924/01029
20130101; H01L 2924/013 20130101; H01L 2224/05624 20130101; H01L
2924/01014 20130101; H01L 2924/01029 20130101; H01L 2924/013
20130101; H01L 2924/013 20130101; H01L 2224/05666 20130101; H01L
2924/01074 20130101; H01L 2924/013 20130101; H01L 2224/05671
20130101; H01L 2924/013 20130101; H01L 2224/05681 20130101; H01L
2924/013 20130101; H01L 2224/05644 20130101; H01L 2924/013
20130101; H01L 2224/05647 20130101; H01L 2924/013 20130101; H01L
2224/05655 20130101; H01L 2924/013 20130101 |
Class at
Publication: |
257/737 ;
257/E23.068 |
International
Class: |
H01L 23/498 20060101
H01L023/498 |
Claims
1-20. (canceled)
21. A circuit component comprising: a chip comprising a silicon
substrate, a first metal layer over said silicon substrate, a
dielectric layer over said first metal layer, a second metal layer
over said dielectric layer, said first metal layer and said silicon
substrate, an insulating layer on said second metal layer and over
said dielectric layer, wherein said second metal layer has multiple
contact points not covered by said insulating layer, multiple metal
bumps on said multiple contact points, wherein said multiple metal
bumps are provided by a copper layer having a thickness between 5
and 50 micrometers; and a first circuit substrate connected to said
chip through said metal bumps, wherein said first circuit substrate
comprises first, second and third metal traces extending across an
edge of said chip, wherein said first, second and third metal
traces are provided by a bottommost fan-out metal layer of said
first circuit substrate, a first vertical interconnect on said
first metal trace and not vertically over said chip, a second
vertical interconnect on said second metal trace and not vertically
over said chip, and a third vertical interconnect on said third
metal trace and not vertically over said chip, wherein said first,
second and third vertical interconnects are aligned in a line
substantially parallel with said edge and connected to said first,
second and third metal traces, respectively, wherein said first,
second and third vertical interconnects are sequentially arranged
in a same order as the arrangement of said first, second and third
metal traces, wherein between said line and said edge from a top
perspective view, said first circuit substrate has no metal trace
between said first and second metal traces and between said second
and third metal traces, wherein from said top perspective view,
said first circuit substrate has no vertical interconnect on any
metal trace, between said line and said edge, of said bottommost
fan-out metal layer of said first circuit substrate, wherein a
first pitch between said first and second metal traces at said edge
is less than a second pitch between said first and second vertical
interconnects, and wherein a third pitch between said second and
third metal traces at said edge is less than a fourth pitch between
said second and third vertical interconnects.
22. The circuit component of claim 21, wherein said first circuit
substrate comprises a flexible substrate.
23. The circuit component of claim 21, wherein a fifth pitch
between a first one of said multiple metal bumps and a second one
of said multiple metal bumps is less than 35 micrometers.
24. The circuit component of claim 21, wherein said first circuit
substrate has no vertical interconnect beyond said line away from
said edge.
25. The circuit component of claim 21, wherein said thickness of
said copper layer is between 10 and 25 micrometers.
26. The circuit component of claim 21 further comprising a
tin-containing layer between said copper layer and said bottommost
fan-out metal layer of said first circuit substrate.
27. The circuit component of claim 21, wherein said circuit
substrate further comprises a fourth metal trace extending across
said edge, wherein said fourth metal trace is provided by said
bottommost fan-out metal layer of said circuit substrate, and a
fourth vertical interconnect on said fourth metal trace and not
vertically over said chip, wherein said fourth vertical
interconnect is aligned with said first, second and third vertical
interconnects in said line and connected to said fourth metal
trace, wherein said first, second, third and fourth vertical
interconnects are sequentially arranged in a same order as the
arrangement of said first, second, third and fourth metal traces,
wherein between said line and said edge from said top perspective
view, said circuit substrate has no metal trace between said third
and fourth metal traces, wherein a fifth pitch between said third
and fourth metal traces at said edge is less than a sixth pitch
between said third and fourth vertical interconnects.
28. The circuit component of claim 27, wherein said circuit
substrate further comprises a fifth metal trace extending across
said edge, wherein said fifth metal trace is provided by said
bottommost fan-out metal layer of said circuit substrate, and a
fifth vertical interconnect on said fifth metal trace and not
vertically over said chip, wherein said fifth vertical interconnect
is aligned with said first, second, third and fourth vertical
interconnects in said line and connected to said fifth metal trace,
wherein said first, second, third, fourth and fifth vertical
interconnects are sequentially arranged in a same order as the
arrangement of said first, second, third, fourth and fifth metal
traces, wherein between said line and said edge from said top
perspective view, said circuit substrate has no metal trace between
said fourth and fifth metal traces, wherein a seventh pitch between
said fourth and fifth metal traces at said edge is less than an
eighth pitch between said fourth and fifth vertical
interconnects.
29. The circuit component of claim 21 further comprising a second
circuit substrate and an anisotropic conductive film (ACF) between
said first and second circuit substrates, wherein said first
circuit substrate is connected to said second circuit substrate
through said anisotropic conductive film.
30. A circuit component comprising: a chip comprising a silicon
substrate, a first metal layer over said silicon substrate, a
dielectric layer over said first metal layer, a second metal layer
over said dielectric layer, said first metal layer and said silicon
substrate, an insulating layer on said second metal layer and over
said dielectric layer, wherein said second metal layer has multiple
contact points not covered by said insulating layer, multiple metal
bumps on said multiple contact points, wherein said multiple metal
bumps are provided by a copper layer having a thickness between 0.5
and 45 micrometers; and a first circuit substrate connected to said
chip through said metal bumps, wherein said first circuit substrate
comprises first, second and third metal traces extending across an
edge of said chip, wherein said first, second and third metal
traces are provided by a bottommost fan-out metal layer of said
first circuit substrate, a first vertical interconnect on said
first metal trace and not vertically over said chip, a second
vertical interconnect on said second metal trace and not vertically
over said chip, and a third vertical interconnect on said third
metal trace and not vertically over said chip, wherein said first,
second and third vertical interconnects are aligned in a line
substantially parallel with said edge and connected to said first,
second and third metal traces, respectively, wherein said first,
second and third vertical interconnects are sequentially arranged
in a same order as the arrangement of said first, second and third
metal traces, wherein between said line and said edge from a top
perspective view, said first circuit substrate has no metal trace
between said first and second metal traces and between said second
and third metal traces, wherein from said top perspective view,
said first circuit substrate has no vertical interconnect on any
metal trace, between said line and said edge, of said bottommost
fan-out metal layer of said first circuit substrate, wherein a
first pitch between said first and second metal traces at said edge
is less than a second pitch between said first and second vertical
interconnects, and wherein a third pitch between said second and
third metal traces at said edge is less than a fourth pitch between
said second and third vertical interconnects.
31. The circuit component of claim 30, wherein said first circuit
substrate comprises a flexible substrate.
32. The circuit component of claim 30, wherein a fifth pitch
between a first one of said multiple metal bumps and a second one
of said multiple metal bumps is less than 35 micrometers.
33. The circuit component of claim 30, wherein said first circuit
substrate has no vertical interconnect beyond said line away from
said edge.
34. The circuit component of claim 30, wherein said thickness of
said copper layer is between 5 and 35 micrometers.
35. The circuit component of claim 30 further comprising a
tin-containing layer between said copper layer and said bottommost
fan-out metal layer of said first circuit substrate.
36. The circuit component of claim 30, wherein said circuit
substrate further comprises a fourth metal trace extending across
said edge, wherein said fourth metal trace is provided by said
bottommost fan-out metal layer of said circuit substrate, and a
fourth vertical interconnect on said fourth metal trace and not
vertically over said chip, wherein said fourth vertical
interconnect is aligned with said first, second and third vertical
interconnects in said line and connected to said fourth metal
trace, wherein said first, second, third and fourth vertical
interconnects are sequentially arranged in a same order as the
arrangement of said first, second, third and fourth metal traces,
wherein between said line and said edge from said top perspective
view, said circuit substrate has no metal trace between said third
and fourth metal traces, wherein a fifth pitch between said third
and fourth metal traces at said edge is less than a sixth pitch
between said third and fourth vertical interconnects.
37. The circuit component of claim 36, wherein said circuit
substrate further comprises a fifth metal trace extending across
said edge, wherein said fifth metal trace is provided by said
bottommost fan-out metal layer of said circuit substrate, and a
fifth vertical interconnect on said fifth metal trace and not
vertically over said chip, wherein said fifth vertical interconnect
is aligned with said first, second, third and fourth vertical
interconnects in said line and connected to said fifth metal trace,
wherein said first, second, third, fourth and fifth vertical
interconnects are sequentially arranged in a same order as the
arrangement of said first, second, third, fourth and fifth metal
traces, wherein between said line and said edge from said top
perspective view, said circuit substrate has no metal trace between
said fourth and fifth metal traces, wherein a seventh pitch between
said fourth and fifth metal traces at said edge is less than an
eighth pitch between said fourth and fifth vertical
interconnects.
38. The circuit component of claim 30 further comprising a second
circuit substrate and an anisotropic conductive film (ACF) between
said first and second circuit substrates, wherein said first
circuit substrate is connected to said second circuit substrate
through said anisotropic conductive film.
39. The circuit component of claim 30 further comprising a
tin-containing layer between said copper layer and said bottommost
fan-out metal layer of said first circuit substrate, wherein said
multiple metal bumps are further provided by a nickel layer between
said copper layer and said tin-containing layer.
40. The circuit component of claim 30 further comprising a
tin-containing layer between said copper layer and said bottommost
fan-out metal layer of said first circuit substrate, wherein said
multiple metal bumps are further provided by a gold layer between
said copper layer and said tin-containing layer.
41. A circuit component comprising: a chip comprising a silicon
substrate, a first metal layer over said silicon substrate, a
dielectric layer over said first metal layer, a second metal layer
over said dielectric layer, said first metal layer and said silicon
substrate, an insulating layer on said second metal layer and over
said dielectric layer, wherein said second metal layer has multiple
contact points not covered by said insulating layer, multiple metal
bumps on said multiple contact points, wherein said multiple metal
bumps are provided by a copper layer having a thickness between 5
and 50 micrometers, wherein a pitch between a first one of said
multiple metal bumps and a second one of said multiple metal bumps
is less than 35 micrometers; a flexible substrate connected to said
chip through said multiple metal bumps; a circuit substrate; and an
anisotropic conductive film (ACF) between said flexible substrate
and said circuit substrate, wherein said flexible substrate is
connected to said circuit substrate through said anisotropic
conductive film.
42. The circuit component of claim 41, wherein said thickness of
said copper layer is between 10 and 25 micrometers.
43. The circuit component of claim 41 further comprising a
tin-containing layer between said copper layer and said flexible
substrate.
44. A circuit component comprising: a chip comprising a silicon
substrate, a first metal layer over said silicon substrate, a
dielectric layer over said first metal layer, a second metal layer
over said dielectric layer, said first metal layer and said silicon
substrate, an insulating layer on said second metal layer and over
said dielectric layer, wherein said second metal layer has multiple
contact points not covered by said insulating layer, multiple metal
bumps on said multiple contact points, wherein said multiple metal
bumps are provided by a copper layer having a thickness between 0.5
and 45 micrometers, wherein a pitch between a first one of said
multiple metal bumps and a second one of said multiple metal bumps
is less than 35 micrometers; a flexible substrate connected to said
chip through said multiple metal bumps; a circuit substrate; and an
anisotropic conductive film (ACF) between said flexible substrate
and said circuit substrate, wherein said flexible substrate is
connected to said circuit substrate through said anisotropic
conductive film.
45. The circuit component of claim 44, wherein said thickness of
said copper layer is between 10 and 25 micrometers.
46. The circuit component of claim 44 further comprising a
tin-containing layer between said copper layer and said flexible
substrate.
47. The circuit component of claim 44 further comprising a
tin-containing layer between said copper layer and said flexible
substrate, wherein said multiple metal bumps are further provided
by a nickel layer between said copper layer and said tin-containing
layer.
48. The circuit component of claim 44 further comprising a
tin-containing layer between said copper layer and said flexible
substrate, wherein said multiple metal bumps are further provided
by a gold layer between said copper layer and said tin-containing
layer.
49. A chip comprising: a silicon substrate; a first metal layer
over said silicon substrate; a dielectric layer over said first
metal layer; a second metal layer over said dielectric layer, said
first metal layer and said silicon substrate; an insulating layer
on said second metal layer and over said dielectric layer, wherein
said second metal layer comprises a first portion having a first
left region, a first right region and a first contact point between
said first left and right regions, wherein said first left and
right regions and said first contact point are not covered by said
insulating layer, wherein said second metal layer comprises a
second portion having a second left region, a second right region
and a second contact point between said second left and right
regions, wherein said second left and right regions and said second
contact point are not covered by said insulating layer; a first
metal bump on said first contact point, wherein said first metal
bump has a first left sidewall horizontally spaced apart from a
left portion of said insulating layer, and said first left region
is between said first left sidewall and said left portion, wherein
said first metal bump has a first right sidewall horizontally
spaced apart from a middle portion of said insulating layer, and
said first right region is between said first right sidewall and
said middle portion, wherein said insulating layer has no portion
between said first left sidewall and said left portion and between
said first right sidewall and said middle portion; and a second
metal bump on said second contact point, wherein said second metal
bump has a second left sidewall horizontally spaced apart from said
middle portion, and said second left region is between said second
left sidewall and said middle portion, wherein said second metal
bump has a second right sidewall horizontally spaced apart from a
right portion of said insulating layer, and said second right
region is between said second right sidewall and said right
portion, wherein said insulating layer has no portion between said
second left sidewall and said middle portion and between said
second right sidewall and said right portion, wherein said first
and second metal bumps are provided by a copper layer having a
thickness between 5 and 50 micrometers, wherein a pitch between
said first and second metal bumps is less than 35 micrometers.
50. The chip of claim 49, wherein said thickness of said copper
layer is between 10 and 25 micrometers.
51. The chip of claim 49, wherein said insulating layer comprises a
polymer.
52. The chip of claim 49, wherein a first opening in said
dielectric layer is over a third contact point of said first metal
layer, and said third contact point is at a bottom of said first
opening, wherein a second opening in said dielectric layer is over
a fourth contact point of said first metal layer, and said fourth
contact point is at a bottom of said second opening, wherein said
third contact point is connected to said fourth contact point
through said second metal layer, and said first metal bump is
connected to said second metal bump through said second metal
layer.
53. The chip of claim 49, wherein said dielectric layer comprises
an oxide layer with a thickness between 0.2 and 1.2
micrometers.
54. The chip of claim 49, wherein said dielectric layer comprises a
nitride layer with a thickness between 0.2 and 1.2 micrometers.
55. The chip of claim 49, wherein said second metal layer comprises
copper.
56. The chip of claim 49, wherein said second metal layer comprises
electroplated copper.
Description
[0001] This application claims priority to U.S. provisional
application No. 60/911,512, filed on Apr. 13, 2007, and to U.S.
provisional application No. 60/914,771, filed on Apr. 30, 2007,
which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to a chip package, and, more
specifically, to a chip package having fine-pitched metal bumps
connected to an external circuit through a flexible circuit
film.
[0004] 2. Brief Description of the Related Art
[0005] In the recent years, the development of advanced technology
is on the cutting edge. As a result, high-technology electronics
manufacturing industries launch more feature-packed and humanized
electronic products. These new products that hit the showroom are
lighter, thinner, and smaller in design. In the manufacturing of
these electronic products, the key component has to be the
integrated circuit (IC) chip inside any electronic product.
SUMMARY OF THE INVENTION
[0006] It is the objective of the invention to provide a chip
package with a semiconductor chip having fine-pitched metal bumps
connected to an external circuit through a flexible circuit
film.
[0007] In order to reach the above objective, the present invention
provides a chip package including a substrate, a flexible circuit
film, a first tin-containing joint, a second tin-containing joint,
a semiconductor chip, a first metal bump and a second metal bump.
The substrate includes multiple insulating layers and multiple
metal circuit layers between the insulating layers. The flexible
circuit film is over a top surface of the substrate, and the
flexible circuit film includes a first polymer layer over the top
surface, a first metal trace on the first polymer layer, a second
metal trace on the first polymer layer and a second polymer layer
on the first and second metal traces. The first tin-containing
joint is between the first metal trace and a first pad of the top
surface, and the first metal trace is connected to the first pad
through the first tin-containing joint. The second tin-containing
joint is between the second metal trace and a second pad of the top
surface, and the second metal trace is connected to the second pad
through the second tin-containing joint. The semiconductor chip is
over the flexible circuit film and directly over the top surface.
The first metal bump is between the semiconductor chip and the
first metal trace, and the second metal bump is between the
semiconductor chip and the second metal trace, wherein a pitch
between the first and second metal bumps is less than 35
micrometers, such as between 5 and 25 micrometers.
[0008] In order to reach the above objective, the present invention
provides a chip package including a substrate, a flexible circuit
film, an anisotropic conductive film (ACF), a semiconductor chip, a
first metal bump and a second metal bump. The substrate includes a
circuit structure in the substrate. The flexible circuit film is
over a top surface of the substrate, and the flexible circuit film
comprises a first polymer layer over the top surface, a first metal
trace on the first polymer layer, a second metal trace on the first
polymer layer and a second polymer layer on the first and second
metal traces. The anisotropic conductive film is between the first
metal trace and a first pad of the top surface, and between the
second metal trace and a second pad of the top surface, wherein the
first metal trace is connected to the first pad through multiple
metal particles in the anisotropic conductive film, and the second
metal trace is connected to the second pad through multiple metal
particles in the anisotropic conductive film. The semiconductor
chip is over the flexible circuit film and directly over the top
surface. The first metal bump is between the semiconductor chip and
the first metal trace, and the second metal bump is between the
semiconductor chip and the second metal trace, wherein a pitch is
between the first and second metal bumps is less than 35
micrometers, such as between 5 and 25 micrometers.
[0009] In order to reach the above objective, the present invention
provides a chip package including a substrate, a flexible circuit
film, a first wireboning wire, a second wireboning wire, a
semiconductor chip, a first metal bump and a second metal bump. The
substrate includes a circuit structure in the substrate. The
flexible circuit film is over a top surface of the substrate, and
the flexible circuit film includes a first polymer layer over the
top surface, a first metal trace on the first polymer layer, a
second metal trace on the first polymer layer and a second polymer
layer on the first and second metal traces. The first wireboning
wire is connected to a first pad of the top surface and to the
first metal trace, and the second wireboning wire is connected to a
second pad of the top surface and to the second metal trace. The
semiconductor chip is over the flexible circuit film and directly
over the top surface. The first metal bump is between the
semiconductor chip and the first metal trace, and the second metal
bump is between the semiconductor chip and the second metal trace,
wherein a pitch between the first and second metal bumps is less
than 35 micrometers, such as between 5 and 25 micrometers.
[0010] To enable the objectives, technical contents,
characteristics and accomplishments of the present invention, the
embodiments of the present invention are to be described in detail
in cooperation with the attached drawings below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1 and 2 are cross-sectional views schematically
showing semiconductor chips according to the present invention.
[0012] FIGS. 1a-1e are cross-sectional views showing a process for
forming a semiconductor chip with metal bumps according to the
present invention.
[0013] FIGS. 3A-3K are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology and joining the flexible circuit film
with a rigid substrate according to one embodiment of the present
invention.
[0014] FIGS. 3L and 3M are perspective views showing two chip
packages each including a rigid substrate, a flexible circuit film
mounted on the rigid substrate and a semiconductor chip joined with
the flexible circuit film.
[0015] FIGS. 3N-3Q are cross-sectional views showing various chip
packages each including a rigid substrate, a flexible circuit film
mounted on the rigid substrate and a semiconductor chip joined with
the flexible circuit film.
[0016] FIGS. 3R-3X are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
tape-automated-bonding (TAB) technology and joining the flexible
circuit film with a rigid substrate according to another embodiment
of the present invention.
[0017] FIG. 3Y is a cross-sectional view showing a chip package
including a rigid substrate, a flexible circuit film mounted on the
rigid substrate and a semiconductor chip joined with the flexible
circuit film.
[0018] FIGS. 4A-4C are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology and bonding solder balls with the
flexible circuit film according to another embodiment of the
present invention.
[0019] FIG. 4D is a perspective view showing a chip package
including a flexible circuit film bonded with solder balls and a
semiconductor chip joined with the flexible circuit film.
[0020] FIGS. 5A-5E are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology and bonding solder balls with the
flexible circuit film according to another embodiment of the
present invention.
[0021] FIGS. 6A-6G are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology and joining the flexible circuit film
with a rigid substrate according to another embodiment of the
present invention.
[0022] FIGS. 6H and 6I are perspective views showing two chip
packages each including a rigid substrate, a flexible circuit film
mounted on the rigid substrate and a semiconductor chip joined with
the flexible circuit film.
[0023] FIGS. 6J-6M are cross-sectional views showing various chip
packages each including a rigid substrate, a flexible circuit film
mounted on the rigid substrate and a semiconductor chip joined with
the flexible circuit film.
[0024] FIGS. 6N-6S are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
tape-automated-bonding (TAB) technology and joining the flexible
circuit film with a rigid substrate according to another embodiment
of the present invention.
[0025] FIG. 6T is a cross-sectional view showing a chip package
including a rigid substrate, a flexible circuit film mounted on the
rigid substrate and a semiconductor chip joined with the flexible
circuit film.
[0026] FIGS. 7A-7F are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology and connecting the flexible circuit
film to a rigid substrate using a wirebinding process according to
another embodiment of the present invention.
[0027] FIG. 7G is perspective view showing a chip package including
a rigid substrate, a flexible circuit film mounted on the rigid
substrate and a semiconductor chip joined with the flexible circuit
film.
[0028] FIGS. 7H-7M are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
tape-automated-bonding (TAB) technology and connecting the flexible
circuit film to a rigid substrate using a wirebinding process
according to another embodiment of the present invention.
[0029] FIGS. 8A-8K are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology, bonding an electronic device with
the flexible circuit film using a chip-on-film (COF) technology and
joining the flexible circuit film with a rigid substrate according
to another embodiment of the present invention.
[0030] FIGS. 8I and 8J are perspective views showing two chip
packages each including a rigid substrate, a flexible circuit film
mounted on the rigid substrate, a semiconductor chip joined with
the flexible circuit film and an electronic device joined with the
flexible circuit film.
[0031] FIGS. 8K-8T are cross-sectional views showing various chip
packages each including a rigid substrate, a flexible circuit film
mounted on the rigid substrate, a semiconductor chip joined with
the flexible circuit film and an electronic device joined with the
flexible circuit film.
[0032] FIGS. 9A-9F are cross-sectional views showing a process for
bonding a semiconductor chip with a flexible circuit film using a
chip-on-film (COF) technology and joining the flexible circuit film
with a lead frame according to another embodiment of the present
invention.
[0033] FIGS. 9G and 9J are perspective views showing two chip
packages each including a lead frame, a flexible circuit film
mounted on the lead frame and a semiconductor chip joined with the
flexible circuit film.
[0034] FIGS. 9H-9I and 9K-9M are cross-sectional views showing
various chip packages each including a lead frame, a flexible
circuit film mounted on the lead frame and a semiconductor chip
joined with the flexible circuit film.
[0035] FIGS. 10A-10B are cross-sectional views showing a process
for bonding a semiconductor chip with a flexible circuit film using
a chip-on-film (COF) technology and joining the flexible circuit
film with a lead frame according to another embodiment of the
present invention.
[0036] FIG. 10C is a perspective view showing a chip package
including a lead frame, a flexible circuit film mounted on the lead
frame and a semiconductor chip joined with the flexible circuit
film.
[0037] FIGS. 10D-10H are cross-sectional views showing various chip
packages each including a lead frame, a flexible circuit film
mounted on the lead frame and a semiconductor chip joined with the
flexible circuit film.
DETAILED DESCRIPTION OF THE INVENTION
[0038] Referring to FIG. 1, a semiconductor chip 2 includes a
semiconductor substrate 4, multiple semiconductor devices 6, a
metallization structure, multiple dielectric layers 8, a
passivation layer 10 and multiple metal bumps 12. The semiconductor
substrate 4 may be a silicon substrate, a GaAs substrate or a SiGe
substrate.
[0039] The semiconductor devices 6 are formed in or over the
semiconductor substrate 4. The semiconductor devices 6 may comprise
a memory cell, a logic circuit, a passive device, such as resistor,
capacitor, inductor or filter, or an active device, such as
p-channel MOS device, n-channel MOS device, CMOS (Complementary
Metal Oxide Semiconductor) device, BJT (Bipolar Junction
Transistor) device or BiCMOS (Bipolar CMOS) device.
[0040] The metallization structure is formed over the semiconductor
substrate 4, connected to the semiconductor devices 6. The
metallization structure comprises multiple patterned metal layers
14 having a thickness t1 of less than 3 micrometers (such as
between 0.2 and 2 .mu.m) and multiple metal plugs 16. For example,
the patterned metal layers 14 and the metal plugs 16 are
principally made of copper, wherein each of the patterned metal
layers 14 has a copper-containing layer having a thickness of less
than 3 micrometers (such as between 0.2 and 2 .mu.m).
Alternatively, the patterned metal layers 14 are principally made
of aluminum or aluminum-alloy, and the metal plugs 16 are
principally made of tungsten, wherein each of the patterned metal
layers 14 has an aluminum-containing layer having a thickness of
less than 3 micrometers (such as between 0.2 and 2 .mu.m). The
patterned metal layers 14 may include multiple metal lines each
having a copper layer and an adhesion/barrier layer on the bottom
surface and sidewalls of the copper layer, wherein the
adhesion/barrier layer may be a tantalum-containing layer, such as
tantalum layer or tantalum nitride layer. The patterned metal
layers 14 can be formed by a damascene process including sputtering
an adhesion/barrier layer on the bottom of an opening in one of the
dielectric layer 8, on the sidewall of the opening and on one of
the dielectric layer 8, sputtering a copper seed layer on the
adhesion/barrier layer, electroplating a copper bulk layer on the
copper seed layer, then removing the copper bulk layer, the copper
seed layer and the adhesion/barrier layer outside the opening using
a chemical mechanical polishing (CMP) process.
[0041] The dielectric layers 8 are located over the semiconductor
substrate 4 and interposed respectively between the neighboring
patterned metal layers 14, and the neighboring patterned metal
layers 14 are interconnected through the metal plugs 16 inside the
dielectric layer 8. The dielectric layers 8 are commonly formed by
a chemical vapor deposition (CVD) process. The material of the
dielectric layers 8 may include silicon oxide, silicon oxynitride,
TEOS (Tetraethoxysilane), a compound containing silicon, carbon,
oxygen and hydrogen (such as Si.sub.wC.sub.xO.sub.yH.sub.z),
silicon nitride (such as Si.sub.3N.sub.4), FSG (Fluorinated
Silicate Glass), Black Diamond, SiLK, a porous silicon oxide, a
porous compound containing nitrogen, silicon carbon nitride (such
as SiCN), oxygen and silicon, SOG (Spin-On Glass), BPSG
(borophosphosilicate glass), a polyarylene ether, polybenzoxazole
(PBO), or a material having a low dielectric constant (K) of
between 1.5 and 3, for example. The dielectric layer 8 between the
neighboring patterned metal layers 14 has a thickness t2 of less
than 3 micrometers, such as between 0.3 and 3 .mu.m or between 0.3
and 2.5 .mu.m.
[0042] The passivation layer 10 is formed over the semiconductor
devices 6, over the metallization structure (including the metal
layers 14 and the metal plugs 16) and over the dielectric layers 8.
The passivation layer 10 can protect the semiconductor devices 6
and the metallization structure from being damaged by moisture and
foreign ion contamination. In other words, mobile ions (such as
sodium ion), transition metals (such as gold, silver and copper)
and impurities can be prevented from penetrating through the
passivation layer 10 to the semiconductor devices 6, such as
transistors, polysilicon resistor elements and
polysilicon-polysilicon capacitor elements, and to the
metallization structure.
[0043] The passivation layer 10 is commonly made of silicon oxide
(such as SiO.sub.2), PSG (phosphosilicate glass), silicon
oxynitride, silicon nitride (such as Si.sub.3N.sub.4) or silicon
carbon nitride (such as SiCN). The passivation layer 10 on pads 18
of the metallization structure and on the topmost metal layers 14
of the metallization structure typically has a thickness t3 of more
than 0.3 .mu.m, such as between 0.3 and 2 .mu.m or between 0.8 and
1.5 .mu.m. In a preferred case, the passivation layer 10 includes a
topmost silicon nitride layer of the semiconductor chip 2, wherein
the topmost silicon nitride layer in the passivation layer 10 has a
thickness of more than 0.2 .mu.m, such as between 0.3 and 1.2
.mu.m, wherein the passivation layer has first and second portions,
and each of the metal bumps 12 shown in FIG. 1 has a metal portion
between the first and second portions of the passivation layer 10
and on the pad 18. Fifteen methods for depositing the passivation
layer 10 are described as below.
[0044] In a first method, the passivation layer 10 is formed by
depositing a silicon oxide layer with a thickness of between 0.2
and 1.2 .mu.m using a CVD method and then depositing a silicon
nitride layer with a thickness of 0.2 and 1.2 .mu.m on the silicon
oxide layer using a CVD method.
[0045] In a second method, the passivation layer 10 is formed by
depositing a silicon oxide layer with a thickness of between 0.2
and 1.2 .mu.m using a CVD method, next depositing a silicon
oxynitride layer with a thickness of between 0.05 and 0.15 .mu.m on
the silicon oxide layer using a Plasma Enhanced CVD (PECVD) method,
and then depositing a silicon nitride layer with a thickness of
between 0.2 and 1.2 .mu.m on the silicon oxynitride layer using a
CVD method.
[0046] In a third method, the passivation layer 10 is formed by
depositing a silicon oxynitride layer with a thickness of between
0.05 and 0.15 .mu.m using a CVD method, next depositing a silicon
oxide layer with a thickness of between 0.2 and 1.2 .mu.m on the
silicon oxynitride layer using a CVD method, and then depositing a
silicon nitride layer with a thickness of between 0.2 and 1.2 .mu.m
on the silicon oxide layer using a CVD method.
[0047] In a fourth method, the passivation layer 10 is formed by
depositing a first silicon oxide layer with a thickness of between
0.2 and 0.5 .mu.m using a CVD method, next depositing a second
silicon oxide layer with a thickness of between 0.5 and 1 .mu.m on
the first silicon oxide layer using a spin-coating method, next
depositing a third silicon oxide layer with a thickness of between
0.2 and 0.5 .mu.m on the second silicon oxide layer using a CVD
method, and then depositing a silicon nitride layer with a
thickness of 0.2 and 1.2 .mu.m on the third silicon oxide using a
CVD method.
[0048] In a fifth method, the passivation layer 10 is formed by
depositing a silicon oxide layer with a thickness of between 0.5
and 2 .mu.m using a High Density Plasma CVD (HDP-CVD) method and
then depositing a silicon nitride layer with a thickness of 0.2 and
1.2 .mu.m on the silicon oxide layer using a CVD method.
[0049] In a sixth method, the passivation layer 10 is formed by
depositing an Undoped Silicate Glass (USG) layer with a thickness
of between 0.2 and 3 .mu.m, next depositing an insulating layer of
TEOS, PSG or BPSG (borophosphosilicate glass) with a thickness of
between 0.5 and 3 .mu.m on the USG layer, and then depositing a
silicon nitride layer with a thickness of 0.2 and 1.2 .mu.m on the
insulating layer using a CVD method.
[0050] In a seventh method, the passivation layer 10 is formed by
optionally depositing a first silicon oxynitride layer with a
thickness of between 0.05 and 0.15 .mu.m using a CVD method, next
depositing a silicon oxide layer with a thickness of between 0.2
and 1.2 .mu.m on the first silicon oxynitride layer using a CVD
method, next optionally depositing a second silicon oxynitride
layer with a thickness of between 0.05 and 0.15 .mu.m on the
silicon oxide layer using a CVD method, next depositing a silicon
nitride layer with a thickness of between 0.2 and 1.2 .mu.m on the
second silicon oxynitride layer or on the silicon oxide using a CVD
method, next optionally depositing a third silicon oxynitride layer
with a thickness of between 0.05 and 0.15 .mu.m on the silicon
nitride layer using a CVD method, and then depositing a silicon
oxide layer with a thickness of between 0.2 and 1.2 .mu.m on the
third silicon oxynitride layer or on the silicon nitride layer
using a CVD method.
[0051] In a eighth method, the passivation layer 10 is formed by
depositing a first silicon oxide layer with a thickness of between
0.2 and 1.2 .mu.m using a CVD method, next depositing a second
silicon oxide layer with a thickness of between 0.5 and 1 .mu.m on
the first silicon oxide layer using a spin-coating method, next
depositing a third silicon oxide layer with a thickness of between
0.2 and 1.2 .mu.m on the second silicon oxide layer using a CVD
method, next depositing a silicon nitride layer with a thickness of
between 0.2 and 1.2 .mu.m on the third silicon oxide layer using a
CVD method, and then depositing a fourth silicon oxide layer with a
thickness of between 0.2 and 1.2 .mu.m on the silicon nitride layer
using a CVD method.
[0052] In a ninth method, the passivation layer 10 is formed by
depositing a first silicon oxide layer with a thickness of between
0.5 and 2 .mu.m using a HDP-CVD method, next depositing a silicon
nitride layer with a thickness of between 0.2 and 1.2 .mu.m on the
first silicon oxide layer using a CVD method, and then depositing a
second silicon oxide layer with a thickness of between 0.5 and 2
.mu.m on the silicon nitride using a HDP-CVD method.
[0053] In a tenth method, the passivation layer 10 is formed by
depositing a first silicon nitride layer with a thickness of
between 0.2 and 1.2 .mu.m using a CVD method, next depositing a
silicon oxide layer with a thickness of between 0.2 and 1.2 .mu.m
on the first silicon nitride layer using a CVD method, and then
depositing a second silicon nitride layer with a thickness of
between 0.2 and 1.2 .mu.m on the silicon oxide layer using a CVD
method.
[0054] In a eleventh method, the passivation layer 10 is formed by
depositing a single layer of silicon nitride with a thickness of
between 0.2 and 1.5 .mu.m, and preferably of between 0.3 and 1.2
.mu.m, using a CVD method, by depositing a single layer of silicon
oxynitride with a thickness of between 0.2 and 1.5 .mu.m, and
preferably of between 0.3 and 1.2 .mu.m, using a CVD method, or by
depositing a single layer of silicon carbon nitride with a
thickness of between 0.2 and 1.5 .mu.m, and preferably of between
0.3 and 1.2 .mu.m, using a CVD method.
[0055] In a twelfth method, the passivation layer 10 is formed by
depositing a silicon oxide layer with a thickness of between 0.2
and 1.2 .mu.m using a CVD method and then depositing a silicon
carbon nitride layer with a thickness of 0.2 and 1.2 .mu.m on the
silicon oxide layer using a CVD method.
[0056] In a thirteenth method, the passivation layer 10 is formed
by depositing a first silicon carbon nitride layer with a thickness
of between 0.2 and 1.2 .mu.m using a CVD method, next depositing a
silicon oxide layer with a thickness of between 0.2 and 1.2 .mu.m
on the first silicon carbon nitride layer using a CVD method, and
then depositing a second silicon carbon nitride layer with a
thickness of 0.2 and 1.2 .mu.m on the silicon oxide layer using a
CVD method.
[0057] In a fourteenth method, the passivation layer 10 is formed
by depositing a silicon carbon nitride layer with a thickness of
between 0.2 and 1.2 .mu.m using a CVD method, next depositing a
silicon oxide layer with a thickness of between 0.2 and 1.2 .mu.m
on the silicon carbon nitride layer using a CVD method, and then
depositing a silicon nitride layer with a thickness of 0.2 and 1.2
.mu.m on the silicon oxide layer using a CVD method.
[0058] In a fifteenth method, the passivation layer 10 is formed by
depositing a silicon nitride layer with a thickness of between 0.2
and 1.2 .mu.m using a CVD method, next depositing a silicon oxide
layer with a thickness of between 0.2 and 1.2 .mu.m on the silicon
nitride layer using a CVD method, and then depositing a silicon
carbon nitride layer with a thickness of 0.2 and 1.2 .mu.m on the
silicon oxide layer using a CVD method.
[0059] Openings 10a in the passivation layer 10 expose the pads 18
of the metallization structure used to input or output signals or
to be connected to a power source or a ground reference. The
neighboring pads 18 are separated from each other by an insulating
material. The pads 18 are provided by a topmost metal layer under
the passivation layer 10. Each of the pads 18 has a thickness t4 of
between 0.5 and 3 .mu.m, and the pads 18 can be connected to the
semiconductor devices 6 through the metal layers 14 and the metal
plugs 16. The pads 18 may be composed of a sputtered aluminum layer
or a sputtered aluminum-copper-alloy layer with a thickness of
between 0.5 and 3 .mu.m. Alternatively, the pads 18 may include a
copper layer with a thickness of between 0.5 and 3 .mu.m, and a
barrier layer, such as tantalum or tantalum nitride, on a bottom
surface and sidewalls of the copper layer, wherein the copper layer
may include electroplated copper.
[0060] Therefore, the pads 18 can be aluminum pads, principally
made of sputtered aluminum with a thickness of between 0.5 and 3
.mu.m. Alternatively, the pads 18 can be copper pads, principally
made of electroplated copper with a thickness of between 0.5 and 3
.mu.m.
[0061] The openings 10a may have a transverse dimension, from a top
view, of between 0.5 and 20 .mu.m or between 20 and 200 .mu.m. The
shape of the openings 10a from a top view may be a circle, and the
diameter of the circle-shaped openings 10a may be between 0.5 and
20 .mu.m or between 20 and 200 .mu.m. Alternatively, the shape of
the openings 10a from a top view may be a square, and the width of
the square-shaped openings 10a may be between 0.5 and 20 .mu.m or
between 20 and 200 .mu.m. Alternatively, the shape of the openings
10a from a top view may be a polygon, such as hexagon or octagon,
and the polygon-shaped openings 10a may have a width of between 0.5
and 20 .mu.m or between 20 and 200 .mu.m. Alternatively, the shape
of the openings 10a from a top view may be a rectangle, and the
rectangle-shaped openings 10a may have a shorter width of between
0.5 and 20 .mu.m or between 20 and 200 .mu.m.
[0062] Metal caps (not shown) having a thickness of between 0.4 and
5 .mu.m, and preferably of between 0.4 and 2 .mu.m, can be
optionally formed on the pads 18 exposed by the openings 10a in the
passivation layer 10 to prevent the pads 18 from being oxidized or
contaminated. The material of the metal caps may include aluminum,
an aluminum-copper alloy or an Al--Si--Cu alloy. For example, when
the pads 18 are copper pads, the metal caps including aluminum are
used to protect the copper pads 18 from being oxidized. The metal
caps may comprise a barrier layer having a thickness of between
0.01 and 0.5 .mu.m on the pads 18. The barrier layer may be made of
titanium, titanium nitride, titanium-tungsten alloy, tantalum,
tantalum nitride, chromium or nickel.
[0063] For example, the metal caps may include a
tantalum-containing layer, such as tantalum layer or
tantalum-nitride layer, having a thickness of between 0.01 and 0.5
.mu.m on the pads 18, principally made of electroplated copper,
exposed by the opening 10a, and an aluminum-containing layer, such
as aluminum layer or aluminum-copper-alloy layer, having a
thickness of between 0.4 and 3 .mu.m on the tantalum-containing
layer.
[0064] The metal bumps 12 can be formed, respectively, on the pads
18, such as aluminum pads or copper pads, exposed by the openings
10a, and a pitch P1 between the neighboring metal bumps 12 is
greater than 5 micrometers or less than 35 micrometers, such as
between 15 and 35 micrometers, between 10 and 30 micrometers or
between 5 and 20 micrometers. The metal bumps 12 can be formed of
an adhesion/barrier layer having a thickness of between 0.03 and
0.7 .mu.m, and preferably of between 0.25 and 0.35 .mu.m, on the
pads 18 exposed by the openings 10a and a metal layer having a
thickness of between 5 and 50 micrometers, and preferably of
between 10 and 25 micrometers, on the adhesion/barrier layer. The
adhesion/barrier layer may be titanium, a titanium-tungsten alloy,
titanium nitride, chromium, tantalum, tantalum nitride or a
composite of the above-mentioned materials, and the
adhesion/barrier layer can be formed by a physical vapor deposition
(PVD) process, such as a sputtering process or an evaporation
process. The metal layer may be gold, copper, silver, nickel,
palladium, tin or a composite of the above-mentioned materials, and
the metal layer may be formed by a process including a sputtering
process, an electroplating process or an electroless plating
process. Below, the process of forming the metal bumps 12 is
exemplified with the case of forming the metal bumps 12 on the pads
18, such as aluminum pads or copper pads, exposed by the openings
10a. Alternatively, the metal bumps 12 can be formed on the metal
caps, such as aluminum caps, wherein the metal caps are formed on
the pads 18, such as copper pads, exposed by the openings 10a.
[0065] FIGS. 1a-1e are schematically cross-sectional figures
showing a process of forming the metal bumps 12 on a semiconductor
wafer 20. The above-mentioned semiconductor chip 2 is cut from the
semiconductor wafer 20. Before cutting the semiconductor wafer 20,
the metal bumps 12 are formed on the semiconductor wafer 20.
[0066] Referring to FIG. 1a, an adhesion/barrier layer 22 having a
thickness t5 of between 0.01 and 0.7 .mu.m, and preferably of
between 0.03 and 0.7 .mu.m, can be formed on the passivation layer
10 and on the pads 18, such as aluminum pads or copper pads,
exposed by the openings 10a. The adhesion/barrier layer 22 can be
formed by a physical vapor deposition (PVD) process, such as a
sputtering process or an evaporation process. The material of the
adhesion/barrier layer 22 may be titanium, a titanium-tungsten
alloy, titanium nitride, chromium, tantalum, tantalum nitride or a
composite of the above-mentioned materials. In a case, the
adhesion/barrier layer 22 can be formed by sputtering a
titanium-tungsten-alloy layer with a thickness of between 0.03 and
0.7 .mu.m, and preferably of between 0.15 and 0.4 .mu.m, on the
passivation layer 10 and on the pads 18, such as aluminum pads or
copper pads, exposed by the openings 10a. In another case, the
adhesion/barrier layer 22 can be formed by sputtering a titanium
layer with a thickness of between 0.01 and 0.7 .mu.m, and
preferably of between 0.01 and 0.15 .mu.m, on the passivation layer
10 and on the pads 18, such as aluminum pads or copper pads,
exposed by the openings 10a. In another case, the adhesion/barrier
layer 22 can be formed by sputtering a titanium-nitride layer with
a thickness of between 0.01 and 0.1 .mu.m, and preferably of
between 0.01 and 0.02 .mu.m, on the passivation layer 10 and on the
pads 18, such as aluminum pads or copper pads, exposed by the
openings 10a. In another case, the adhesion/barrier layer 22 can be
formed by sputtering a titanium layer with a thickness of between
0.01 and 0.15 .mu.m on the passivation layer 10 and on the pads 18,
such as aluminum pads or copper pads, exposed by the openings 10a,
and then sputtering a titanium-tungsten-alloy layer with a
thickness of between 0.1 and 0.35 .mu.m on the titanium layer. The
adhesion/barrier layer 22 is used to prevent the occurrence of
interdiffusion between metal layers and to provide good adhesion
between the metal layers.
[0067] Next, a seed layer 24 having a thickness t6 of between 0.03
and 1 .mu.m, and preferably of between 0.05 and 0.2 .mu.m, can be
formed on the adhesion/barrier layer 22. The seed layer 24 can be
formed by a physical vapor deposition (PVD) process, such as a
sputtering process or an evaporation process. The seed layer 24 is
beneficial to electroplating a metal layer thereon.
[0068] For example, when the adhesion/barrier layer 22 is formed by
sputtering a titanium-containing layer, the seed layer 24 can be
formed by sputtering a gold layer with a thickness of between 0.03
and 1 .mu.m, and preferably of between 0.05 and 0.2 .mu.m, on the
titanium-containing layer. When the adhesion/barrier layer 22 is
formed by sputtering a titanium-containing layer, the seed layer 24
can be formed by sputtering a copper layer with a thickness of
between 0.03 and 1 .mu.m, and preferably of between 0.1 and 0.5
.mu.m, on the titanium-containing layer. The above-mentioned
titanium-containing layer can be a single titanium-tungsten-alloy
layer having a thickness of between 0.03 and 0.7 .mu.m, and
preferably of between 0.15 and 0.4 .mu.m, a single titanium layer
having a thickness of between 0.01 and 0.7 .mu.m, and preferably of
between 0.01 and 0.15 .mu.m, a single titanium-nitride layer having
a thickness of between 0.01 and 0.1 .mu.m, and preferably of
between 0.01 and 0.02 .mu.m, or a composite layer comprising a
titanium layer having a thickness of between 0.01 and 0.15 .mu.m,
and a titanium-tungsten-alloy layer, having a thickness of between
0.1 and 0.35 .mu.m, on the titanium layer.
[0069] Referring to FIG. 1b, a photoresist layer 26, such as
positive-type photoresist layer or negative-type photoresist layer,
having a thickness of between 5 and 50 micrometers, and preferably
of between 10 and 25 micrometers, is spin-on coated on the seed
layer 24. Next, the photoresist layer 26 is patterned with the
processes of exposure and development to form openings 26a in the
photoresist layer 26 exposing the seed layer 24. A 1X stepper or 1X
contact aligner can be used to expose the photoresist layer 26
during the process of exposure.
[0070] For example, the photoresist layer 26 can be formed by
spin-on coating a positive-type photosensitive polymer layer having
a thickness of between 5 and 50 .mu.m, and preferably of between 15
and 20 .mu.m, on the seed layer 24, then exposing the
photosensitive polymer layer using a 1X stepper or contact aligner
with at least two of G-line, H-line and I-line, wherein G-line has
a wavelength ranging from 434 to 438 nm, H-line has a wavelength
ranging from 403 to 407 nm, and I-line has a wavelength ranging
from 363 to 367 nm, then developing the exposed polymer layer by
spraying and puddling a developer on a wafer or by immersing a
wafer into a developer, and then cleaning the wafer using deionized
wafer and drying the wafer by sprining the wafer. After
development, a scum removal process of removing the residual
polymeric material or other contaminants from the seed layer 24 may
be conducted by using an O.sub.2 plasma or a plasma containing
fluorine of below 200 PPM and oxygen. By these processes, the
photoresist layer 26 can be patterned with the openings 26a in the
photoresist layer 26 exposing the seed layer 24.
[0071] Referring to FIG. 1c, a metal layer 28 having a thickness t7
of between 5 and 50 micrometers, and preferably of between 10 and
25 micrometers, can be electroplated and/or electroless plated on
the seed layer 24 exposed by the openings 26a. The material of the
metal layer 28 may be gold, copper, nickel, silver, tin, palladium
or a composite of the above-mentioned materials.
[0072] For example, the metal layer 28 may be formed by
electroplating a gold layer with a thickness of between 5 and 50
.mu.m, and preferably of between 10 and 25 micrometers, on the seed
layer 24, made of gold, exposed by the opening 26a with a
non-cyanide electroplating solution, such as a solution containing
gold sodium sulfite (Na.sub.3Au(SO.sub.3).sub.2) or a solution
containing gold ammonium sulfite
((NH.sub.4).sub.3[Au(SO.sub.3).sub.2]), or with an electroplating
solution containing cyanide. Alternatively, the metal layer 28 may
be formed by electroplating a copper layer having a thickness of
between 0.5 and 45 .mu.m, and preferably of between 5 and 35
micrometers, on the seed layer 24, made of copper, exposed by the
opening 26a, then electroplating a nickel layer having a thickness
of between 0.5 and 5 .mu.m, and preferably of between 1 and 3
micrometers, on the copper layer in the opening 26a, and then
electroplating a gold layer having a thickness of between 0.5 and 5
.mu.m, and preferably of between 1 and 3 micrometers, on the nickel
layer in the opening 26a with a non-cyanide electroplating
solution, such as a solution containing gold sodium sulfite
(Na.sub.3Au(SO.sub.3).sub.2) or a solution containing gold ammonium
sulfite ((NH.sub.4).sub.3[Au(SO.sub.3).sub.2]), or with an
electroplating solution containing cyanide. Alternatively, the
metal layer 28 may be formed by electroplating a copper layer
having a thickness of between 0.5 and 45 .mu.m, and preferably of
between 5 and 35 micrometers, on the seed layer 24, made of copper,
exposed by the opening 26a, and then electroplating a gold layer
having a thickness of between 0.5 and 5 .mu.m, and preferably of
between 1 and 3 micrometers, on the copper layer in the opening 26a
with a non-cyanide electroplating solution, such as a solution
containing gold sodium sulfite (Na.sub.3Au(SO.sub.3).sub.2) or a
solution containing gold ammonium sulfite
((NH.sub.4).sub.3[Au(SO.sub.3).sub.2]), or with an electroplating
solution containing cyanide. Alternatively, the metal layer 28 may
be formed by electroplating a nickel layer having a thickness of
between 0.5 and 45 .mu.m, and preferably of between 5 and 35
micrometers, on the seed layer 24, made of copper, exposed by the
opening 26a, and then electroplating a gold layer having a
thickness of between 0.5 and 5 .mu.m, and preferably of between 1
and 3 micrometers, on the nickel layer in the opening 26a with a
non-cyanide electroplating solution, such as a solution containing
gold sodium sulfite (Na.sub.3Au(SO.sub.3).sub.2) or a solution
containing gold ammonium sulfite
((NH.sub.4).sub.3[Au(SO.sub.3).sub.2]), or with an electroplating
solution containing cyanide.
[0073] Referring to FIG. 1d, after the metal layer 28 is formed,
most of the photoresist layer 26 can be removed using an organic
solution with amide or a solution containing H.sub.2SO.sub.4 and
H.sub.2O.sub.2. However, some residuals from the photoresist layer
26 could remain on the metal layer 28 and on the seed layer 24.
Thereafter, the residuals can be removed from the metal layer 28
and from the seed layer 24 with a plasma, such as O.sub.2 plasma or
plasma containing fluorine of below 200 PPM and oxygen.
[0074] Referring to FIG. 1e, the seed layer 24 and the
adhesion/barrier layer 22 not under the metal layer 28 are
subsequently removed with a wet etching method or a dry etching
method. The dry etching method may be an Ar sputtering etching
process or a reactive ion etching (RIE) process. As to the wet
etching method, when the seed layer 24 is a gold layer, it can be
etched with an iodine-containing solution, such as solution
containing potassium iodide; when the seed layer 24 a copper layer,
it can be etched with a solution containing NH.sub.4OH or with a
solution containing H.sub.2SO.sub.4; when the adhesion/barrier
layer 22 is a titanium-tungsten-alloy layer, it can be etched with
a solution containing hydrogen peroxide or with a solution
containing NH.sub.4OH and hydrogen peroxide; when the
adhesion/barrier layer 22 is a titanium layer, it can be etched
with a solution containing hydrogen fluoride or with a solution
containing NH.sub.4OH and hydrogen peroxide; when the
adhesion/barrier layer 22 is a chromium layer, it can be etched
with a solution containing potassium ferricyanide.
[0075] Thereby, in the present invention, the metal bumps 12 can be
formed, respectively, on the pads 18, such as aluminum pads or
copper pads, exposed by the openings 10a, and the pitch P1 between
the neighboring metal bumps 12 is greater than 5 micrometers or
less than 35 micrometers, such as between 15 and 35 micrometers,
between 10 and 30 micrometers or between 5 and 20 micrometers. The
metal bumps 12 can be formed of the adhesion/barrier layer 22 on
the pads 18 and a bump metal layer (including the seed layer 24 and
the metal layer 28 on the seed layer 24), having a thickness of
between 5 and 30 micrometers, and preferably of between 10 and 25
micrometers, on the adhesion/barrier layer 22.
[0076] In a case, the metal bumps 12 may include a
titanium-containing layer on the pads 18 exposed by the openings
10a, and a gold layer having a thickness of between 5 and 50
micrometers, and preferably of between 10 and 25 micrometers, on
the titanium-containing layer. In another case, the metal bumps 12
may include a titanium-containing layer on the pads 18 exposed by
the openings 10a, a copper layer having a thickness of between 0.5
and 45 micrometers, and preferably of between 5 and 35 micrometers,
on the titanium-containing layer, a nickel layer having a thickness
of between 0.5 and 5 micrometers, and preferably of between 1 and 3
micrometers, on the copper layer, and a gold layer having a
thickness of between 0.5 and 5 micrometers, and preferably of
between 1 and 3 micrometers, on the nickel layer. In another case,
the metal bumps 12 may include a titanium-containing layer on the
pads 18 exposed by the openings 10a, a copper layer having a
thickness of between 0.5 and 45 micrometers, and preferably of
between 5 and 35 micrometers, on the titanium-containing layer, and
a gold layer having a thickness of between 0.5 and 5 micrometers,
and preferably of between 1 and 3 micrometers, on the copper layer.
In another case, the metal bumps 12 may include a
titanium-containing layer on the pads 18 exposed by the openings
10a, a copper layer, formed by a sputtering process, having a
thickness of between 0.03 and 1 .mu.m, and preferably of between
0.1 and 0.5 .mu.m, on the titanium-containing layer, a nickel
layer, formed by an electroplating process, having a thickness of
between 0.5 and 45 micrometers, and preferably of between 5 and 35
micrometers, on the copper layer, and a gold layer, formed by an
electroplating process, having a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
nickel layer. The above-mentioned titanium-containing layer can be
a single titanium-tungsten-alloy layer having a thickness of
between 0.03 and 0.7 .mu.m, and preferably of between 0.15 and 0.4
.mu.m, a single titanium layer having a thickness of between 0.01
and 0.7 .mu.m, and preferably of between 0.01 and 0.15 .mu.m, a
single titanium-nitride layer having a thickness of between 0.01
and 0.1 .mu.m, and preferably of between 0.01 and 0.02 .mu.m, or a
composite layer comprising a titanium layer having a thickness of
between 0.01 and 0.15 .mu.m on the pads 18 exposed by the openings
10a, and a titanium-tungsten-alloy layer having a thickness of
between 0.1 and 0.35 .mu.m on the titanium layer.
[0077] Multiple undercuts 29 may be formed under the seed layer 24
and under the metal layer 28 when the adhesion/barrier layer 22 not
under the metal layer 28 is removed using a wet etching method. The
adhesion/barrier layer 22 under the metal layer 28 has a first
sidewall recessed from a second sidewall of the seed layer 24,
wherein a distance D between the first sidewall and the second
sidewall is between 0.3 and 2 micrometers.
[0078] However, the undercuts 29 could result in the dramatical
drop of the contact area between the metal bump 12, especially fine
pitch metal bump, and the passivation layer 10. For avoiding the
undesired undercuts 29, the adhesion/barrier layer 22 not under the
metal layer 28 can be alternatively removed using the
above-mentioned dry etching method.
[0079] After the metal bumps 12 are formed, the semiconductor wafer
20 can be cut into the semiconductor chips 2 by a mechanical
cutting process. The fine-pitched metal bumps 12 are formed on the
pads 18, of each semiconductor chips 2, exposed by the openings
10a.
[0080] Referring to FIG. 2, alternatively, the semiconductor chip 2
cut from the semiconductor wafer includes the semiconductor
substrate 4, the semiconductor devices 6, the metallization
structure (including the patterned metal layers 14 and the metal
plugs 16), the dielectric layers 8, the passivation layer 10, a
polymer layer 30, multiple metal traces 32, the metal bumps 12 and
a polymer layer 34. The specification of the semiconductor
substrate 4, the semiconductor devices 6, the metallization
structure (including the patterned metal layers 14 and the metal
plugs 16), the dielectric layers 8 and the passivation layer 10
shown in FIG. 2 can be referred to as the specification of the
semiconductor substrate 4, the semiconductor devices 6, the
metallization structure (including the patterned metal layers 14
and the metal plugs 16), the dielectric layers 8 and the
passivation layer 10 illustrated in FIG. 1. The process, of forming
the metallization structure (including the patterned metal layers
14 and the metal plugs 16), the dielectric layers 8 and the
passivation layer 10, as shown in FIG. 2 can be referred to as the
process, of forming the metallization structure (including the
patterned metal layers 14 and the metal plugs 16), the dielectric
layers 8 and the passivation layer 10, as illustrated in FIG.
1.
[0081] The polymer layer 30 having a thickness t8 of between 3 and
25 .mu.m can be formed on the passivation layer 10 by a process
including a spin-on coating process, a lamination process or a
screen-printing process. The material of the polymer layer 30 may
include benzocyclobutane (BCB), polyimide (PT), polybenzoxazole
(PBO) or epoxy resin.
[0082] For example, the polymer layer 30 can be formed by spin-on
coating a negative-type photosensitive polyimide layer having a
thickness of between 6 and 50 .mu.m on the passivation layer 10 and
on the pads 18 exposed by the openings 10a, then baking the spin-on
coated polyimide layer, then exposing the baked polyimide layer
using a 1X stepper or 1X contact aligner with at least two of
G-line having a wavelength ranging from 434 to 438 nm, H-line
having a wavelength ranging from 403 to 407 nm, and I-line having a
wavelength ranging from 363 to 367 nm, illuminating the baked
polyimide layer, that is, G-line and H-line, G-line and I-line,
H-line and I-line, or G-line, H-line and I-line illuminate the
baked polyimide layer, then developing the exposed polyimide layer
to form a patterned polyimide layer on the passivation layer 10,
then curing or heating the patterned polyimide layer at a peak
temperature of between 180 and 400.degree. C. for a time of between
20 and 150 minutes in a nitrogen ambient or in an oxygen-free
ambient, the cured polyimide layer having a thickness of between 3
and 25 .mu.m, and then removing the residual polymeric material or
other contaminants from the upper surface of the pads 18 with an
O.sub.2 plasma or a plasma containing fluorine of below 200 PPM and
oxygen, such that the polymer layer 30 can be formed on the
passivation layer 10. For example, the patterned polyimide layer
can be cured or heated at a temperature between 180 and 250.degree.
C. for a time of between 20 and 150 minutes in a nitrogen ambient
or in an oxygen-free ambient. Alternatively, the patterned
polyimide layer can be cured or heated at a temperature between 250
and 290.degree. C. for a time of between 20 and 150 minutes in a
nitrogen ambient or in an oxygen-free ambient. Alternatively, the
patterned polyimide layer can be cured or heated at a temperature
between 290 and 400.degree. C. for a time of between 20 and 150
minutes in a nitrogen ambient or in an oxygen-free ambient.
Alternatively, the patterned polyimide layer can be cured or heated
at a temperature between 250 and 400.degree. C. for a time of
between 20 and 150 minutes in a nitrogen ambient or in an
oxygen-free ambient.
[0083] Alternatively, the polymer layer 30 can be formed by spin-on
coating a positive-type photosensitive polybenzoxazole layer having
a thickness of between 3 and 25 .mu.m on the passivation layer 10
and on the pads 18 exposed by the openings 10a, then baking the
spin-on coated polybenzoxazole layer, then exposing the baked
polybenzoxazole layer using a 1X stepper or 1X contact aligner with
at least two of G-line having a wavelength ranging from 434 to 438
nm, H-line having a wavelength ranging from 403 to 407 nm, and
I-line having a wavelength ranging from 363 to 367 nm, illuminating
the baked polyimide layer, that is, G-line and H-line, G-line and
I-line, H-line and I-line, or G-line, H-line and I-line illuminate
the baked polybenzoxazole layer, then developing the exposed
polybenzoxazole layer to form a patterned polybenzoxazole layer on
the passivation layer 10, then curing or heating the patterned
polybenzoxazole layer at a peak temperature of between 150 and
250.degree. C., and preferably of between 180 and 250.degree. C.,
for a time of between 5 and 180 minutes, and preferably of between
30 and 120 minutes, in a nitrogen ambient or in an oxygen-free
ambient, the cured polybenzoxazole layer having a thickness of
between 3 and 25 .mu.m, and then removing the residual polymeric
material or other contaminants from the upper surface of the pads
18 with an O.sub.2 plasma or a plasma containing fluorine of below
200 PPM and oxygen, such that the polymer layer 30 can be formed on
the passivation layer 10. Alternatively, the patterned
polybenzoxazole layer can be cured or heated at a temperature
between 200 and 400.degree. C., and preferably of between 250 and
350.degree. C., for a time of between 5 and 180 minutes, and
preferably of between 30 and 120 minutes, in a nitrogen ambient or
in an oxygen-free ambient.
[0084] Each of the metal traces 32 having a thickness t9 of between
1 and 30 micrometers, and preferably of between 5 and 20
micrometers, can be formed on the passivation layer 10, on the
polymer layer 30 and on the pads 18 exposed by the openings 10a,
wherein the metal trace 32 may connect one of the pads 18 to
another one of the pads 18. The metal traces 32 may include
titanium, a titanium-tungsten alloy, titanium nitride, chromium,
tantalum, tantalum nitride, gold, copper, nickel or a composite of
the above-mentioned materials, and the metal traces 32 may be
formed by a process including a sputtering process, an
electroplating process or an electroless plating process.
[0085] In a case, the metal traces 32 may include a
titanium-containing layer on the pads 18 exposed by the openings
10a, on the passivation layer 10 and on the polymer layer 30, and a
gold layer having a thickness of between 1 and 30 micrometers, and
preferably of between 5 and 20 micrometers, on the
titanium-containing layer. In another case, the metal traces 32 may
include a titanium-containing layer on the pads 18 exposed by the
openings 10a, on the passivation layer 10 and on the polymer layer
30, and a copper layer having a thickness of between 1 and 30
micrometers, and preferably of between 5 and 20 micrometers, on the
titanium-containing layer. In another case, the metal traces 32 may
include a titanium-containing layer on the pads 18 exposed by the
openings 10a, on the passivation layer 10 and on the polymer layer
30, and a nickel layer having a thickness of between 1 and 30
micrometers, and preferably of between 5 and 20 micrometers, on the
titanium-containing layer. In another case, the metal traces 32 may
include a titanium-containing layer on the pads 18 exposed by the
openings 10a, on the passivation layer 10 and on the polymer layer
30, a copper layer having a thickness of between 1 and 25
micrometers, and preferably of between 3 and 15 micrometers, on the
titanium-tungsten-alloy layer, a nickel layer having a thickness of
between 0.5 and 2.5 micrometers, and preferably of between 1 and
2.5 micrometers, on the copper layer, and a gold layer having a
thickness of between 0.5 and 2.5 micrometers, and preferably of
between 1 and 2.5 micrometers, on the nickel layer. In another
case, the metal traces 32 may include a titanium-containing layer
on the pads 18 exposed by the openings 10a, on the passivation
layer 10 and on the polymer layer 30, a copper layer having a
thickness of between 1 and 25 .mu.m, and preferably of between 3
and 15 micrometers, on the titanium-containing layer, and a gold
layer having a thickness of between 0.5 and 5 micrometers, and
preferably of between 2 and 5 micrometers, on the copper layer. In
another case, the metal traces 32 may include a titanium-containing
layer on the pads 18 exposed by the openings 10a, on the
passivation layer 10 and on the polymer layer 30, a copper layer,
formed by a sputtering process, having a thickness of between 0.03
and 1 .mu.m, and preferably of between 0.1 and 0.5 .mu.m, on the
titanium-containing layer, a nickel layer, formed by an
electroplating process, having a thickness of between 0.5 and 25
micrometers, and preferably of between 3 and 15 micrometers, on the
sputtered copper layer, and a gold layer, formed by an
electroplating process, having a thickness of between 0.5 and 5
micrometers, and preferably of between 2 and 5 micrometers, on the
nickel layer. In another case, the metal traces 32 may include a
titanium-containing layer on the pads 18 exposed by the openings
10a, on the passivation layer 10 and on the polymer layer 30, a
copper layer, formed by a sputtering process, having a thickness of
between 0.03 and 1 .mu.m, and preferably of between 0.1 and 0.5
.mu.m, on the titanium-containing layer, and a nickel layer, formed
by an electroplating process, having a thickness of between 0.5 and
25 micrometers, and preferably of between 3 and 15 micrometers, on
the sputtered copper layer. The above-mentioned titanium-containing
layer can be a single titanium-tungsten-alloy layer having a
thickness of between 0.03 and 0.7 .mu.m, and preferably of between
0.15 and 0.4 .mu.m, a single titanium layer having a thickness of
between 0.01 and 0.7 .mu.m, and preferably of between 0.01 and 0.15
.mu.m, a single titanium-nitride layer having a thickness of
between 0.01 and 0.1 .mu.m, and preferably of between 0.01 and 0.02
.mu.m, or a composite layer comprising a titanium layer having a
thickness of between 0.01 and 0.15 .mu.m, and a
titanium-tungsten-alloy layer, having a thickness of between 0.1
and 0.35 .mu.m, on the titanium layer.
[0086] The polymer layer 34 having a thickness t10 of between 1 and
25 .mu.m can be formed on the passivation layer 10, on the metal
traces 32 and on the polymer layer 30 by a process including a
spin-on coating process, a lamination process or a screen-printing
process. The polymer layer 34 uncovers the metal bumps 12 on the
metal traces 32, with openings 34a in the polymer layer 34 being
over the metal traces 32 having the metal bumps 12 formed thereon.
The material of the polymer layer 34 may include benzocyclobutane
(BCB), polyimide (PI), polybenzoxazole (PBO) or epoxy resin.
[0087] For example, the polymer layer 34 can be formed by spin-on
coating a negative-type photosensitive polyimide layer having a
thickness of between 2 and 50 .mu.m on the passivation layer 10, on
the metal traces 32, on the metal bumps 12 and on the polymer layer
30, then baking the spin-on coated polyimide layer, then exposing
the baked polyimide layer using a 1X stepper or 1X contact aligner
with at least two of G-line having a wavelength ranging from 434 to
438 nm, H-line having a wavelength ranging from 403 to 407 nm, and
I-line having a wavelength ranging from 363 to 367 nm, illuminating
the baked polyimide layer, that is, G-line and H-line, G-line and
I-line, H-line and I-line, or G-line, H-line and I-line illuminate
the baked polyimide layer, then developing the exposed polyimide
layer to uncover the metal bumps 12, then curing or heating the
developed polyimide layer at a peak temperature of between 180 and
400.degree. C. for a time of between 20 and 150 minutes in a
nitrogen ambient or in an oxygen-free ambient, the cured polyimide
layer having a thickness of between 3 and 25 .mu.m, and then
removing the residual polymeric material or other contaminants from
the upper surface of the metal bumps 12 and from the upper surface
of the metal traces 32 with an O.sub.2 plasma or a plasma
containing fluorine of below 200 PPM and oxygen, such that the
polymer layer 34 can be formed on the passivation layer 10, on the
metal traces 32 and on the polymer layer 30, uncovering the metal
bumps 12. For example, the developed polyimide layer can be cured
or heated at a temperature between 180 and 250.degree. C. for a
time of between 20 and 150 minutes in a nitrogen ambient or in an
oxygen-free ambient. Alternatively, the developed polyimide layer
can be cured or heated at a temperature between 250 and 290.degree.
C. for a time of between 20 and 150 minutes in a nitrogen ambient
or in an oxygen-free ambient. Alternatively, the developed
polyimide layer can be cured or heated at a temperature between 290
and 400.degree. C. for a time of between 20 and 150 minutes in a
nitrogen ambient or in an oxygen-free ambient. Alternatively, the
developed polyimide layer can be cured or heated at a temperature
between 250 and 400.degree. C. for a time of between 20 and 150
minutes in a nitrogen ambient or in an oxygen-free ambient.
[0088] Alternatively, the polymer layer 34 can be formed by spin-on
coating a positive-type photosensitive polybenzoxazole layer having
a thickness of between 3 and 25 .mu.m on the passivation layer 10,
on the metal traces 32 and on the polymer layer 30, then baking the
spin-on coated polybenzoxazole layer, then exposing the baked
polybenzoxazole layer using a 1X stepper or 1X contact aligner with
at least two of G-line having a wavelength ranging from 434 to 438
nm, H-line having a wavelength ranging from 403 to 407 nm, and
I-line having a wavelength ranging from 363 to 367 nm, illuminating
the baked polyimide layer, that is, G-line and H-line, G-line and
I-line, H-line and I-line, or G-line, H-line and I-line illuminate
the baked polybenzoxazole layer, then developing the exposed
polybenzoxazole layer to uncover the metal bumps 12, then curing or
heating the developed polybenzoxazole layer at a peak temperature
of between 200 and 400.degree. C., and preferably of between 250
and 350.degree. C., for a time of between 5 and 180 minutes, and
preferably of between 30 and 120 minutes, in a nitrogen ambient or
in an oxygen-free ambient, the cured polybenzoxazole layer having a
thickness of between 3 and 25 .mu.m, and then removing the residual
polymeric material or other contaminants from the upper surface of
the metal bumps 12 and from the upper surface of the metal traces
32 with an O.sub.2 plasma or a plasma containing fluorine of below
200 PPM and oxygen, such that the polymer layer 34 can be formed on
the passivation layer 10, on the metal traces 32 and on the polymer
layer 30, uncovering the metal bumps 12.
[0089] The metal bumps 12 are on the metal traces 32 exposed by the
openings 34a, and the pitch P2 between the neighboring metal bumps
12 is greater than 5 micrometers or less than 35 micrometers, such
as between 15 and 35 micrometers, between 10 and 30 micrometers or
between 5 and 20 micrometers. The metal bumps 12 may include
titanium, a titanium-tungsten alloy, titanium nitride, chromium,
tantalum, tantalum nitride, gold, copper, silver, nickel,
palladium, tin or a composite of the above-mentioned materials, and
the metal bumps 12 may be formed by a process including a
sputtering process, an electroplating process or an electroless
plating process.
[0090] For example, the specification of the metal bumps 12 shown
in FIG. 2 can be referred to as the specification of the metal
bumps 12 illustrated in FIG. 1 and FIGS. 1a-1e. Alternatively, the
metal bumps 12 can be formed by electroplating a gold layer with a
thickness of between 5 and 50 micrometers, and preferably of
between 10 and 25 micrometers, directly on the gold layer of the
metal traces 32, directly on the copper layer of the metal traces
32 or directly on the nickel layer of metal traces 32.
Alternatively, the metal bumps 12 can be formed by electroplating a
copper layer with a thickness of between 5 and 50 micrometers, and
preferably of between 10 and 25 micrometers, directly on the gold
layer of the metal traces 32, directly on the copper layer of the
metal traces 32 or directly on the nickel layer of metal traces 32.
Alternatively, the metal bumps 12 can be formed by electroplating a
copper layer with a thickness of between 0.5 and 45 micrometers,
and preferably of between 5 and 35 micrometers, directly on the
gold layer of the metal traces 32, directly on the copper layer of
the metal traces 32 or directly on the nickel layer of metal traces
32, and then electroplating a gold layer with a thickness of
between 0.5 and 5 micrometers, and preferably of between 1 and 3
micrometers, on the electroplated copper layer. Alternatively, the
metal bumps 12 can be formed by electroplating a copper layer with
a thickness of between 0.5 and 45 micrometers, and preferably of
between 5 and 35 micrometers, directly on the gold layer of the
metal traces 32, directly on the copper layer of the metal traces
32 or directly on the nickel layer of metal traces 32, then
electroplating a nickel layer with a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
electroplated copper layer, and then electroplating a gold layer
with a thickness of between 0.5 and 5 micrometers, and preferably
of between 1 and 3 micrometers, on the electroplated nickel
layer.
[0091] The above-mentioned metal bumps 12 of the semiconductor chip
2 can be joined with any one of various flexible circuit films 36,
38, 40, 42, 44, 46 and 48 as illustrated in the following
embodiments.
Embodiment 1
[0092] FIG. 3A is a schematically cross-sectional figure showing a
chip-on-film (COF) package. A flexible circuit film 36 includes a
polymer layer 200, a polymer layer 220 and multiple copper traces
210 between the polymer layers 200 and 220, wherein openings 200a
in the polymer layer 200 expose first contact points of the copper
traces 210 and openings 220a in the polymer layer 220 expose second
contact points of the copper traces 210. Each of the copper traces
210 has a thickness t11 of between 3 and 30 micrometers, of between
5 and 20 micrometers or of between 4 and 10 micrometers.
Alternatively, the copper traces 210 can be replaced by gold traces
having a thickness of between 3 and 30 .mu.m, of between 5 and 20
micrometers or of between 4 and 10 micrometers. Alternatively, the
copper traces 210 can be replaced by silver traces having a
thickness of between 3 and 30 .mu.m, of between 5 and 20
micrometers or of between 4 and 10 micrometers.
[0093] The polymer layer 200 has a thickness t13 of between 10 and
100 micrometers, of between 15 and 30 micrometers or of between 20
and 80 micrometers, and the material of the polymer layer 200 may
be polybenzoxazole, expoxy, polyester or polyimide. The polymer
layer 220 has a thickness t14 of between 5 and 30 micrometers, and
preferably of between 5 and 15 micrometers, and the material of the
polymer layer 220 may be polybenzoxazole, expoxy, polyester or
polyimide.
[0094] The flexible circuit film 36 further comprises a wetting
layer 240a on the first contact points of the copper traces 210
exposed by the openings 200a, and a wetting layer 240b on the
second contact points of the copper traces 210 exposed by the
openings 220a to be joined with the metal bumps 12 preformed on the
metal pads 18 or on the metal traces 32 of the semiconductor chip 2
shown in FIG. 1 or 2.
[0095] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210 of the flexible circuit film 36 exposed
by the openings 220a through an interface bonding layer 250. Two
methods for bonding the metal bumps 12 of the semiconductor chip 2
with the copper traces 210 of the flexible circuit film 36 are
described as shown in FIG. 3B and FIG. 3C.
[0096] Referring to FIGS. 3B and 3C, the flexible circuit film 36
can be connected to the semiconductor chip 2. The flexible circuit
film 36 has the wetting layer 240a to be joined with a substrate
300 shown in FIG. 3E, and the wetting layer 240b to be joined with
the metal bumps 12 preformed on the metal pads 18 or on the metal
traces 32 of the semiconductor chip 2 shown in FIG. 1 or 2. The
wetting layer 240a having a thickness of between 0.05 and 5
micrometers, and preferably of between 0.1 and 1 micrometer, may be
gold, copper, nickel, silver, palladium, tin or a composite of the
above-mentioned materials. For example, the wetting layer 240a may
be a tin-containing layer, such as pure tin, a tin-silver alloy, a
tin-silver-copper alloy or a tin-lead alloy, having a thickness of
between 0.05 and 5 micrometers, and preferably of between 0.1 and 1
micrometer, directly on the first contact points of the copper
traces 210. Alternatively, the wetting layer 240a may be a gold
layer having a thickness of between 0.05 and 5 micrometers, and
preferably of between 0.1 and 1 micrometer, directly on the first
contact points of the copper traces 210; optionally, a nickel layer
having a thickness between 0.05 and 1 micrometer may be between the
copper traces 210 and the gold layer. The wetting layer 240b having
a thickness of between 0.05 and 2 micrometers, and preferably of
between 0.1 and 1 micrometer, may be gold, copper, nickel, silver,
palladium, tin or a composite of the above-mentioned materials. For
example, the wetting layer 240b may be a tin-containing layer, such
as pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy, having a thickness of between 0.05 and 2
micrometers, and preferably of between 0.1 and 1 micrometer,
directly on the second contact points of the copper traces 210.
Alternatively, the wetting layer 240b may be a gold layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.1 and 1 micrometer, directly on the second contact points
of the copper traces 210; optionally, a nickel layer having a
thickness between 0.05 and 1 micrometer may be between the copper
traces 210 and the gold layer.
[0097] In a first case, referring to FIG. 3B, the metal bumps 12
have the above-mentioned gold layer, at the tips of the metal bumps
12, capable of being used to be joined with the wetting layer 240b
of pure tin or an above-mentioned tin alloy using gang bonding,
which process is described as below. First, the semiconductor chip
2 is held by vacuum adsorption on a stage 600 kept at a temperature
of between 250 and 500.degree. C., and preferably of between 350
and 450.degree. C. Next, the flexible circuit film 36 is thermally
pressed on the metal bumps 12 of the semiconductor chip 2 at a
force of between 20 and 150N, and preferably of between 50 and 90N,
for a time of between 0.1 and 10 seconds, and preferably of between
0.5 and 3 seconds, by a tool head 610 kept at a temperature of
between 150 and 450.degree. C., and preferably of between 250 and
400.degree. C., optionally applying ultrasonic waves to the metal
bumps 12 and to the wetting layer 240b of the flexible circuit film
36, to join the wetting layer 240b with the metal bumps 12.
Referring to FIGS. 3A and 3B, in the step of joining the wetting
layer 240b with the metal bumps 12, the interface bonding layer
250, such as a metal alloy, may be formed between the metal bumps
12 and the copper traces 210. The interface bonding layer 250 has a
thickness t12 of between 0.2 and 10 micrometers, and preferably of
between 0.4 and 5 micrometers. When the wetting layer 240b before
bonded with the gold layer of the metal bumps 12 is pure tin, the
interface bonding layer 250 is a tin-gold alloy having a thickness
of between 0.2 and 10 micrometers or of between 0.4 and 5
micrometers, wherein an atomic ratio of tin to gold in the tin-gold
alloy is between 0.2 and 0.3. When the wetting layer 240b before
bonded with the gold layer of the metal bumps 12 is a
tin-silver-copper alloy, the interface bonding layer 250 is a
tin-silver-gold-copper alloy having a thickness of between 0.2 and
10 micrometers or of between 0.4 and 5 micrometers. When the
wetting layer 240b before bonded with the gold layer of the metal
bumps 12 is a tin-silver alloy, the interface bonding layer 250 is
a tin-silver-gold alloy having a thickness of between 0.2 and 10
micrometers or of between 0.4 and 5 micrometers. When the wetting
layer 240b before bonded with the gold layer of the metal bumps 12
is a tin-lead alloy, the interface bonding layer 250 is a
tin-lead-gold alloy having a thickness of between 0.2 and 10
micrometers or of between 0.4 and 5 micrometers. Next, the tool
head 610 is removed from the flexible circuit film 36. Next, the
semiconductor chip 2 bonded with the flexible circuit film 36 is
removed from the stage 600.
[0098] The metal bumps 12 bonded with the copper traces 210 of the
flexible circuit film 36 have a thickness of between 5 and 50
micrometers, and preferably of between 10 and 25 micrometers. For
example, the metal bumps 12 between the semiconductor chip 2 and
the interface bonding layer 250 may include a titanium-containing
layer on the pads 18 exposed by the openings 10a, and a gold layer
having a thickness of between 5 and 50 micrometers, and preferably
of between 10 and 25 micrometers, on the titanium-containing layer
and between the titanium-containing layer and the interface bonding
layer 250. Alternatively, the metal bumps 12 between the
semiconductor chip 2 and the interface bonding layer 250 may
include a titanium-containing layer on the pads 18 exposed by the
openings 10a, and a copper layer having a thickness of between 5
and 50 micrometers, and preferably of between 10 and 25
micrometers, on the titanium-containing layer and between the
titanium-containing layer and the interface bonding layer 250.
Alternatively, the metal bumps 12 between the semiconductor chip 2
and the interface bonding layer 250 may include a
titanium-containing layer on the pads 18 exposed by the openings
10a, a copper layer having a thickness of between 0.5 and 45
micrometers, and preferably of between 5 and 35 micrometers, on the
titanium-containing layer and between the titanium-containing layer
and the interface bonding layer 250, a nickel layer having a
thickness of between 0.5 and 5 micrometers, and preferably of
between 1 and 3 micrometers, on the copper layer and between the
copper layer and the interface bonding layer 250, and a gold layer
having a thickness of between 0.5 and 5 micrometers, and preferably
of between 1 and 3 micrometers, on the nickel layer and between the
nickel layer and the interface bonding layer 250. Alternatively,
the metal bumps 12 between the semiconductor chip 2 and the
interface bonding layer 250 may include a titanium-containing layer
on the pads 18 exposed by the openings 10a, a copper layer having a
thickness of between 0.5 and 45 micrometers, and preferably of
between 5 and 35 micrometers, on the titanium-containing layer and
between the titanium-containing layer and the interface bonding
layer 250, and a nickel layer having a thickness of between 0.5 and
5 micrometers, and preferably of between 1 and 3 micrometers, on
the copper layer and between the copper layer and the interface
bonding layer 250. Alternatively, the metal bumps 12 between the
semiconductor chip 2 and the interface bonding layer 250 may
include a titanium-containing layer on the pads 18 exposed by the
openings 10a, a copper layer having a thickness of between 0.5 and
45 micrometers, and preferably of between 5 and 35 micrometers, on
the titanium-containing layer and between the titanium-containing
layer and the interface bonding layer 250, and a gold layer having
a thickness of between 0.5 and 5 micrometers, and preferably of
between 1 and 3 micrometers, on the copper layer and between the
copper layer and the interface bonding layer 250. Alternatively,
the metal bumps 12 between the semiconductor chip 2 and the
interface bonding layer 250 may include a titanium-containing layer
on the pads 18 exposed by the openings 10a, a copper layer, formed
by a sputtering process, having a thickness of between 0.03 and 1
.mu.m, and preferably of between 0.1 and 0.5 .mu.m, on the
titanium-containing layer and between the titanium-containing layer
and the interface bonding layer 250, a nickel layer, formed by an
electroplating process, having a thickness of between 0.5 and 45
micrometers, and preferably of between 5 and 35 micrometers, on the
sputtered copper layer and between the sputtered copper layer and
the interface bonding layer 250, and a gold layer, formed by an
electroplating process, having a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
nickel layer and between the nickel layer and the interface bonding
layer 250. Alternatively, the metal bumps 12 between the
semiconductor chip 2 and the interface bonding layer 250 may
include a titanium-containing layer on the pads 18 exposed by the
openings 10a, a copper layer, formed by a sputtering process,
having a thickness of between 0.03 and 1 .mu.m, and preferably of
between 0.1 and 0.5 .mu.m, on the titanium-containing layer and
between the titanium-containing layer and the interface bonding
layer 250, and a nickel layer, formed by an electroplating process,
having a thickness of between 0.5 and 45 micrometers, and
preferably of between 5 and 35 micrometers, on the sputtered copper
layer and between the sputtered copper layer and the interface
bonding layer 250. The above-mentioned titanium-containing layer
can be a single titanium-tungsten-alloy layer having a thickness of
between 0.03 and 0.7 .mu.m, and preferably of between 0.15 and 0.4
.mu.m, a single titanium layer having a thickness of between 0.01
and 0.7 .mu.m, and preferably of between 0.01 and 0.15 .mu.m, a
single titanium-nitride layer having a thickness of between 0.01
and 0.1 .mu.m, and preferably of between 0.01 and 0.02 .mu.m, or a
composite layer comprising a titanium layer having a thickness of
between 0.01 and 0.15 .mu.m, and a titanium-tungsten-alloy layer,
having a thickness of between 0.1 and 0.35 .mu.m, on the titanium
layer.
[0099] In a second case, referring to FIG. 3B, the metal bumps 12
have the above-mentioned gold layer, at the tips of the metal bumps
12, capable of being used to be joined with a gold layer of the
wetting layer 240b using gang bonding, which process is described
as below. First, the semiconductor chip 2 is held by vacuum
adsorption on the stage 600 kept at a temperature of between 250
and 500.degree. C., and preferably of between 350 and 450.degree.
C. Next, the flexible circuit film 36 is thermally pressed on the
metal bumps 12 of the semiconductor chip 2 at a force of between 20
and 150N, and preferably of between 70 and 120N, for a time of
between 0.1 and 10 seconds, and preferably of between 0.5 and 3
seconds, by the tool head 610 kept at a temperature of between 150
and 450.degree. C., and preferably of between 250 and 400.degree.
C., optionally applying ultrasonic waves to the metal bumps 12 and
to the wetting layer 240b of the flexible circuit film 36, to join
the gold layer of the wetting layer 240b with the above-mentioned
gold layer of the metal bumps 12. Next, the tool head 610 is
removed from the flexible circuit film 36. Next, the semiconductor
chip 2 bonded with the flexible circuit film 36 is removed from the
stage 600.
[0100] Thereby, the pads 18 of the semiconductor chip 2 can be
connected to the copper traces 210 of the flexible circuit film 36
through gold joints formed by joining the gold layer of the wetting
layer 240b with the above-mentioned gold layer of the metal bumps
12. For example, the metal bumps 12 between the semiconductor chip
2 and the copper traces 210 may include a titanium-containing layer
on the pads 18 exposed by the openings 10a, and a gold joint having
a thickness of between 5 and 50 micrometers, and preferably of
between 10 and 25 micrometers on the titanium-containing layer and
between the titanium-containing layer and the copper traces 210.
Alternatively, the metal bumps 12 between the semiconductor chip 2
and the copper traces 210 may include a titanium-containing layer
on the pads 18 exposed by the openings 10a, a copper layer having a
thickness of between 0.5 and 45 micrometers, and preferably of
between 5 and 35 micrometers, on the titanium-containing layer and
between the titanium-containing layer and the copper traces 210, a
nickel layer having a thickness of between 0.5 and 5 micrometers,
and preferably of between 1 and 3 micrometers, on the copper layer
and between the copper layer and the copper traces 210, and a gold
joint having a thickness of between 0.5 and 5 micrometers, and
preferably of between 1 and 3 micrometers, on the nickel layer and
between the nickel layer and the copper traces 210. Alternatively,
the metal bumps 12 between the semiconductor chip 2 and the copper
traces 210 may include a titanium-containing layer on the pads 18
exposed by the openings 10a, a copper layer having a thickness of
between 0.5 and 45 micrometers, and preferably of between 5 and 35
.mu.m, on the titanium-containing layer and between the
titanium-containing layer and the copper traces 210, and a gold
joint having a thickness of between 0.5 and 5 micrometers, and
preferably of between 1 and 3 micrometers, on the copper layer and
between the copper layer and the copper traces 210. Alternatively,
the metal bumps 12 between the semiconductor chip 2 and the copper
traces 210 may include a titanium-containing layer on the pads 18
exposed by the openings 10a, a copper layer, formed by a sputtering
process, having a thickness of between 0.03 and 1 .mu.m, and
preferably of between 0.1 and 0.5 .mu.m, on the titanium-containing
layer and between the titanium-containing layer and the copper
traces 210, a nickel layer, formed by an electroplating process,
having a thickness of between 0.5 and 45 micrometers, and
preferably of between 5 and 35 micrometers, on the sputtered copper
layer and between the sputtered copper layer and the copper traces
210, and a gold joint having a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
nickel layer and between the nickel layer and the copper traces
210. The above-mentioned titanium-containing layer can be a single
titanium-tungsten-alloy layer having a thickness of between 0.03
and 0.7 .mu.m, and preferably of between 0.15 and 0.4 .mu.m, a
single titanium layer having a thickness of between 0.01 and 0.7
.mu.m, and preferably of between 0.01 and 0.15 .mu.m, a single
titanium-nitride layer having a thickness of between 0.01 and 0.1
.mu.m, and preferably of between 0.01 and 0.02 .mu.m, or a
composite layer comprising a titanium layer having a thickness of
between 0.01 and 0.15 .mu.m, and a titanium-tungsten-alloy layer,
having a thickness of between 0.1 and 0.35 .mu.m, on the titanium
layer.
[0101] In a first case, referring to FIG. 3C, the metal bumps 12
have the above-mentioned gold layer, at the tips of the metal bumps
12, capable of being used to be joined with the wetting layer 240b
of pure tin or an above-mentioned tin alloy using flip-chip
bonding, which process is described as below. First, the flexible
circuit film 36 is placed on a stage 600a kept at a temperature of
between 150 and 450.degree. C., and preferably of between 250 and
400.degree. C., and the semiconductor chip 2 is held by vacuum
adsorption on a tool head 610a kept at a temperature of between 250
and 500.degree. C., of between 350 and 450.degree. C. or of between
100 and 500.degree. C. Next, the semiconductor chip 2 is thermally
pressed on the wetting layer 240b of the flexible circuit film 36
at a force of between 20 and 150N, and preferably of between 50 and
90N, for a time of between 0.1 and 10 seconds, and preferably of
between 0.5 and 3 seconds, by the tool head 610a kept at a
temperature of between 250 and 500.degree. C., of between 350 and
450.degree. C. or of between 100 and 500.degree. C., optionally
applying ultrasonic waves to the metal bumps 12 and to the wetting
layer 240b of the flexible circuit film 36, to join the metal bumps
12 with the wetting layer 240b. Referring to FIGS. 3A and 3C, in
the step of joining the metal bumps 12 with the wetting layer 240b,
the interface bonding layer 250, such as a metal alloy, may be
formed between the metal bumps 12 and the copper traces 210. The
specification of the interface bonding layer 250 formed in the
process as illustrated in the first case shown in FIG. 3C can be
referred to as the specification of the interface bonding layer 250
formed in the process as illustrated in the first case shown in
FIGS. 3A and 3B. Next, the tool head 610a is removed from the
semiconductor chip 2. Next, the flexible circuit film 36 bonded
with the semiconductor chip 2 is removed from the stage 600a. The
specification of the metal bumps 12, between the semiconductor chip
2 and the interface bonding layer 250, formed in the process as
illustrated in the first case shown in FIG. 3C can be referred to
as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B.
[0102] In a second case, referring to FIG. 3C, the metal bumps 12
have the above-mentioned gold layer, at the tips of the metal bumps
12, capable of being used to be joined with a gold layer of the
wetting layer 240b using flip-chip bonding, which process is
described as below. First, the flexible circuit film 36 is placed
on the stage 600a kept at a temperature of between 150 and
450.degree. C., and preferably of between 250 and 400.degree. C.,
and the semiconductor chip 2 is held by vacuum adsorption on the
tool head 610a kept at a temperature of between 250 and 500.degree.
C., of between 350 and 450.degree. C. or of between 100 and
500.degree. C. Next, the semiconductor chip 2 is thermally pressed
on the wetting layer 240b of the flexible circuit film 36 at a
force of between 20 and 150N, and preferably of between 70 and
120N, for a time of between 0.1 and 10 seconds, and preferably of
between 0.5 and 3 seconds, by the tool head 610a kept at a
temperature of between 250 and 500.degree. C., of between 350 and
450.degree. C. or of between 100 and 500.degree. C., optionally
applying ultrasonic waves to the metal bumps 12 and to the wetting
layer 240b of the flexible circuit film 36, to join the
above-mentioned gold layer of the metal bumps 12 with the gold
layer of the wetting layer 240b. Next, the tool head 610a is
removed from the semiconductor chip 2. Next, the flexible circuit
film 36 bonded with the semiconductor chip 2 is removed from the
stage 600a. Thereby, the pads 18 of the semiconductor chip 2 can be
connected to the copper traces 210 of the flexible circuit film 36
through gold joints formed by joining the above-mentioned gold
layer of the metal bumps 12 with the gold layer of the wetting
layer 240b. The specification of the metal bumps 12, between the
semiconductor chip 2 and the flexible circuit film 36, formed in
the process as illustrated in the second case shown in FIG. 3C can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B.
[0103] Referring to FIG. 3D, a polymer layer 260 is filled into the
gap between the semiconductor chip 2 and the flexible circuit film
36, enclosing the metal bumps 12, by dispensing a polymer on the
flexible circuit film 36 close to the semiconductor chip 2, with
the polymer flowing into the gap between the semiconductor chip 2
and the flexible circuit film 36, and then curing the flowing
polymer at a temperature of between 100 and 250.degree. C. The
material of the polymer layer 260 may be expoxy, polyester,
polybenzoxazole or polyimide.
[0104] Referring to FIG. 3E, a substrate 300 comprises a circuit
structure in the substrate 300, an insulating layer 320, an
insulating layer 330, metal pads 310a and metal pads 310b. The
circuit structure comprises copper traces (including 340a and 340b)
each having a thickness between 5 and 30 micrometers. Openings 320a
in the insulating layer 320 expose the topmost copper traces 340a
and openings 330a in the insulating layer 330 expose the bottommost
copper traces 340b. The metal pads 310a are on the topmost copper
traces 340a exposed by the openings 320a, and the metal pads 310b
are on the bottommost copper traces 340b exposed by the openings
330a. The metal pads 310a are connected to the metal pads 310b
through the copper traces (comprising the copper traces 340a and
340b) in the substrate 300.
[0105] Each of the insulating layers 320 and 330 has a thickness of
between 5 and 40 micrometers, of between 5 and 10 micrometers or of
between 10 and 20 micrometers, and may comprise epoxy, polyester,
polybenzoxazole or polyimide. Each of the metal pads 310a and 310b
has a thickness of between 0.1 and 3 micrometers, and may be gold,
copper, silver, nickel, tin, palladium or a composite of the
above-mentioned materials. For example, the metal pads 310a can be
formed by electroless plating a nickel layer having a thickness of
between 0.05 and 1 .mu.m on the topmost copper traces 340a exposed
by the openings 320a, and electroless plating a gold layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 0.3 micrometers, on the nickel layer in the
openings 320a. Alternatively, the metal pads 310a can be formed by
electroless plating a nickel layer having a thickness of between
0.05 and 1 .mu.m on the topmost copper traces 340a exposed by the
openings 320a, and electroless plating a tin layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 0.3 micrometers, on the nickel layer in the
openings 320a. Alternatively, the metal pads 310a can be formed by
electroless plating a gold layer having a thickness of between 0.05
and 2 micrometers, and preferably of between 0.05 and 0.3
micrometers, on the topmost copper traces 340a exposed by the
openings 320a. For example, the metal pads 310b can be formed by
electroless plating a nickel layer having a thickness of between
0.05 and 1 .mu.m on the bottommost copper traces 340b exposed by
the openings 330a, and electroless plating a gold layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 0.3 micrometers, on the nickel layer in the
openings 330a. Alternatively, the metal pads 310b can be formed by
electroless plating a nickel layer having a thickness of between
0.05 and 1 .mu.m on the bottommost copper traces 340b exposed by
the openings 330a, and electroless plating a tin layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 0.3 micrometers, on the nickel layer in the
openings 330a. Alternatively, the metal pads 310b can be formed by
electroless plating a gold layer having a thickness of between 0.05
and 2 micrometers, and preferably of between 0.05 and 0.3
micrometers, on the bottommost copper traces 340b exposed by the
openings 330a.
[0106] In a case, the substrate 300 may comprise a core layer, such
as a glass fiber reinforced epoxy with a thickness of between 200
and 2,000 .mu.m, multiple copper circuit layers respectively over
and under the core layer, and multiple polymer layers between the
neighboring copper circuit layers. The copper circuit layers
provide the circuit structure in the substrate 300. The metal pads
310a and 310b are respectively on the copper traces 340a of the
topmost copper circuit layer and on the copper traces 340b of the
bottommost copper circuit layer.
[0107] In another case, the substrate 300 may comprise multiple
copper circuit layers and multiple ceramic layers between the
neighboring copper circuit layers. The copper circuit layers
provide the circuit structure in the substrate 300. The metal pads
310a and 310b are respectively on the copper traces 340a of the
topmost copper circuit layer and on the copper traces 340b of the
bottommost copper circuit layer.
[0108] The substrate 300 may be a ball grid array (BGA) substrate
with a thickness t15 of between 200 and 2,000 .mu.m. Alternatively,
the substrate 300 may be a glass fiber reinforced epoxy based
substrate with a thickness t15 of between 200 and 2,000 .mu.m.
Alternatively, the substrate 300 may be a silicon substrate with a
thickness t15 of between 200 and 2,000 .mu.m. Alternatively, the
substrate 300 may be a ceramic substrate with a thickness t15 of
between 200 and 2,000 .mu.m. Alternatively, the substrate 300 may
be an organic substrate with a thickness t15 of between 200 and
2,000 .mu.m.
[0109] Referring to FIG. 3F, metal joints 410a, such as
tin-containing joints, are formed on the metal pads 310a by screen
printing a solder paste containing flux and solder, such as pure
tin, a tin-silver alloy, a tin-silver-copper alloy or a tin-lead
alloy, on the metal pads 310a and then reflowing the solder paste.
The metal joints 410a may be formed of pure tin, a tin-silver
alloy, a tin-silver-copper alloy or a tin-lead alloy. Two methods
of bonding the flexible circuit film 36 with the substrate 300 are
described as follow.
[0110] In a first case, referring to FIGS. 3F and 3G, when the
metal joints 410a are tin-containing joints, the metal joints 410a
can be used to be joined with the wetting layer 240a of pure tin or
an above-mentioned tin alloy using a heat press process, which
method is described as below. First, the substrate 300 is placed on
a stage kept at a temperature of between 150 and 350.degree. C.,
and preferably of between 200 and 300.degree. C. Next, the flexible
circuit film 36 is thermally pressed on the metal joints 410a on
the metal pads 310a of the substrate 300 at a force of between 20
and 150N, and preferably of between 50 and 90N, for a time of
between 0.1 and 10 seconds, and preferably of between 0.5 and 3
seconds, by a tool head kept at a temperature of between 250 and
500.degree. C., and preferably of between 350 and 450.degree. C.,
to join the wetting layer 240a with the metal joints 410a. In the
step of joining the wetting layer 240a with the metal joints 410a,
metal joints 410b can be formed between the first contact points of
the copper traces 210 and the topmost copper traces 340a of the
substrate 300. The metal joints 410b can be tin-containing joints
having a thickness t16 of between 20 and 150 micrometers or of
between 15 and 50 micrometers, wherein the tin-containing joints
may include pure tin, a tin-silver alloy, a tin-silver-copper alloy
or a tin-lead alloy. The tin-containing joints may include a
tin-gold alloy, a tin-silver-gold alloy, a tin-silver-gold-copper
alloy or a tin-lead-gold alloy at the bottom side of the
tin-containing joints due to the reaction between tin in the metal
joints 410a and gold at the top of the metal pads 310a. Next, the
tool head is removed from the flexible circuit film 36. Next, the
substrate 300 bonded with the flexible circuit film 36 is removed
from the stage.
[0111] In a second case, referring to FIGS. 3F and 3G, when the
metal joints 410a are tin-containing joints, the metal joints 410a
can be used to be joined with a gold layer of the wetting layer
240a using a heat press process, which method is described as
below. First, the substrate 300 is placed on a stage kept at a
temperature of between 150 and 350.degree. C., and preferably of
between 200 and 300.degree. C. Next, the flexible circuit film 36
is thermally pressed on the metal joints 410a on the metal pads
310a of the substrate 300 at a force of between 20 and 150N, and
preferably of between 50 and 90N, for a time of between 0.1 and 10
seconds, and preferably of between 0.5 and 3 seconds, by a tool
head kept at a temperature of between 250 and 500.degree. C., and
preferably of between 350 and 450.degree. C., to join the wetting
layer 240a with the metal joints 410a. In the step of joining the
wetting layer 240a with the metal joints 410a, the metal joints
410b can be formed between the first contact points of the copper
traces 210 and the topmost copper traces 340a of the substrate 300.
The metal joints 410b can be tin-containing joints having a
thickness t16 of between 20 and 150 micrometers or of between 15
and 50 micrometers. The tin-containing joints may include a
tin-silver-gold-copper alloy, a tin-silver-gold alloy or a tin-gold
alloy at the top side of the tin-containing joints due to the
reaction between tin in the metal joints 410a and gold at the top
of the wetting layer 240a. The tin-containing joints may include a
tin-gold alloy, a tin-silver-gold alloy or a tin-silver-gold-copper
alloy at the bottom side of the tin-containing joints due to the
reaction between tin in the metal joints 410a and gold at the top
of the metal pads 310a. Next, the tool head is removed from the
flexible circuit film 36. Next, the substrate 300 bonded with the
flexible circuit film 36 is removed from the stage.
[0112] Referring to FIG. 3H, after the flexible circuit film 36 is
bonded with the substrate 300, a polymer layer 350 can be filled
into the gap between the flexible circuit film 36 and the substrate
300, enclosing the metal joints 410b, by dispensing a polymer on
the substrate 300 close to the flexible circuit film 36, with the
polymer flowing into the gap between the flexible circuit film 36
and the substrate 300, and then curing the flowing polymer at a
temperature of between 100 and 250.degree. C. The material of the
polymer layer 350 may be expoxy, polyester or polyimide, and the
polymer layer 350 has a thickness t17 of between 1 and 30
micrometers.
[0113] Referring to FIG. 3I, a polymer compound 360 is formed on
the semiconductor chip 2, on the flexible circuit film 36 and on a
peripheral region of the substrate 300 by molding an epoxy-based
polymer with carbon fillers therein on the semiconductor chip 2, on
the flexible circuit film 36 and on the peripheral region of the
substrate 300 at a temperature of between 130 and 250.degree. C.
Alternatively, the polymer compound 360 can be polyimide,
polybenzoxazole (PBO) or polyester. Preferably, the polymer
compound 360 has a value of Young's modulus less than 0.5 GPa.
[0114] Referring to FIGS. 3J and 3K, solder balls 501 shown in FIG.
3J may be being placed, in a ball-grid-array arrangement, on a flux
or solder paste 505 preformed on the metal pads 310b of the
substrate 300 using a ball placement process to form solder balls
502 shown in FIG. 3K on the substrate 300. The solder balls 502 can
be formed by printing the flux or solder paste 505 on the metal
pads 310b, next placing the solder balls 501, such as pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
having a diameter of between 0.25 and 1.2 millimeters on the flux
or solder paste 505, next reflowing the solder balls 501 at a peak
temperature of between 230 and 270.degree. C., and then cleaning
the remaining flux from the substrate 300. The solder balls 502
have a diameter of between 0.2 and 1.2 millimeters, and the solder
balls 502 may include pure tin, a tin-silver alloy, a
tin-silver-copper alloy or a tin-lead alloy.
[0115] For example, during the step of reflowing the solder balls
501, when the metal pads 310b have a bottommost metal layer of
gold, the gold layer of the metal pads 310b is solved in the solder
balls 502. Preferably, the metal pads 310b have a nickel layer
between the gold layer and the copper traces 340b. The nickel layer
serves as a barrier layer preventing copper in the copper traces
340b from being solved in the solder balls 502 after the solder
balls 502 are formed on the substrate 300. In the case of gold
serving as a bottommost metal layer of the metal pads 310b, the
solder balls 502, after being joined with the substrate 300, may
include a portion, of a tin-silver-gold-copper alloy, a
tin-silver-gold alloy, a tin-gold alloy or a tin-lead-gold alloy,
on the nickel layer of the metal pads 310b and under the copper
traces 340b of the substrate 300 due to the reaction between gold
in the metal pads 310b and tin in the solder balls 501 during
reflowing the solder balls 501.
[0116] After the solder balls 502 are formed on the substrate 300,
the substrate 300 and the polymer compound 360 can be optionally
cut into multiple units.
[0117] FIG. 3L is a perspective view showing FIG. 3K. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 36 by bonding the semiconductor chip 2 with the flexible
circuit film 36. The flexible circuit film 36 is also bonded with
the substrate 300 to connect the fine-pitched metal bumps 12 of the
semiconductor chip 2 with the circuit structure of the substrate
300. Thereby, the semiconductor chip 2 has the fine-pitched metal
bumps 12 connected to an external circuit, such as a printed
circuit board (PCB) comprising a glass fiber as a core, through the
copper traces 210 of the flexible circuit film 36 and the circuit
structure of the substrate 300.
[0118] Alternatively, referring to FIGS. 3M and 3N, the step of
forming the polymer compound 360, as shown in FIG. 3I, can be
omitted, that is, the semiconductor chip 2 and the flexible circuit
film 36 are uncovered by any polymer compound. Alternatively,
referring to FIG. 30, the step of forming the polymer layer 350, as
shown in FIG. 3H, can be omitted. Alternatively, referring to FIG.
3P, the steps of forming the polymer layer 350, as shown in FIG.
3H, and of forming the polymer compound 360, as shown in FIG. 3I,
can be omitted, that is, the semiconductor chip 2 and the flexible
circuit film 36 are uncovered by any polymer compound.
[0119] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 3I. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0120] Alternatively, the polymer compound 360 and the solder balls
502 can be omitted, as shown in FIG. 3H. The semiconductor chip 2
and the flexible circuit film 36 are uncovered by any polymer
compound. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0121] Alternatively, the polymer layer 350 and the solder balls
502 can be omitted, as shown in FIG. 3Q. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0122] Alternatively, the polymer layer 350, the polymer compound
360 and the solder balls 502 can be omitted, as shown in FIG. 3G.
The semiconductor chip 2 and the flexible circuit film 36 are
uncovered by any polymer compound. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0123] FIG. 3R is a schematically cross-sectional figure showing a
chip package including the semiconductor chip 2 joined with a
flexible circuit substrate 38 using a tape-automated-bonding (TAB)
technology. The above-mentioned flexible circuit film 36 can be
replaced by the flexible circuit film 38. The flexible circuit film
38 includes the polymer layer 200, the polymer layer 220, the
wetting layer 240a, the wetting layer 240b and the copper traces
210 between the polymer layers 200 and 220, wherein the openings
200a in the polymer layer 200 expose contact points of the copper
traces 210, and the polymer layers 200 and 220 uncover top and
bottom sides of the copper traces 210 at the center portion of the
flexible circuit film 38. The wetting layer 240a is on the contact
points of the copper traces 210 exposed by the openings 200a in the
polymer layer 200, and the wetting layer 240b is on the copper
traces 210 at the center portion of the flexible circuit film 38.
The specification of the polymer layer 200, the polymer layer 220
and the copper traces 210 shown in FIG. 3R can be referred to as
the specification of the polymer layer 200, the polymer layer 220
and the copper traces 210 illustrated in FIG. 3A. The specification
of the wetting layer 240a shown in FIG. 3R can be referred to as
the specification of the wetting layer 240a illustrated in FIGS. 3B
and 3C. Alternatively, the copper traces 210 can be replaced by
gold traces having a thickness of between 3 and 30 .mu.m, of
between 5 and 20 micrometers or of between 4 and 10 micrometers.
Alternatively, the copper traces 210 can be replaced by silver
traces having a thickness of between 3 and 30 .mu.m, of between 5
and 20 micrometers or of between 4 and 10 micrometers.
[0124] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210 at the center portion of the flexible
circuit film 38 through the interface bonding layer 250. A method
for bonding the metal bumps 12 of the semiconductor chip 2 with the
copper traces 210 at the center portion of the flexible circuit
film 38 is described as shown in FIG. 3S.
[0125] Referring to FIG. 3S, the flexible circuit film 38 can be
connected to the semiconductor chip 2. The flexible circuit film 38
has the wetting layer 240a to be joined with the substrate 300
shown in FIG. 3E, and the wetting layer 240b to be joined with the
metal bumps 12 on the semiconductor chip 2. The wetting layer 240b
is formed on the top and bottom sides of the copper traces 210,
uncovered by the polymer layers 200 and 220, at the center portion
of the flexible circuit film 38, and the wetting layer 240b having
a thickness of between 0.05 and 2 micrometers, and preferably of
between 0.1 and 1 micrometer, may be gold, copper, nickel, silver,
palladium, tin or a composite of the above-mentioned materials. For
example, the wetting layer 240b may be a tin-containing layer, such
as pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, having a thickness of between 0.05 and 2
micrometers, and preferably of between 0.1 and 1 micrometer, on the
top and bottom sides of the copper traces 210, uncovered by the
polymer layers 200 and 220, at the center portion of the flexible
circuit film 38. Alternatively, the wetting layer 240b may be a
gold layer having a thickness of between 0.05 and 2 micrometers,
and preferably of between 0.1 and 1 micrometer, on the top and
bottom sides of the copper traces 210, uncovered by the polymer
layers 200 and 220, at the center portion of the flexible circuit
film 38.
[0126] In a first case, referring to FIG. 3S, the metal bumps 12
have the above-mentioned gold layer, at the tips of the metal bumps
12, capable of being used to be joined with the wetting layer 240b
of pure tin or an above-mentioned tin alloy, which method is
described as below. First, the semiconductor chip 2 is held by
vacuum adsorption on a stage 600b kept at a temperature of between
250 and 500.degree. C., and preferably of between 350 and
450.degree. C. Next, the flexible circuit film 38 is thermally
pressed on the metal bumps 12 of the semiconductor chip 2 at a
force of between 20 and 150N, and preferably of between 50 and 90N,
for a time of between 0.1 and 10 seconds, and preferably of between
0.5 and 3 seconds, by a tool head 610b kept at a temperature of
between 150 and 450.degree. C., and preferably of between 250 and
400.degree. C., optionally applying ultrasonic waves to the metal
bumps 12 and to the wetting layer 240b of the flexible circuit film
38, to join the wetting layer 240b with the metal bumps 12.
Referring to FIGS. 3R and 3S, in the step of joining the wetting
layer 240b with the metal bumps 12, the interface bonding layer
250, such as a metal alloy, may be formed between the metal bumps
12 and the copper traces 210. The interface bonding layer 250 has a
thickness t12 of between 0.2 and 10 micrometers, and preferably of
between 0.4 and 5 micrometers. When the wetting layer 240b before
bonded with the gold layer of the metal bumps 12 is pure tin, the
interface bonding layer 250 is a tin-gold alloy having a thickness
of between 0.2 and 10 micrometers or of between 0.4 and 5
micrometers, wherein an atomic ratio of tin to gold in the tin-gold
alloy is between 0.2 and 0.3. When the wetting layer 240b before
bonded with the gold layer of the metal bumps 12 is a tin-silver
alloy, the interface bonding layer 250 is a tin-silver-gold alloy
having a thickness of between 0.2 and 10 micrometers or of between
0.4 and 5 micrometers. When the wetting layer 240b before bonded
with the gold layer of the metal bumps 12 is a tin-silver-copper
alloy, the interface bonding layer 250 is a tin-silver-gold-copper
alloy having a thickness of between 0.2 and 10 micrometers or of
between 0.4 and 5 micrometers. Next, the tool head 610b is removed
from the flexible circuit film 38. Next, the semiconductor chip 2
bonded with the flexible circuit film 38 is removed from the stage
600b. The metal bumps 12 bonded with the copper traces 210 of the
flexible circuit film 38 have a thickness of between 5 and 50
micrometers, and preferably of between 10 and 25 micrometers, and
the specification of the metal bumps 12, between the semiconductor
chip 2 and the interface bonding layer 250, formed in the process
as illustrated in the first case shown in FIGS. 3R and 3S can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B.
[0127] In a second case, referring to FIG. 3S, the metal bumps 12
have the above-mentioned gold layer, at the tips of the metal bumps
12, capable of being used to be joined with a gold layer of the
wetting layer 240b, which method is described as below. First, the
semiconductor chip 2 is held by vacuum adsorption on the stage 600b
kept at a temperature of between 250 and 500.degree. C., and
preferably of between 350 and 450.degree. C. Next, the flexible
circuit film 38 is thermally pressed on the metal bumps 12 of the
semiconductor chip 2 at a force of between 20 and 150N, and
preferably of between 70 and 120N, for a time of between 0.1 and 10
seconds, and preferably of between 0.5 and 3 seconds, by the tool
head 610b kept at a temperature of between 150 and 450.degree. C.,
and preferably of between 250 and 400.degree. C., optionally
applying ultrasonic waves to the metal bumps 12 and to the wetting
layer 240b of the flexible circuit film 38, to join the gold layer
of the wetting layer 240b with the above-mentioned gold layer of
the metal bumps 12. Next, the tool head 610b is removed from the
flexible circuit film 38. Next, the semiconductor chip 2 bonded
with the flexible circuit film 38 is removed from the stage 600b.
Thereby, the pads 18 of the semiconductor chip 2 can be connected
to the copper traces 210 of the flexible circuit film 38 through
gold joints formed by joining the gold layer of the wetting layer
240b with the above-mentioned gold layer of the metal bumps 12. The
metal bumps 12 bonded with the copper traces 210 of the flexible
circuit film 38 have a thickness of between 5 and 50 micrometers,
and preferably of between 10 and 25 micrometers. The specification
of the metal bumps 12, between the semiconductor chip 2 and the
copper traces 210, formed in the process as illustrated in the
second case shown in FIG. 3S can be referred to as the
specification of the metal bumps 12, between the semiconductor chip
2 and the copper traces 210, formed in the process as illustrated
in the second case shown in FIG. 3B.
[0128] Referring to FIG. 3T, the polymer layer 260 can be formed by
dispensing a polymer on the semiconductor chip 2 with the polymer
enclosing the metal bumps 12 and the copper traces 210 at the
center portion of the flexible circuit film 38, and then curing the
polymer at a temperature of between 100 and 250.degree. C. The
material of the polymer layer 260 may be expoxy, polyester or
polyimide.
[0129] The metal joints 410a, such as tin-containing joints, are
formed on the metal pads 310a of the substrate 300 shown in FIG. 3E
by screen printing a solder paste containing flux and solder, such
as pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy, on the metal pads 310a and then reflowing the
solder paste. The metal joints 410a may be formed of pure tin, a
tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy.
The specification of the substrate 300 shown in FIG. 3T can be
referred to as the specification of the substrate 300 illustrated
in FIG. 3E. Two methods of bonding the flexible circuit film 38
with the substrate 300 are described as follow.
[0130] In a first case, referring to FIGS. 3T and 3U, when the
metal joints 410a are tin-containing joints, the metal joints 410a
can be used to be joined with the wetting layer 240a of pure tin or
an above-mentioned tin alloy using a heat press process, which
method which process is described as below. First, the substrate
300 is placed on a stage kept at a temperature of between 150 and
350.degree. C., and preferably of between 200 and 300.degree. C.
Next, the flexible circuit film 38 is thermally pressed on the
metal joints 410a on the metal pads 310a of the substrate 300 at a
force of between 20 and 150N, and preferably of between 50 and 90N,
for a time of between 0.1 and 10 seconds, and preferably of between
0.5 and 3 seconds, by a tool head kept at a temperature of between
250 and 500.degree. C., and preferably of between 350 and
450.degree. C., to join the wetting layer 240a with the metal
joints 410a. In the step of joining the wetting layer 240a with the
metal joints 410a, the metal joints 410b can be formed between the
contact points of the copper traces 210 and the topmost copper
traces 340a of the substrate 300. Next, the tool head is removed
from the flexible circuit film 38. Next, the substrate 300 bonded
with the flexible circuit film 38 is removed from the stage. The
specification of the metal joints 410b, between the contact points
of the copper traces 210 and the topmost copper traces 340a of the
substrate 300, formed in the process as illustrated in the first
case shown in FIGS. 3T and 3U can be referred to as the
specification of the metal joints 410b, between the first contact
points of the copper traces 210 and the topmost copper traces 340a
of the substrate 300, formed in the process as illustrated in the
first case shown in FIGS. 3F and 3G.
[0131] In a second case, referring to FIGS. 3T and 3U, when the
metal joints 410a are tin-containing joints, the metal joints 410a
can be used to be joined with a gold layer of the wetting layer
240a using a heat press process, which method is described as
below. First, the substrate 300 is placed on a stage kept at a
temperature of between 150 and 350.degree. C., and preferably of
between 200 and 300.degree. C. Next, the flexible circuit film 38
is thermally pressed on the metal joints 410a on the metal pads
310a of the substrate 300 at a force of between 20 and 150N, and
preferably of between 50 and 90N, for a time of between 0.1 and 10
seconds, and preferably of between 0.5 and 3 seconds, by a tool
head kept at a temperature of between 250 and 500.degree. C., and
preferably of between 350 and 450.degree. C., to join the wetting
layer 240a with the metal joints 410a. In the step of joining the
wetting layer 240a with the metal joints 410a, the metal joints
410b can be formed between the contact points of the copper traces
210 and the topmost copper traces 340a of the substrate 300. Next,
the tool head is removed from the flexible circuit film 38. Next,
the substrate 300 is removed from the stage. The specification of
the metal joints 410b, between the contact points of the copper
traces 210 and the topmost copper traces 340a of the substrate 300,
formed in the process as illustrated in the second case shown in
FIGS. 3T and 3U can be referred to as the specification of the
metal joints 410b, between the first contact points of the copper
traces 210 and the topmost copper traces 340a of the substrate 300,
formed in the process as illustrated in the second case shown in
FIGS. 3F and 3G.
[0132] Referring to FIG. 3V, after the flexible circuit film 38 is
bonded with the substrate 300, the polymer layer 350 can be
optionally filled into the gap between the flexible circuit film 38
and the substrate 300, enclosing the metal joints 410b, by
dispensing a polymer on the substrate 300 close to the flexible
circuit film 38, with the polymer flowing into the gap between the
flexible circuit film 38 and the substrate 300, and then curing the
flowing polymer at a temperature of between 100 and 250.degree. C.
The material of the polymer layer 350 may be expoxy, polyester or
polyimide, and the polymer layer 350 has a thickness t17 of between
1 and 30 micrometers.
[0133] Referring to FIG. 3W, the polymer compound 360 can be
optionally formed on the semiconductor chip 2, on the flexible
circuit film 38 and on the substrate 300 by molding an epoxy-based
polymer with carbon fillers therein on the semiconductor chip 2, on
the flexible circuit film 38 and the peripheral region of the
substrate 300 at a temperature of between 130 and 250.degree. C.
Alternatively, the polymer compound 360 can be polyimide or
polyester. Preferably, the polymer compound 360 has a value of
Young's modulus less than 0.5 GPa.
[0134] Referring to FIG. 3X, after the polymer compound 360 is
formed, the solder balls 502 may be formed, in a ball-grid-array
arrangement, on the metal pads 310b of the substrate 300 using a
ball placement process. The process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as shown in FIG.
3X can be referred to as the process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as illustrated in
FIGS. 3J and 3K. The specification of the solder balls 502 shown in
FIG. 3X can be referred to as the specification of the solder balls
502 illustrated in FIGS. 3J and 3K. Optionally, the substrate 300
can be sawed after the solder balls 502 are formed on the metal
pads 310b of the substrate 300.
[0135] Thereby, the fine-pitched metal bumps 12 of the
semiconductor chip 2 can be fanned out through the copper traces
210 of the flexible circuit film 38 by bonding the semiconductor
chip 2 with the flexible circuit film 38. The flexible circuit film
38 is also bonded with the substrate 300 to connect the
fine-pitched metal bumps 12 of the semiconductor chip 2 with the
circuit structure of the substrate 300. The semiconductor chip 2
has the fine-pitched metal bumps 12 connected to an external
circuit, such as a printed circuit board (PCB) comprising a glass
fiber as a core, through the copper traces 210 of the flexible
circuit film 38 and the circuit structure of the substrate 300.
[0136] Alternatively, the step of forming the polymer compound 360,
as shown in FIG. 3W, can be omitted, that is, the semiconductor
chip 2 and the flexible circuit film 38 are uncovered by any
polymer compound. Alternatively, the step of forming the polymer
layer 350, as shown in FIG. 3V, can be omitted. Alternatively, the
steps of forming the polymer layer 350, as shown in FIG. 3V, and of
forming the polymer compound 360, as shown in FIG. 3W, can be
omitted, that is, the semiconductor chip 2 and the flexible circuit
film 38 are uncovered by any polymer compound.
[0137] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 3W. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0138] Alternatively, the polymer compound 360 and the solder balls
502 can be omitted, as shown in FIG. 3V. The semiconductor chip 2
and the flexible circuit film 38 are uncovered by any polymer
compound. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0139] Alternatively, the polymer layer 350 and the solder balls
502 can be omitted, as shown in FIG. 3Y. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0140] Alternatively, the polymer layer 350, the polymer compound
360 and the solder balls 502 can be omitted, as shown in FIG. 3U.
The semiconductor chip 2 and the flexible circuit film 38 are
uncovered by any polymer compound. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
Embodiment 2
[0141] Referring to FIG. 4A, after the step shown in FIG. 3D, a
polymer compound 360 is formed on the semiconductor chip 2 and on
the flexible circuit film 36 by molding an epoxy-based polymer with
carbon fillers therein on the semiconductor chip 2 and on the
flexible circuit film 36 at a temperature of between 130 and
250.degree. C. Alternatively, the polymer compound 360 can be
polyimide or polyester. Preferably, the polymer compound 360 has a
value of Young's modulus less than 0.5 GPa.
[0142] Referring to FIGS. 4B and 4C, after the polymer compound 360
is formed, solder balls 501 shown in FIG. 4B are placed, in a
ball-grid-array arrangement, on a flux or solder paste 505
preformed on the wetting layer 240a of the flexible circuit film 36
using a ball placement process to form solder balls 502 shown in
FIG. 4C on the flexible circuit film 36. The solder balls 502 can
be formed by printing the flux or solder paste 505 on the wetting
layer 240a, next placing the solder balls 501, such as pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
having a diameter of between 0.25 and 1.2 millimeters on the flux
or solder paste 505, next reflowing the solder balls 501 at a peak
temperature of between 230 and 270.degree. C., and then cleaning
the remaining flux from the flexible circuit film 36. The solder
balls 502 have a diameter of between 0.2 and 1.2 millimeters, and
the solder balls 502 may include pure tin, a tin-silver alloy, a
tin-silver-copper alloy or a tin-lead alloy.
[0143] For example, during the step of reflowing the solder balls
501, when the wetting layer 240a is a tin-containing layer, such as
pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy, the tin-containing layer is solved in the solder
balls 502.
[0144] Alternatively, during the step of reflowing the solder balls
501, when the wetting layer 240a is a gold layer, the gold layer is
solved in the solder balls 502. The solder balls 502, after being
joined with the flexible circuit film 36, include a portion, of a
tin-silver-gold-copper alloy, a tin-silver-gold alloy, a tin-gold
alloy or a tin-lead-gold alloy, on the copper traces 210 of the
flexible circuit film 36 due to the reaction between gold in the
wetting layer 240a and tin in the solder balls 501 during reflowing
the solder balls 501.
[0145] After the solder balls 502 are formed on the flexible
circuit film 36, the flexible circuit film 36 and the polymer
compound 360 can be cut into multiple units.
[0146] FIG. 4D is a perspective view showing FIG. 4C. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 36 by bonding the semiconductor chip 2 with the flexible
circuit film 36. Thereby, the semiconductor chip 2 has the
fine-pitched metal bumps 12 connected to an external circuit, such
as a printed circuit board (PCB) comprising a glass fiber as a
core, through the copper traces 210 of the flexible circuit film 36
and the solder balls 502.
[0147] FIG. 5A is a schematically cross-sectional figure showing a
chip-on-film package. The above-mentioned flexible circuit film 36
can be replaced by a flexible circuit film 40. The flexible circuit
film 40 includes the polymer layer 200, the polymer layer 220, the
wetting layer 240b, metal pads 245 and the copper traces 210
between the polymer layers 200 and 220. The metal pads 245 are
formed on first contact points of the copper traces 210 exposed by
openings in the polymer layer 200, and the openings are filled up
with the metal pads 245. The wetting layer 240b are formed on
second contact points of the copper traces 210 exposed by the
openings 220a in the polymer layer 220. The specification of the
polymer layer 200, the polymer layer 220 and the copper traces 210
shown in FIG. 5A can be referred to as the specification of the
polymer layer 200, the polymer layer 220 and the copper traces 210
illustrated in FIG. 3A. The specification of the wetting layer 240b
shown in FIG. 5A can be referred to as the specification of the
wetting layer 240b illustrated in FIGS. 3B and 3C. The
specification of the interface bonding layer 250 shown in FIG. 5A
can be referred to as the specification of the interface bonding
layer 250 formed in the process as illustrated in the first case
shown in FIGS. 3A and 3B. Alternatively, the copper traces 210 can
be replaced by gold traces having a thickness of between 3 and 30
.mu.m, of between 5 and 20 micrometers or of between 4 and 10
micrometers. Alternatively, the copper traces 210 can be replaced
by silver traces having a thickness of between 3 and 30 .mu.m, of
between 5 and 20 micrometers or of between 4 and 10
micrometers.
[0148] The material of the metal pads 245 may be gold, copper,
nickel, silver, tin, palladium or a composite of the
above-mentioned materials, and the metal pads 245 have a thickness
t18 of between 4 and 10 micrometers, of between 15 and 30
micrometers or of between 10 and 100 micrometers. In a case, the
metal pads 245 may be formed by electroplating or electroless
plating a gold layer with a thickness of between 4 and 10
micrometers, of between 15 and 30 micrometers or of between 10 and
100 micrometers on the first contact points of the copper traces
210 exposed by the openings in the polymer layer 200, and the
openings in the polymer layer 200 are filled up with the gold
layer. In another case, the metal pads 245 may be formed by
electroplating or electroless plating a tin-containing layer, such
as pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy, with a thickness of between 4 and 10 micrometers,
of between 15 and 30 micrometers or of between 10 and 100
micrometers on the first contact points of the copper traces 210
exposed by the openings in the polymer layer 200, and the openings
are filled up with the tin-containing layer. In another case, the
metal pads 245 may be formed by electroplating or electroless
plating a copper layer with a thickness of between 4 and 10
micrometers, of between 15 and 30 micrometers or of between 10 and
100 micrometers on the first contact points of the copper traces
210 exposed by the openings in the polymer layer 200, and the
openings are filled up with the copper layer. In another case, the
metal pads 245 may be formed by electroplating a nickel layer with
a thickness of between 0.5 and 5 micrometers, and preferably of
between 1 and 3 micrometers, on the first contact points of the
copper traces 210 exposed by the openings in the polymer layer 200,
and then electroplating a gold layer with a thickness of between
0.05 and 2 micrometers, and preferably of between 0.05 and 0.5
micrometers, on the nickel layer in the openings in the polymer
layer 200, wherein the openings in the polymer layer 200 are filled
up with the nickel layer and the gold layer. In another case, the
metal pads 245 may be formed by electroless plating a nickel layer
with a thickness of between 0.5 and 5 micrometers, and preferably
of between 1 and 3 micrometers, on the first contact points of the
copper traces 210 exposed by the openings in the polymer layer 200,
and then electroless plating a gold layer with a thickness of
between 0.05 and 2 micrometers, and preferably of between 0.05 and
0.5 micrometers, on the nickel layer in the openings in the polymer
layer 200, wherein the openings in the polymer layer 200 are filled
up with the nickel layer and the gold layer. In another case, the
metal pads 245 may be formed by electroplating a nickel layer with
a thickness of between 0.5 and 5 micrometers, and preferably of
between 1 and 3 micrometers, on the first contact points of the
copper traces 210 exposed by the openings in the polymer layer 200,
and then electroplating a tin-containing layer, such as pure tin, a
tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy,
with a thickness of between 0.05 and 2 micrometers, and preferably
of between 0.05 and 0.5 micrometers, on the nickel layer in the
openings in the polymer layer 200, wherein the openings in the
polymer layer 200 are filled up with the nickel layer and the
tin-containing layer. In another case, the metal pads 245 may be
formed by electroless plating a nickel layer with a thickness of
between 0.5 and 5 micrometers, and preferably of between 1 and 3
micrometers, on the first contact points of the copper traces 210
exposed by the openings in the polymer layer 200, and then
electroless plating a tin-containing layer, such as pure tin, a
tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy,
with a thickness of between 0.05 and 2 micrometers, and preferably
of between 0.05 and 0.5 micrometers, on the nickel layer in the
openings in the polymer layer 200, wherein the openings in the
polymer layer 200 are filled up with the nickel layer and the
tin-containing layer.
[0149] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210, exposed by the openings 220a, of the
flexible circuit film 40 through the interface bonding layer 250.
The methods, of bonding the metal bumps 12 of the semiconductor
chip 2 with the copper traces 210 of the flexible circuit film 40,
as shown in FIG. 5A can be referred to as the methods, of bonding
the metal bumps 12 of the semiconductor chip 2 with the copper
traces 210 of the flexible circuit film 36, as illustrated in the
first and second cases shown in FIGS. 3B and 3C. When the step of
bonding a gold layer of the metal bumps 12 with the wetting layer
240b of a tin-containing layer is performed, the specification of
the metal bumps 12 between the semiconductor chip 2 and the
interface bonding layer 250 shown in FIG. 5A can be referred to as
the specification of the metal bumps 12, between the semiconductor
chip 2 and the interface bonding layer 250, formed in the process
as illustrated in the first case shown in FIGS. 3A and 3B.
Alternatively, when the step of bonding a gold layer of the metal
bumps 12 with the wetting layer 240b of a gold layer is performed,
the specification of the metal bumps 12 between the semiconductor
chip 2 and the copper traces 210 shown in FIG. 5A can be referred
to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B.
[0150] Referring to FIG. 5B, after the semiconductor chip 2 is
bonded with the flexible circuit film 40, the polymer layer 260 is
filled into the gap between the semiconductor chip 2 and the
flexible circuit film 40, enclosing the metal bumps 12, by
dispensing a polymer on the flexible circuit film 40 close to the
semiconductor chip 2, with the polymer flowing into the gap between
the semiconductor chip 2 and the flexible circuit film 40, and then
curing the flowing polymer at a temperature of between 100 and
250.degree. C. The material of the polymer layer 260 may be expoxy,
polyester, polybenzoxazole or polyimide.
[0151] Referring to FIG. 5C, after the polymer layer 260 is formed,
the polymer compound 360 is formed on the semiconductor chip 2 and
on the flexible circuit film 40 by molding an epoxy-based polymer
with carbon fillers therein on the semiconductor chip 2 and on the
flexible circuit film 40 at a temperature of between 130 and
250.degree. C. Alternatively, the polymer compound 360 can be
polyimide or polyester. Preferably, the polymer compound 360 has a
value of Young's modulus less than 0.5 GPa.
[0152] Referring to FIGS. 5D and 5E, after the polymer compound 360
is formed, the solder balls 501 shown in FIG. 5D are placed, in a
ball-grid-array arrangement, on the flux or solder paste 505
preformed on the metal pads 245 of the flexible circuit film 40
using a ball placement process to form the solder balls 502 shown
in FIG. 5E on the flexible circuit film 40. The solder balls 502
can be formed by printing the flux or solder paste 505 on the metal
pads 245, next placing the solder balls 501, such as pure tin, a
tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy,
having a diameter of between 0.25 and 1.2 millimeters on the flux
or solder paste 505, next reflowing the solder balls 501 at a peak
temperature of between 230 and 270.degree. C., and then cleaning
the remaining flux from the flexible circuit film 40. The solder
balls 502 have a diameter of between 0.2 and 1.2 millimeters, and
the solder balls 502 may include pure tin, a tin-silver alloy, a
tin-silver-copper alloy or a tin-lead alloy.
[0153] For example, during the step of reflowing the solder balls
501, when the metal pads 245 have a bottommost metal layer of gold,
the gold layer of the metal pads 245 is solved in the solder balls
502. Preferably, the metal pads 245 have a nickel layer between the
gold layer and the copper traces 210. The nickel layer serves as a
barrier layer preventing copper in the copper traces 210 from being
solved in the solder balls 502 after the solder balls 502 are
formed on the flexible circuit film 40. In the case of gold serving
as a bottommost metal layer of the metal pads 245, the solder balls
502, after being joined with the flexible circuit film 40, may
include a portion, of a tin-gold alloy, a tin-silver-gold-copper
alloy, a tin-silver-gold alloy or a tin-lead-gold alloy, on the
nickel layer of the metal pads 245 and under the first contact
points of the copper traces 210 due to the reaction between gold in
the metal pads 245 and tin in the solder balls 501 during reflowing
the solder balls 501.
[0154] Alternatively, during the step of reflowing the solder balls
501, when the metal pads 245 have a bottommost metal layer of
copper, all or a part of the copper layer of the metal pads 245 may
be solved in the solder balls 502. In the case of copper serving as
a bottommost metal layer of the metal pads 245, the solder balls
502, after being joined with the flexible circuit film 40, may
include a portion, of a tin-silver-copper alloy, a tin-lead-copper
alloy or a tin-copper alloy, under the first contact points of the
copper traces 210 due to the reaction between copper in the metal
pads 245 and tin in the solder balls 501 during reflowing the
solder balls 501.
[0155] After the solder balls 502 are formed on the flexible
circuit film 40, the flexible circuit film 40 and the polymer
compound 360 can be cut into multiple units.
[0156] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 5C. The flexible circuit film 40 is sawed into multiple
units. After sawing the flexible circuit film 40, the metal pads
245 of the flexible circuit film 40 can be joined with a solder,
containing pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
[0157] Thereby, the fine-pitched metal bumps 12 of the
semiconductor chip 2 can be fanned out through the copper traces
210 of the flexible circuit film 40 by bonding the semiconductor
chip 2 with the flexible circuit film 40. The semiconductor chip 2
has the fine-pitched metal bumps 12 connected to an external
circuit, such as a printed circuit board (PCB) comprising a glass
fiber as a core, through the copper traces 210 of the flexible
circuit film 40.
Embodiment 3
[0158] FIG. 6A is a schematically cross-sectional figure showing a
chip-on-film package. A flexible circuit film 42 includes a polymer
layer 200, a polymer layer 220, a wetting layer 240b, a wetting
layer 240c and copper traces 210 between the polymer layers 200 and
220, wherein the polymer layers 200 and 220 uncover top and bottom
sides of the copper traces 210 at the outer portion of the flexible
circuit film 42. The wetting layer 240b is on contact points,
exposed by openings 220a, of the copper traces 210 in the polymer
layer 220. The wetting layer 240c is on the copper traces 210 at
the outer portion of the flexible circuit film 42. The
specification of the polymer layer 200, the polymer layer 220 and
the copper traces 210 shown in FIG. 6A can be referred to as the
specification of the polymer layer 200, the polymer layer 220 and
the copper traces 210 illustrated in FIG. 3A. The specification of
the wetting layer 240b shown in FIG. 6A can be referred to as the
specification of the wetting layer 240b illustrated in FIGS. 3B and
3C. Alternatively, the copper traces 210 can be replaced by gold
traces having a thickness of between 3 and 30 .mu.m, of between 5
and 20 micrometers or of between 4 and 10 micrometers.
Alternatively, the copper traces 210 can be replaced by silver
traces having a thickness of between 3 and 30 .mu.m, of between 5
and 20 micrometers or of between 4 and 10 micrometers.
[0159] The wetting layer 240c having a thickness of between 0.05
and 2 micrometers, and preferably of between 0.1 and 1 micrometer,
may be gold, copper, nickel, silver, tin or a composite of the
above-mentioned materials. For example, the wetting layer 240c may
be a tin-containing layer, such as pure tin, a tin-silver alloy, a
tin-lead alloy or a tin-silver-copper alloy, having a thickness of
between 0.05 and 2 micrometers, and preferably of between 0.1 and 1
micrometer, on the copper traces 210 at the outer portion of the
flexible circuit film 42. Alternatively, the wetting layer 240c may
be a gold layer having a thickness of between 0.05 and 2
micrometers, and preferably of between 0.1 and 1 micrometer, on the
copper traces 210 at the outer portion of the flexible circuit film
42.
[0160] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210, exposed by the openings 220a, of the
flexible circuit film 42 through an interface bonding layer 250.
The specification of the interface bonding layer 250 shown in FIG.
6A can be referred to as the specification of the interface bonding
layer 250 formed in the process as illustrated in the first case
shown in FIGS. 3A and 3B. The methods, of bonding the metal bumps
12 of the semiconductor chip 2 with the copper traces 210 of the
flexible circuit film 42, as shown in FIG. 6A can be referred to as
the methods, of bonding the metal bumps 12 of the semiconductor
chip 2 with the copper traces 210 of the flexible circuit film 36,
as illustrated in the first and second cases shown in FIGS. 3B and
3C. When the step of bonding a gold layer of the metal bumps 12
with the wetting layer 240b of a tin-containing layer is performed,
the specification of the metal bumps 12 between the semiconductor
chip 2 and the interface bonding layer 250 shown in FIG. 6A can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 6A can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B.
[0161] Referring to FIG. 6B, a polymer layer 260 is filled into the
gap between the semiconductor chip 2 and the flexible circuit film
42, enclosing the metal bumps 12, by dispensing a polymer on the
flexible circuit film 42 close to the semiconductor chip 2, with
the polymer flowing into the gap between the semiconductor chip 2
and the flexible circuit film 42, and then curing the flowing
polymer at a temperature of between 100 and 250.degree. C. The
material of the polymer layer 260 may be expoxy, polyester,
polybenzoxazole or polyimide.
[0162] Metal joints 410c, such as tin-containing joints, are formed
on the metal pads 310a of the substrate 300 shown in FIG. 3E by
screen printing a solder paste containing flux and solder, such as
pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy, on the metal pads 310a and then reflowing the
solder paste. The metal joints 410a may be formed of pure tin, a
tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy.
The specification of the substrate 300 shown in FIG. 6B can be
referred to as the specification of the substrate 300 illustrated
in FIG. 3E. Two methods of bonding the flexible circuit film 42
with the substrate 300 are described as follow.
[0163] In a first case, referring to FIGS. 6B and 6C, when the
metal joints 410c are tin-containing joints, the metal joints 410c
can be used to be joined with the wetting layer 240c of pure tin or
an above-mentioned tin alloy using a heat press process, which
method is described as below. First, the substrate 300 is placed on
a stage kept at a temperature of between 150 and 350.degree. C.,
and preferably of between 200 and 300.degree. C. Next, the flexible
circuit film 42 is thermally pressed on the metal joints 410c on
the metal pads 310a of the substrate 300 at a force of between 20
and 150N, and preferably of between 50 and 90N, for a time of
between 0.1 and 10 seconds, and preferably of between 0.5 and 3
seconds, by a tool head kept at a temperature of between 250 and
500.degree. C., and preferably of between 350 and 450.degree. C.,
to join the wetting layer 240c with the metal joints 410c. In the
step of joining the wetting layer 240c with the metal joints 410c,
metal joints 410d can be formed between the topmost copper traces
340a of the substrate 300 and the copper traces 210 at the outer
portion of the flexible circuit film 42. The metal joints 410d can
be tin-containing joints having a thickness t19 of between 0.5 and
100 micrometers, and preferably of between 1 and 10 micrometers,
wherein the tin-containing joints may include pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy.
The tin-containing joints may include a tin-gold alloy, a
tin-silver-gold alloy, a tin-silver-gold-copper alloy or a
tin-lead-gold alloy at the bottom side of the tin-containing joints
due to the reaction between tin in the metal joints 410c and gold
at the top of the metal pads 310a. Preferably, the metal pads 310a
have a nickel layer between the metal joints 410d and the copper
traces 340a. The nickel layer serves as a barrier layer preventing
copper in the copper traces 340a from being solved in the metal
joints 410d after the metal joints 410d are formed between the
flexible circuit film 42 and the substrate 300. Next, the tool head
is removed from the flexible circuit film 42. Next, the substrate
300 bonded with flexible circuit film 42 is removed from the
stage.
[0164] In a second case, referring to FIGS. 6B and 6C, when the
metal joints 410c are tin-containing joints, the metal joints 410c
can be used to be joined with a gold layer of the wetting layer
240c using a heat press process, which method is described as
below. First, the substrate 300 is placed on a stage kept at a
temperature of between 150 and 350.degree. C., and preferably of
between 200 and 300.degree. C. Next, the flexible circuit film 42
is thermally pressed on the metal joints 410c on the metal pads
310a of the substrate 300 at a force of between 20 and 150N, and
preferably of between 50 and 90N, for a time of between 0.1 and 10
seconds, and preferably of between 0.5 and 3 seconds, by a tool
head kept at a temperature of between 250 and 500.degree. C., and
preferably of between 350 and 450.degree. C., to join the wetting
layer 240c with the metal joints 410c. In the step of joining the
wetting layer 240c with the metal joints 410c, the metal joints
410d can be formed between the topmost copper traces 340a of the
substrate 300 and the copper traces 210 at the outer portion of the
flexible circuit film 42. The metal joints 410d can be
tin-containing joints having a thickness t19 of between 0.5 and 100
micrometers, and preferably of between 1 and 10 micrometers. The
tin-containing joints may include a tin-silver-gold-copper alloy, a
tin-silver-gold alloy, a tin-gold alloy or a tin-lead-gold alloy at
the top side of the tin-containing joints due to the reaction
between tin in the metal joints 410c and gold at the top of the
wetting layer 240c. The tin-containing joints may include a
tin-gold alloy, a tin-silver-gold alloy, a tin-silver-gold-copper
alloy or a tin-lead-gold alloy at the bottom side of the
tin-containing joints due to the reaction between tin in the metal
joints 410c and gold at the top of the metal pads 310a. Preferably,
the metal pads 310a have a nickel layer between the metal joints
410d and the copper traces 340a. The nickel layer serves as a
barrier layer preventing copper in the copper traces 340a from
being solved in the metal joints 410d after the metal joints 410d
are formed between the flexible circuit film 42 and the substrate
300. Next, the tool head is removed from the flexible circuit film
42. Next, the substrate 300 bonded with the flexible circuit film
42 is removed from the stage.
[0165] Referring to FIG. 6C, there is no opening in the polymer
layer 200 exposing the copper traces 210 to lead the copper traces
210 to be connected to the substrate 300. Alternatively, the metal
joints 410d can be replaced by an anisotropic conductive film
(ACF). The anisotropic conductive film can be preformed on the
metal pads 310a of the substrate 300 shown in FIG. 3E, and then the
wetting layer 240c on the copper traces 210 at the outer portion of
the flexible circuit film 42 can be pressed on the anisotropic
conductive film, such that metal particles in the anisotropic
conductive film connects the wetting layer 240c of the flexible
circuit film 42 to the metal pads 310a of the substrate 300.
[0166] Referring to FIG. 6D, after the flexible circuit film 42 is
bonded with the substrate 300, a polymer layer 350a can be filled
into the gap between the flexible circuit film 42 and the substrate
300, enclosing the metal joints 410d and the wetting layer 240c, by
dispensing a polymer on the substrate 300 close to the flexible
circuit film 42, with the polymer flowing into the gap between the
flexible circuit film 42 and the substrate 300, and then curing the
flowing polymer at a temperature of between 100 and 250.degree. C.
The material of the polymer layer 350a may be expoxy, polyester or
polyimide, and the polymer layer 350a between the flexible circuit
film 42 and the substrate 300 has a thickness t20 of between 1 and
30 micrometers.
[0167] Referring to FIG. 6E, a polymer compound 360 is formed on
the semiconductor chip 2, on the flexible circuit film 42 and on a
peripheral region of the substrate 300 by molding an epoxy-based
polymer with carbon fillers therein on the semiconductor chip 2, on
the flexible circuit film 42 and on the peripheral region of the
substrate 300 at a temperature of between 130 and 250.degree. C.
Alternatively, the polymer compound 360 can be polyimide or
polyester. Preferably, the polymer compound 360 has a value of
Young's modulus less than 0.5 GPa.
[0168] Referring to FIGS. 6F and 6G, solder balls 501 shown in FIG.
6F may be being placed, in a ball-grid-array arrangement, on a flux
or solder paste 505 preformed on the metal pads 310b of the
substrate 300 using a ball placement process to form solder balls
502 shown in FIG. 6G on the substrate 300. The solder balls 502 can
be formed by printing the flux or solder paste 505 on the metal
pads 310b, next placing the solder balls 501, such as pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
having a diameter of between 0.25 and 1.2 millimeters on the flux
or solder paste 505, next reflowing the solder balls 501 at a peak
temperature of between 230 and 270.degree. C., and then cleaning
the remaining flux from the substrate 300. The solder balls 502
have a diameter of between 0.2 and 1.2 millimeters, and the solder
balls 502 may include pure tin, a tin-silver alloy, a
tin-silver-copper alloy or a tin-lead alloy.
[0169] For example, during the step of reflowing the solder balls
501, when the metal pads 310b have a bottommost metal layer of
gold, the gold layer of the metal pads 310b is solved in the solder
balls 502. Preferably, the metal pads 310b have a nickel layer
between the gold layer and the copper traces 340b. The nickel layer
serves as a barrier layer preventing copper in the copper traces
340b from being solved in the solder balls 502 after the solder
balls 502 are formed on the substrate 300. In the case of gold
serving as a bottommost metal layer of the metal pads 310b, the
solder balls 502, after being joined with the substrate 300, may
include a portion, of a tin-silver-gold-copper alloy, a
tin-silver-gold alloy, a tin-gold alloy or a tin-lead-gold alloy,
on the nickel layer of the metal pads 310b and under the copper
traces 340b of the substrate 300 due to the reaction between gold
in the metal pads 310b and tin in the solder balls 501 during
reflowing the solder balls 501.
[0170] After the solder balls 502 are formed on the substrate 300,
the substrate 300 and the polymer compound 360 can be optionally
cut into multiple units.
[0171] FIG. 6H is a perspective view showing FIG. 6G. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 42 by bonding the semiconductor chip 2 with the flexible
circuit film 42. The flexible circuit film 42 is also bonded with
the substrate 300 to connect the fine-pitched metal bumps 12 of the
semiconductor chip 2 with the circuit structure of the substrate
300. Thereby, the semiconductor chip 2 has the fine-pitched metal
bumps 12 connected to an external circuit, such as a printed
circuit board (PCB) comprising a glass fiber as a core, through the
copper traces 210 of the flexible circuit film 42 and the circuit
structure of the substrate 300.
[0172] Alternatively, referring to FIGS. 6I and 6J, the step of
forming the polymer compound 360, as shown in FIG. 6E, can be
omitted, that is, the semiconductor chip 2 and the flexible circuit
film 42 are uncovered by any polymer compound. Alternatively,
referring to FIG. 6K, the step of forming the polymer layer 350a,
as shown in FIG. 6D, can be omitted. Alternatively, referring to
FIG. 6L, the steps of forming the polymer layer 350a, as shown in
FIG. 6D, and of forming the polymer compound 360, as shown in FIG.
6E, can be omitted, that is, the semiconductor chip 2 and the
flexible circuit film 42 are uncovered by any polymer compound.
[0173] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 6E. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0174] Alternatively, the polymer compound 360 and the solder balls
502 can be omitted, as shown in FIG. 6D. The semiconductor chip 2
and the flexible circuit film 42 are uncovered by any polymer
compound. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0175] Alternatively, the polymer layer 350a and the solder balls
502 can be omitted, as shown in FIG. 6M. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0176] Alternatively, the polymer layer 350a, the polymer compound
360 and the solder balls 502 can be omitted, as shown in FIG. 6C.
The semiconductor chip 2 and the flexible circuit film 42 are
uncovered by any polymer compound. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0177] FIG. 6N is a schematically cross-sectional figure showing a
chip package including the semiconductor chip 2 joined with a
flexible circuit substrate 44 using a tape-automated-bonding (TAB)
technology. The above-mentioned flexible circuit film 42 can be
replaced by the flexible circuit film 44. The flexible circuit film
44 includes the polymer layer 200, the polymer layer 220, the
wetting layer 240b, the wetting layer 240c and the copper traces
210 between the polymer layers 200 and 220, wherein the polymer
layers 200 and 220 uncover top and bottom sides of the copper
traces 210 at the center portion and the outer portion of the
flexible circuit film 44. The wetting layer 240b is on the copper
traces 210 at the center portion of the flexible circuit film 44,
and the wetting layer 240c is on the copper traces 210 at the outer
portion of the flexible circuit film 44. The specification of the
polymer layer 200, the polymer layer 220 and the copper traces 210
shown in FIG. 6N can be referred to as the specification of the
polymer layer 200, the polymer layer 220 and the copper traces 210
illustrated in FIG. 3A. The specification of the wetting layer 240b
shown in FIG. 6N can be referred to as the specification of the
wetting layer 240b illustrated in FIG. 3S. The specification of the
wetting layer 240c shown in FIG. 6N can be referred to as the
specification of the wetting layer 240c illustrated in FIG. 6A.
Alternatively, the copper traces 210 can be replaced by gold traces
having a thickness of between 3 and 30 .mu.m, of between 5 and 20
micrometers or of between 4 and 10 micrometers. Alternatively, the
copper traces 210 can be replaced by silver traces having a
thickness of between 3 and 30 .mu.m, of between 5 and 20
micrometers or of between 4 and 10 micrometers.
[0178] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210 at the center portion of the flexible
circuit film 44 through the interface bonding layer 250. The
specification of the interface bonding layer 250 shown in FIG. 6N
can be referred to as the specification of the interface bonding
layer 250 formed in the process as illustrated in the first case
shown in FIGS. 3R and 3S. The method, of bonding the metal bumps 12
of the semiconductor chip 2 with the copper traces 210 of the
flexible circuit film 44, as shown in FIG. 6N can be referred to as
the method, of bonding the metal bumps 12 of the semiconductor chip
2 with the copper traces 210 of the flexible circuit film 38, as
illustrated in the first and second cases shown in FIG. 3R. When
the step of bonding a gold layer of the metal bumps 12 with the
wetting layer 240b of a tin-containing layer is performed, the
specification of the metal bumps 12 between the semiconductor chip
2 and the interface bonding layer 250 shown in FIG. 6N can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 6N can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B.
[0179] Referring to FIG. 6O, the polymer layer 260 can be formed by
dispensing a polymer on the semiconductor chip 2 with the polymer
enclosing the metal bumps 12 and the copper traces 210 at the
center portion of the flexible circuit film 44, and then curing the
polymer at a temperature of between 100 and 250.degree. C. The
material of the polymer layer 260 may be expoxy, polyester or
polyimide.
[0180] The metal joints 410c, such as tin-containing joints, are
formed on the metal pads 310a of the substrate 300 shown in FIG. 3E
by screen printing a solder paste containing flux and solder, such
as pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy, on the metal pads 310a and then reflowing the
solder paste. The metal joints 410a may be formed of pure tin, a
tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy.
The specification of the substrate 300 shown in FIG. 6O can be
referred to as the specification of the substrate 300 illustrated
in FIG. 3E.
[0181] Referring to FIG. 6P, after the polymer layer 260 is formed,
the flexible circuit film 44 is bonded with the substrate 300.
There is no opening in the polymer layer 200 exposing the copper
traces 210 to lead the copper traces 210 to be connected to the
substrate 300. The methods of bonding the flexible circuit film 44
with the substrate 300, as shown in FIG. 6P, can be referred to as
the methods of bonding the flexible circuit film 42 with the
substrate 300, as illustrated in the first and second cases shown
in FIGS. 6B and 6C.
[0182] Alternatively, the metal joints 410d can be replaced by an
anisotropic conductive film (ACF). The anisotropic conductive film
can be preformed on the metal pads 310a of the substrate 300 shown
in FIG. 3E, and then the wetting layer 240c on the copper traces
210 at the outer portion of the flexible circuit film 44 can be
pressed on the anisotropic conductive film, such that metal
particles in the anisotropic conductive film connects the wetting
layer 240c of the flexible circuit film 44 to the metal pads 310a
of the substrate 300.
[0183] Referring to FIG. 6Q, after the flexible circuit film 44 is
bonded with the substrate 300, the polymer layer 350a can be
optionally filled into the gap between the flexible circuit film 44
and the substrate 300, enclosing the metal joints 410d and the
wetting layer 240c, by dispensing a polymer on the substrate 300
close to the flexible circuit film 44, with the polymer flowing
into the gap between the flexible circuit film 44 and the substrate
300, and then curing the flowing polymer at a temperature of
between 100 and 250.degree. C. The specification of the polymer
layer 350a shown in FIG. 6Q can be referred to as the specification
of the polymer layer 350a illustrated in FIG. 6D.
[0184] Referring to FIG. 6R, the polymer compound 360 can be
optionally formed on the semiconductor chip 2, on the flexible
circuit film 44 and on a peripheral region of the substrate 300 by
molding an epoxy-based polymer with carbon fillers therein on the
semiconductor chip 2, on the flexible circuit film 44 and the
peripheral region of the substrate 300 at a temperature of between
130 and 250.degree. C. Alternatively, the polymer compound 360 can
be polyimide or polyester. Preferably, the polymer compound 360 has
a value of Young's modulus less than 0.5 GPa.
[0185] Referring to FIG. 6S, after the polymer compound 360 is
formed, the solder balls 502 may be formed, in a ball-grid-array
arrangement, on the metal pads 310b of the substrate 300 using a
ball placement process. The process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as shown in FIG.
6S can be referred to as the process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as illustrated in
FIGS. 6F and 6G. The specification of the solder balls 502 shown in
FIG. 6S can be referred to as the specification of the solder balls
502 illustrated in FIGS. 6F and 6G.
[0186] Thereby, the fine-pitched metal bumps 12 of the
semiconductor chip 2 can be fanned out through the copper traces
210 of the flexible circuit film 44 by bonding the semiconductor
chip 2 with the flexible circuit film 44. The flexible circuit film
44 is also bonded with the substrate 300 to connect the
fine-pitched metal bumps 12 of the semiconductor chip 2 with the
circuit structure of the substrate 300. The semiconductor chip 2
has the fine-pitched metal bumps 12 connected to an external
circuit, such as a printed circuit board (PCB) comprising a glass
fiber as a core, through the copper traces 210 of the flexible
circuit film 44 and the circuit structure of the substrate 300.
[0187] Alternatively, the step of forming the polymer compound 360,
as shown in FIG. 6R, can be omitted, that is, the semiconductor
chip 2 and the flexible circuit film 44 are uncovered by any
polymer compound. Alternatively, the step of forming the polymer
layer 350a, as shown in FIG. 6Q, can be omitted. Alternatively, the
steps of forming the polymer layer 350a, as shown in FIG. 6Q, and
of forming the polymer compound 360, as shown in FIG. 6R, can be
omitted, that is, the semiconductor chip 2 and the flexible circuit
film 44 are uncovered by any polymer compound.
[0188] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 6R. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0189] Alternatively, the polymer compound 360 and the solder balls
502 can be omitted, as shown in FIG. 6Q. The semiconductor chip 2
and the flexible circuit film 44 are uncovered by any polymer
compound. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0190] Alternatively, the polymer layer 350a and the solder balls
502 can be omitted, as shown in FIG. 6T. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0191] Alternatively, the polymer layer 350a, the polymer compound
360 and the solder balls 502 can be omitted, as shown in FIG. 6P.
The semiconductor chip 2 and the flexible circuit film 44 are
uncovered by any polymer compound. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
Embodiment 4
[0192] FIG. 7A is a schematically cross-sectional figure showing a
chip-on-film package. A flexible circuit film 46 includes a polymer
layer 200, a polymer layer 220, a wirebondable layer 230, a wetting
layer 240b and copper traces 210 between the polymer layers 200 and
220. The wirebondable layer 230 is on first contact points, exposed
by openings 220b, of the copper traces 210 in the polymer layer
220, and the wetting layer 240b is on second contact points,
exposed by openings 220a, of the copper traces 210 in the polymer
layer 220. The specification of the polymer layer 200, the polymer
layer 220 and the copper traces 210 shown in FIG. 7A can be
referred to as the specification of the polymer layer 200, the
polymer layer 220 and the copper traces 210 illustrated in FIG. 3A.
The specification of the wetting layer 240b shown in FIG. 7A can be
referred to as the specification of the wetting layer 240b
illustrated in FIGS. 3B and 3C. Alternatively, the copper traces
210 can be replaced by gold traces having a thickness of between 3
and 30 .mu.m, of between 5 and 20 micrometers or of between 4 and
10 micrometers. Alternatively, the copper traces 210 can be
replaced by silver traces having a thickness of between 3 and 30
.mu.m, of between 5 and 20 micrometers or of between 4 and 10
micrometers.
[0193] The wirebondable layer 230 having a thickness of between
0.05 and 2 micrometers, and preferably of between 0.1 and 1
micrometer, may be gold, copper, aluminum, nickel, silver,
palladium or a composite of the above-mentioned materials. For
example, the wirebondable layer 230 may be a gold layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 1 micrometer, on the first contact points, exposed
by the openings 220b, of the copper traces 210 in the polymer layer
220. Alternatively, the wirebondable layer 230 may be a palladium
layer having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.05 and 1 micrometer, on the first contact
points, exposed by the openings 220b, of the copper traces 210 in
the polymer layer 220. Alternatively, the wirebondable layer 230
may be a silver layer having a thickness of between 0.05 and 2
micrometers, and preferably of between 0.1 and 1 micrometer, on the
first contact points, exposed by the openings 220b, of the copper
traces 210 in the polymer layer 220. Alternatively, the
wirebondable layer 230 may be an aluminum layer having a thickness
of between 0.05 and 2 micrometers, and preferably of between 0.1
and 1 micrometer, on the first contact points, exposed by the
openings 220b, of the copper traces 210 in the polymer layer 220.
Alternatively, the wirebondable layer 230 comprises a nickel layer
having a thickness of between 0.05 and 1 micrometer on the first
contact points, exposed by the openings 220b, of the copper traces
210 in the polymer layer 220, and a gold layer having a thickness
of between 0.05 and 1 micrometer on the nickel layer.
[0194] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210, exposed by the openings 220a, of the
flexible circuit film 46 through an interface bonding layer 250.
The specification of the interface bonding layer 250 shown in FIG.
7A can be referred to as the specification of the interface bonding
layer 250 formed in the process as illustrated in the first case
shown in FIGS. 3A and 3B. The methods, of bonding the metal bumps
12 of the semiconductor chip 2 with the copper traces 210 of the
flexible circuit film 46, as shown in FIG. 7A can be referred to as
the methods, of bonding the metal bumps 12 of the semiconductor
chip 2 with the copper traces 210 of the flexible circuit film 36,
as illustrated in the first and second cases shown in FIGS. 3B and
3C. When the step of bonding a gold layer of the metal bumps 12
with the wetting layer 240b of a tin-containing layer is performed,
the specification of the metal bumps 12 between the semiconductor
chip 2 and the interface bonding layer 250 shown in FIG. 7A can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 7A can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B.
[0195] Referring to FIG. 7B, a polymer layer 260 is filled into the
gap between the semiconductor chip 2 and the flexible circuit film
46, enclosing the metal bumps 12, by dispensing a polymer on the
flexible circuit film 46 close to the semiconductor chip 2, with
the polymer flowing into the gap between the semiconductor chip 2
and the flexible circuit film 46, and then curing the flowing
polymer at a temperature of between 100 and 250.degree. C. The
material of the polymer layer 260 may be expoxy, polyester,
polybenzoxazole or polyimide.
[0196] A substrate 300a comprises a circuit structure in the
substrate 300a, an insulating layer 320, an insulating layer 330,
wirebonding pads 310c and metal pads 310b. The circuit structure
comprises copper traces (including 340a and 340b) each having a
thickness between 5 and 30 micrometers. The wirebonding pads 310c
are formed on the topmost copper traces 340a exposed by openings in
the insulating layer 320, and the openings may be filled up with
the wirebonding pads 310c. The metal pads 310b are formed on the
bottommost copper traces 340b exposed by openings 330a in the
insulating layer 330. The wirebonding pads 310c are connected to
the metal pads 310b through the copper traces (comprising the
copper traces 340a and 340b) in the substrate 300a. The
specification of the metal pads 310b, the insulating layer 320 and
the insulating layer 330 shown in FIG. 7B can be referred to as the
specification of the metal pads 310b, the insulating layer 320 and
the insulating layer 330 illustrated in FIG. 3E.
[0197] The material of the wirebonding pads 310c may be gold,
copper, nickel, aluminum, palladium, silver or a composite of the
above-mentioned materials, and the wirebonding pads 310c have a
thickness t21 of between 0.05 and 2 micrometers, and preferably of
between 0.1 and 1 micrometer. For example, the wirebonding pads
310c may be formed by electroplating or electroless plating a gold
layer with a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.05 and 1 micrometer, on the topmost copper
traces 340a exposed by openings in the insulating layer 320, and
the openings in the insulating layer 320 may be filled up with the
gold layer. Alternatively, the wirebonding pads 310c may be formed
by electroplating or electroless plating a palladium layer with a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 1 micrometer, on the topmost copper traces 340a
exposed by openings in the insulating layer 320, and the openings
in the insulating layer 320 may be filled up with the palladium
layer. Alternatively, the wirebonding pads 310c may be formed by
electroplating or electroless plating a silver layer with a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.1 and 1 micrometer, on the topmost copper traces 340a
exposed by openings in the insulating layer 320, and the openings
in the insulating layer 320 may be filled up with the silver layer.
Alternatively, the wirebonding pads 310c may be formed by
electroplating or electroless plating an aluminum layer with a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.1 and 1 micrometer, on the topmost copper traces 340a
exposed by openings in the insulating layer 320, and the openings
in the insulating layer 320 may be filled up with the aluminum
layer. Alternatively, the wirebonding pads 310c may be formed by
electroless plating a nickel layer with a thickness of between 0.05
and 1 micrometer on the topmost copper traces 340a exposed by
openings in the insulating layer 320, and electroless plating a
gold layer with a thickness of between 0.05 and 1 micrometer on the
nickel layer in the openings in the insulating layer 320, and the
openings in the insulating layer 320 may be filled up with the
nickel layer and the gold layer.
[0198] In a case, the substrate 300a may comprise a core layer,
such as a glass fiber reinforced epoxy with a thickness of between
200 and 2,000 .mu.m, multiple copper circuit layers respectively
over and under the core layer, and multiple polymer layers between
the neighboring copper circuit layers. The copper circuit layers
provide the circuit structure in the substrate 300a. The
wirebonding pads 310c are on the copper traces 340a of the topmost
copper circuit layer, and the metal pads 310b are on the copper
traces 340b of the bottommost copper circuit layer.
[0199] In another case, the substrate 300a may comprise multiple
copper circuit layers and multiple ceramic layers between the
neighboring copper circuit layers. The copper circuit layers
provide the circuit structure in the substrate 300a. The
wirebonding pads 310c are on the copper traces 340a of the topmost
copper circuit layer, and the metal pads 310b are on the copper
traces 340b of the bottommost copper circuit layer.
[0200] The substrate 300a may be a ball grid array (BGA) substrate
with a thickness t22 of between 200 and 2,000 .mu.m. Alternatively,
the substrate 300a may be a glass fiber reinforced epoxy based
substrate with a thickness t22 of between 200 and 2,000 .mu.m.
Alternatively, the substrate 300a may be a silicon substrate with a
thickness t22 of between 200 and 2,000 .mu.m. Alternatively, the
substrate 300a may be a ceramic substrate with a thickness t22 of
between 200 and 2,000 .mu.m. Alternatively, the substrate 300a may
be an organic substrate with a thickness t22 of between 200 and
2,000 .mu.m.
[0201] Referring to FIGS. 7B and 7C, a glue material 650 is first
formed on the insulating layer 320 of the substrate 300a by a
dispensing process after the semiconductor chip 2 is bonded with
the flexible circuit film 46. Next, the polymer layer 200 of the
flexible circuit film 46 adheres onto the glue material 650, and
then the glue material 650 is baked at a temperature of between 100
and 200.degree. C. and to a thickness t23 between 5 and 30
micrometers if the glue material 650 is an epoxy. Alternatively,
the glue material 650 can be polyimide, silver-filed epoxy or
polyester. Thereby, the flexible circuit film 46 can be joined with
the substrate 300a. In another word, the flexible circuit film 46
bonded with the semiconductor chip 2 can be joined with the
substrate 300a using the glue material 650.
[0202] Referring to FIG. 7C, there is no opening in the polymer
layer 200 exposing the copper traces 210 to lead the copper traces
210 to be connected to the substrate 300a.
[0203] Referring to FIG. 7D, after the flexible circuit film 46 is
joined with the substrate 300a, wireboning wires 400 having a
diameter of between 12 and 40 micrometers are bonded with the
wirebondable layer 230 and with the wirebonding pads 310c via a
wire-bonding process. The wireboning wires 400 may be gold wires
with a diameter of between 12 and 40 micrometers. Thereby, the
wirebondable layer 230 of the flexible circuit film 46 can be
electrically connected to the wirebonding pads 310c of the
substrate 300a through the wireboning wires 400.
[0204] Referring to FIG. 7E, a polymer compound 360 is formed on
the semiconductor chip 2, on the flexible circuit film 46 and on a
peripheral region of the substrate 300a by molding an epoxy-based
polymer with carbon fillers therein on the semiconductor chip 2, on
the flexible circuit film 46 and on the peripheral region of the
substrate 300a at a temperature of between 130 and 250.degree. C.
The polymer compound 360 encloses the wireboning wires 400, to
protect the wireboning wires 400. Alternatively, the polymer
compound 360 can be polyimide or polyester. Preferably, the polymer
compound 360 has a value of Young's modulus less than 0.5 GPa.
[0205] Referring to FIG. 7F, after the polymer compound 360 is
formed, the solder balls 502 may be formed, in a ball-grid-array
arrangement, on the metal pads 310b of the substrate 300a using a
ball placement process. The process, of forming the solder balls
502 on the metal pads 310b of the substrate 300a, as shown in FIG.
7F can be referred to as the process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as illustrated in
FIGS. 3J and 3K. The specification of the solder balls 502 shown in
FIG. 7F can be referred to as the specification of the solder balls
502 illustrated in FIGS. 3J and 3K. After the solder balls 502 are
formed on the substrate 300a, the substrate 300a and the polymer
compound 360 can be optionally cut into multiple units.
[0206] FIG. 7G is a perspective view showing FIG. 7F. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 46 by bonding the semiconductor chip 2 with the flexible
circuit film 46. The flexible circuit film 46 is also joined with
the substrate 300a, and the wireboning wires 400 connect the
flexible circuit film 46 to the substrate 300a. Thereby, the
semiconductor chip 2 has the fine-pitched metal bumps 12 connected
to an external circuit, such as a printed circuit board (PCB)
comprising a glass fiber as a core, through the copper traces 210
of the flexible circuit film 46, the wirebonding wires 400 and the
circuit structure of the substrate 300a.
[0207] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 7E. The substrate 300a can be optionally sawed into
multiple units. After sawing the substrate 300a, the metal pads
310b of the substrate 300a can be joined with a solder, containing
pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
[0208] FIG. 7H is a schematically cross-sectional figure showing a
chip package including the semiconductor chip 2 joined with a
flexible circuit substrate 48 using a tape-automated-bonding (TAB)
technology. The above-mentioned flexible circuit film 46 can be
replaced by the flexible circuit film 48. The flexible circuit film
48 includes the polymer layer 200, the polymer layer 220, the
wirebondable layer 230, the wetting layer 240b and the copper
traces 210 between the polymer layers 200 and 220, wherein the
openings 220b in the polymer layer 220 expose contact points of the
copper traces 210, and the polymer layers 200 and 220 uncover top
and bottom sides of the copper traces 210 at the center portion of
the flexible circuit film 48. The wirebondable layer 230 is on the
contact points, exposed by openings 220b, of the copper traces 210
in the polymer layer 220, and the wetting layer 240b is on the
copper traces 210 at the center portion of the flexible circuit
film 48. The specification of the polymer layer 200, the polymer
layer 220 and the copper traces 210 shown in FIG. 7H can be
referred to as the specification of the polymer layer 200, the
polymer layer 220 and the copper traces 210 illustrated in FIG. 3A.
The specification of the wirebondable layer 230 shown in FIG. 7H
can be referred to as the specification of the wirebondable layer
230 illustrated in FIG. 7A. The specification of the wetting layer
240b shown in FIG. 7H can be referred to as the specification of
the wetting layer 240b illustrated in FIG. 3S. Alternatively, the
copper traces 210 can be replaced by gold traces having a thickness
of between 3 and 30 .mu.m, of between 5 and 20 micrometers or of
between 4 and 10 micrometers. Alternatively, the copper traces 210
can be replaced by silver traces having a thickness of between 3
and 30 .mu.m, of between 5 and 20 micrometers or of between 4 and
10 micrometers.
[0209] The metal bumps 12 of the semiconductor chip 2 are bonded
with the copper traces 210 at the center portion of the flexible
circuit film 48 through the interface bonding layer 250. The
specification of the interface bonding layer 250 shown in FIG. 7H
can be referred to as the specification of the interface bonding
layer 250 formed in the process as illustrated in the first case
shown in FIGS. 3R and 3S. The method, of bonding the metal bumps 12
of the semiconductor chip 2 with the copper traces 210 of the
flexible circuit film 48, as shown in FIG. 7H can be referred to as
the method, of bonding the metal bumps 12 of the semiconductor chip
2 with the copper traces 210 of the flexible circuit film 38, as
illustrated in the first and second cases shown in FIGS. 3R and 3S.
When the step of bonding a gold layer of the metal bumps 12 with
the wetting layer 240b of a tin-containing layer is performed, the
specification of the metal bumps 12 between the semiconductor chip
2 and the interface bonding layer 250 shown in FIG. 7H can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3R and
3S. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 7H can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
as illustrated in the second case shown in FIG. 3S.
[0210] Referring to FIG. 7I, the polymer layer 260 can be formed by
dispensing a polymer on the semiconductor chip 2 with the polymer
enclosing the metal bumps 12 and the copper traces 210 at the
center portion of the flexible circuit film 48, and then curing the
polymer at a temperature of between 100 and 250.degree. C. The
material of the polymer layer 260 may be expoxy, polyester or
polyimide. The specification of the substrate 300a shown in FIG. 7I
can be referred to as the specification of the substrate 300a
illustrated in FIG. 7B.
[0211] Referring to FIGS. 7I and 7J, the glue material 650 is first
formed on the insulating layer 320 of the substrate 300a by a
dispensing process after the semiconductor chip 2 is bonded with
the flexible circuit film 48. Next, the polymer layer 200 of the
flexible circuit film 48 adheres onto the glue material 650, and
then the glue material 650 is baked at a temperature of between 100
and 200.degree. C. and to a thickness t23 between 5 and 30
micrometers if the glue material 650 is an epoxy. Alternatively,
the glue material 650 can be polyimide or polyester. Thereby, the
flexible circuit film 48 can be joined with the substrate 300a. In
another word, the flexible circuit film 48 bonded with the
semiconductor chip 2 can be joined with the substrate 300a using
the glue material 650.
[0212] Referring to FIG. 7J, there is no opening in the polymer
layer 200 exposing the copper traces 210 to lead the copper traces
210 to be connected to the substrate 300a.
[0213] Referring to FIG. 7K, after the flexible circuit film 48 is
joined with the substrate 300a, the wireboning wires 400 having a
diameter of between 12 and 40 micrometers are bonded with the
wirebondable layer 230 and with the wirebonding pads 310c via a
wire-bonding process. The wireboning wires 400 may be gold wires
with a diameter of between 12 and 40 micrometers. Thereby, the
wirebondable layer 230 of the flexible circuit film 48 can be
electrically connected to the wirebonding pads 310c of the
substrate 300a through the wireboning wires 400.
[0214] Referring to FIG. 7L, the polymer compound 360 is formed on
the semiconductor chip 2, on the flexible circuit film 48 and on a
peripheral region of the substrate 300a by molding an epoxy-based
polymer with carbon fillers therein on the semiconductor chip 2, on
the flexible circuit film 48 and on the peripheral region of the
substrate 300a at a temperature of between 130 and 250.degree. C.
The polymer compound 360 encloses the wireboning wires 400, to
protect the wireboning wires 400. Alternatively, the polymer
compound 360 can be polyimide or polyester. Preferably, the polymer
compound 360 has a value of Young's modulus less than 0.5 GPa.
[0215] Referring to FIG. 7M, after the polymer compound 360 is
formed, the solder balls 502 may be formed, in a ball-grid-array
arrangement, on the metal pads 310b of the substrate 300a using a
ball placement process. The process, of forming the solder balls
502 on the metal pads 310b of the substrate 300a, as shown in FIG.
7M can be referred to as the process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as illustrated in
FIGS. 3J and 3K. The specification of the solder balls 502 shown in
FIG. 7M can be referred to as the specification of the solder balls
502 illustrated in FIGS. 3J and 3K. After the solder balls 502 are
formed on the substrate 300a, the substrate 300a and the polymer
compound 360 can be optionally cut into multiple units.
[0216] The fine-pitched metal bumps 12 of the semiconductor chip 2
can be fanned out through the copper traces 210 of the flexible
circuit film 48 by bonding the semiconductor chip 2 with the
flexible circuit film 48. The flexible circuit film 48 is also
joined with the substrate 300a, and the wireboning wires 400
connect the flexible circuit film 48 to the substrate 300a.
Thereby, the semiconductor chip 2 has the fine-pitched metal bumps
12 connected to an external circuit, such as a printed circuit
board (PCB) comprising a glass fiber as a core, through the copper
traces 210 of the flexible circuit film 48, the wirebonding wires
400 and the circuit structure of the substrate 300a.
[0217] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 7L. The substrate 300a can be optionally sawed into
multiple units. After sawing the substrate 300a, the metal pads
310b of the substrate 300a can be joined with a solder, containing
pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
Embodiment 5
[0218] FIG. 8A is a schematically cross-sectional figure showing a
chip-on-film package. A flexible circuit film 42 includes a polymer
layer 200, a polymer layer 220, a wetting layer 240b, a wetting
layer 240c and copper traces 210 between the polymer layers 200 and
220, wherein the polymer layers 200 and 220 uncover top and bottom
sides of the copper traces 210 at the outer portion of the flexible
circuit film 42, and openings 220a in the polymer layer 220 expose
contact points 71, 72, 73 and 74 of the copper traces 210. The
wetting layer 240b is on the contact points 71, 72, 73 and 74 of
the copper traces 210 exposed by the openings 220a in the polymer
layer 220. The wetting layer 240c is on the copper traces 210 at
the outer portion of the flexible circuit film 42. The
specification of the polymer layer 200, the polymer layer 220 and
the copper traces 210 shown in FIG. 8A can be referred to as the
specification of the polymer layer 200, the polymer layer 220 and
the copper traces 210 illustrated in FIG. 3A. The specification of
the wetting layer 240b shown in FIG. 8A can be referred to as the
specification of the wetting layer 240b illustrated in FIGS. 3B and
3C. The specification of the wetting layer 240c shown in FIG. 8A
can be referred to as the specification of the wetting layer 240c
illustrated in FIG. 6A. Alternatively, the copper traces 210 can be
replaced by gold traces having a thickness of between 3 and 30
.mu.m, of between 5 and 20 micrometers or of between 4 and 10
micrometers. Alternatively, the copper traces 210 can be replaced
by silver traces having a thickness of between 3 and 30 .mu.m, of
between 5 and 20 micrometers or of between 4 and 10
micrometers.
[0219] The metal bumps 12 of the semiconductor chip 2 are bonded
with the contact points 71 and 72, exposed by the openings 220a, of
the copper traces 210 of the flexible circuit film 42 through an
interface bonding layer 250, and multiple metal bumps 62 of an
electronic device 60 are bonded with the contact points 73 and 74,
exposed by the openings 220a, of the copper traces 210 of the
flexible circuit film 42 through an interface bonding layer 255.
The electronic device 60 can be a passive device, such as resistor,
capacitor or inductor, or another semiconductor chip. The
semiconductor chip 2 is connected to the electronic device 60
through the copper trace 210 at the center portion of the flexible
circuit film 42. A method for bonding the metal bumps 12 of the
semiconductor chip 2 with the contact points 71 and 72 of the
copper traces 210 of the flexible circuit film 42, and for bonding
the metal bumps 62 of the electronic device 60 with the contact
points 73 and 74 of the copper traces 210 of the flexible circuit
film 42 are described as shown in FIG. 8B and FIG. 8C.
[0220] Referring to FIGS. 8B and 8C, the flexible circuit film 42
can be connected to the semiconductor chip 2 and to the electronic
device 60. The flexible circuit film 42 has the wetting layer 240c
to be joined with the substrate 300 shown in FIG. 3E, and the
wetting layer 240b to be joined with the metal bumps 12 of the
semiconductor chip 2 and with the metal bumps 62 of the electronic
device 60. The metal bumps 62 of the electronic device 60 having a
thickness of between 5 and 200 micrometers, and preferably of
between 10 and 50 micrometers, may comprise gold, copper, nickel,
silver, tin, palladium or a composite of the above-mentioned
materials. A pitch between the neighboring metal bumps 62 is
greater than 1 micrometer, greater than 5 micrometers, less than 35
micrometers, less than 30 micrometers, less than 25 micrometers or
less than 20 micrometers, such as between 1 and 30 micrometers or
between 2 and 20 micrometers. For example, the metal bumps 62 may
be gold bumps having a thickness of between 5 and 200 micrometers,
and preferably of between 10 and 50 micrometers. Alternatively, the
metal bumps 62 may be copper bumps having a thickness of between 5
and 200 micrometers, and preferably of between 10 and 50
micrometers. Alternatively, the metal bumps 62 may be
tin-containing bumps having a thickness of between 5 and 200
micrometers, and preferably of between 10 and 50 micrometers,
wherein the tin-containing bumps may be made of a lead-free solder,
such as a tin-silver alloy or a tin-silver-copper alloy, of an
eutectic solder, such as a tin-lead alloy, or of a high-lead solder
containing more than 90 weight percent of lead. Alternatively, the
metal bumps 62 may comprise a copper layer having a thickness of
between 0.5 and 45 micrometers, and preferably of between 5 and 35
micrometers, a nickel layer having a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
copper layer, and a gold layer having a thickness of between 0.5
and 5 micrometers, and preferably of between 1 and 3 micrometers,
on the nickel layer.
[0221] In a first case, referring to FIGS. 8B and 8C, the metal
bumps 12 and 62 have the above-mentioned gold layer, at the tips of
the metal bumps 12 and 62, capable of being used to be joined with
the wetting layer 240b of pure tin or an above-mentioned tin alloy
using flip-chip bonding, which method is described as below. First,
the flexible circuit film 42 is placed on a stage 600a kept at a
temperature of between 150 and 450.degree. C., and preferably of
between 250 and 400.degree. C., and the semiconductor chip 2 is
held by vacuum adsorption on a tool head 610a kept at a temperature
of between 250 and 500.degree. C., of between 350 and 450.degree.
C. or of between 100 and 500.degree. C. Next, the semiconductor
chip 2 is thermally pressed on the wetting layer 240b of the
flexible circuit film 42 at a force of between 20 and 150N, and
preferably of between 50 and 90N, for a time of between 0.1 and 10
seconds, and preferably of between 0.5 and 3 seconds, by the tool
head 610a kept at a temperature of between 250 and 500.degree. C.,
of between 350 and 450.degree. C. or of between 100 and 500.degree.
C., optionally applying ultrasonic waves to the metal bumps 12 and
to the wetting layer 240b of the flexible circuit film 42, to join
the metal bumps 12 with the wetting layer 240b. In the step of
joining the metal bumps 12 with the wetting layer 240b, the
interface bonding layer 250, such as a metal alloy, may be formed
between the metal bumps 12 and the contact points 71 and 72 of the
copper traces 210. The interface bonding layer 250 between the
metal bumps 12 and the contact points 71 and 72 of the copper
traces 210 has a thickness of between 0.2 and 10 micrometers or of
between 0.4 and 5 micrometers. When the wetting layer 240b before
bonded with the gold layer of the metal bumps 12 is pure tin, the
interface bonding layer 250 is a tin-gold alloy having a thickness
of between 0.2 and 10 micrometers or of between 0.4 and 5
micrometers, wherein an atomic ratio of tin to gold in the tin-gold
alloy is between 0.2 and 0.3. When the wetting layer 240b before
bonded with the gold layer of the metal bumps 12 is a
tin-silver-copper alloy, the interface bonding layer 250 is a
tin-silver-gold-copper alloy having a thickness of between 0.2 and
10 micrometers or of between 0.4 and 5 micrometers. When the
wetting layer 240b before bonded with the gold layer of the metal
bumps 12 is a tin-silver alloy, the interface bonding layer 250 is
a tin-silver-gold alloy having a thickness of between 0.2 and 10
micrometers or of between 0.4 and 5 micrometers. Next, the tool
head 610a is removed from the semiconductor chip 2. Next, the
electronic device 60 is held by vacuum adsorption on the tool head
610a kept at a temperature of between 250 and 500.degree. C., of
between 350 and 450.degree. C. or of between 100 and 500.degree. C.
Next, the electronic device 60 is thermally pressed on the wetting
layer 240b of the flexible circuit film 42 at a force of between 20
and 150N, and preferably of between 50 and 90N, for a time of
between 0.1 and 10 seconds, and preferably of between 0.5 and 3
seconds, by the tool head 610a kept at a temperature of between 250
and 500.degree. C., of between 350 and 450.degree. C. or of between
100 and 500.degree. C., optionally applying ultrasonic waves to the
metal bumps 62 and to the wetting layer 240b of the flexible
circuit film 42, to join the metal bumps 62 with the wetting layer
240b. Referring to FIGS. 8A and 8C, in the step of joining the
metal bumps 62 with the wetting layer 240b, the interface bonding
layer 255, such as a metal alloy, may be formed between the metal
bumps 62 and the contact points 73 and 74 of the copper traces 210.
The interface bonding layer 255 between the metal bumps 62 and the
contact points 73 and 74 of the copper traces 210 has a thickness
of between 0.2 and 10 micrometers or of between 0.4 and 5
micrometers. When the wetting layer 240b before bonded with the
gold layer of the metal bumps 62 is pure tin, the interface bonding
layer 255 is a tin-gold alloy having a thickness of between 0.2 and
10 micrometers or of between 0.4 and 5 micrometers, wherein an
atomic ratio of tin to gold in the tin-gold alloy is between 0.2
and 0.3. When the wetting layer 240b before bonded with the gold
layer of the metal bumps 62 is a tin-silver-copper alloy, the
interface bonding layer 255 is a tin-silver-gold-copper alloy
having a thickness of between 0.2 and 10 micrometers or of between
0.4 and 5 micrometers. When the wetting layer 240b before bonded
with the gold layer of the metal bumps 62 is a tin-silver alloy,
the interface bonding layer 255 is a tin-silver-gold alloy having a
thickness of between 0.2 and 10 micrometers or of between 0.4 and 5
micrometers. Next, the tool head 610a is removed from the
electronic device 60. Next, the flexible circuit film 42 bonded
with the semiconductor chip 2 and with the electronic device 60 is
removed from the stage 600a.
[0222] The specification of the metal bumps 12 between the
semiconductor chip 2 and the interface bonding layer 250 shown in
FIGS. 8A and 8C can be referred to as the specification of the
metal bumps 12, between the semiconductor chip 2 and the interface
bonding layer 250, formed in the process as illustrated in the
first case shown in FIGS. 3A and 3B.
[0223] The metal bumps 62 bonded with the contact points 73 and 74
of the copper traces 210 of the flexible circuit film 42 have a
thickness of between 5 and 200 micrometers, and preferably of
between 10 and 50 micrometers. For example, the metal bumps 62
between the electronic device 60 and the interface bonding layer
255 may include a gold layer having a thickness of between 5 and
200 micrometers, and preferably of between 10 and 50 micrometers,
between the electronic device 60 and the interface bonding layer
255. Alternatively, the metal bumps 62 between the electronic
device 60 and the interface bonding layer 255 may include a copper
layer having a thickness of between 5 and 200 micrometers, and
preferably of between 10 and 50 micrometers, between the electronic
device 60 and the interface bonding layer 255. Alternatively, the
metal bumps 62 between the electronic device 60 and the interface
bonding layer 255 may include a copper layer having a thickness of
between 0.5 and 45 micrometers, and preferably of between 5 and 35
micrometers, between the electronic device 60 and the interface
bonding layer 255, a nickel layer having a thickness of between 0.5
and 5 micrometers, and preferably of between 1 and 3 micrometers,
on the copper layer and between the copper layer and the interface
bonding layer 255, and a gold layer having a thickness of between
0.5 and 5 micrometers, and preferably of between 1 and 3
micrometers, on the nickel layer and between the nickel layer and
the interface bonding layer 255. Alternatively, the metal bumps 62
between the electronic device 60 and the interface bonding layer
255 may include a copper layer having a thickness of between 0.5
and 45 micrometers, and preferably of between 5 and 35 micrometers,
between the electronic device 60 and the interface bonding layer
255, and a nickel layer having a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
copper layer and between the copper layer and the interface bonding
layer 255. Alternatively, the metal bumps 62 between the electronic
device 60 and the interface bonding layer 255 may include a copper
layer having a thickness of between 0.5 and 45 micrometers, and
preferably of between 5 and 35 micrometers, between the electronic
device 60 and the interface bonding layer 255, and a gold layer
having a thickness of between 0.5 and 5 micrometers, and preferably
of between 1 and 3 micrometers, on the copper layer and between the
copper layer and the interface bonding layer 255.
[0224] In a second case, referring to FIGS. 8B and 8C, the metal
bumps 12 and 62 have the above-mentioned gold layer, at the tips of
the metal bumps 12 and 62, capable of being used to be joined with
a gold layer of the wetting layer 240b using flip-chip bonding,
which method is described as below. First, the flexible circuit
film 42 is placed on the stage 600a kept at a temperature of
between 150 and 450.degree. C., and preferably of between 250 and
400.degree. C., and the semiconductor chip 2 is held by vacuum
adsorption on the tool head 610a kept at a temperature of between
250 and 500.degree. C., of between 350 and 450.degree. C. or of
between 100 and 500.degree. C. Next, the semiconductor chip 2 is
thermally pressed on the wetting layer 240b of the flexible circuit
film 42 at a force of between 20 and 150N, and preferably of
between 70 and 120N, for a time of between 0.1 and 10 seconds, and
preferably of between 0.5 and 3 seconds, by the tool head 610a kept
at a temperature of between 250 and 500.degree. C., of between 350
and 450.degree. C. or of between 100 and 500.degree. C., optionally
applying ultrasonic waves to the metal bumps 12 and to the wetting
layer 240b of the flexible circuit film 42, to join the
above-mentioned gold layer of the metal bumps 12 with the gold
layer of the wetting layer 240b. Next, the tool head 610a is
removed from the semiconductor chip 2. Next, the electronic device
60 is held by vacuum adsorption on the tool head 610a kept at a
temperature of between 250 and 500.degree. C., of between 350 and
450.degree. C. or of between 100 and 500.degree. C. Next, the
electronic device 60 is thermally pressed on the wetting layer 240b
of the flexible circuit film 42 at a force of between 20 and 150N,
and preferably of between 70 and 120N, for a time of between 0.1
and 10 seconds, and preferably of between 0.5 and 3 seconds, by the
tool head 610a kept at a temperature of between 250 and 500.degree.
C., of between 350 and 450.degree. C. or of between 100 and
500.degree. C., optionally applying ultrasonic waves to the metal
bumps 62 and to the wetting layer 240b of the flexible circuit film
42, to join the above-mentioned gold layer of the metal bumps 62
with the gold layer of the wetting layer 240b. Next, the tool head
610a is removed from the electronic device 60. Next, the flexible
circuit film 42 bonded with the semiconductor chip 2 and with the
electronic device 60 is removed from the stage 600a.
[0225] Thereby, the pads 18 of the semiconductor chip 2 can be
connected to the contact points 71 and 72 of the copper traces 210
of the flexible circuit film 42 through gold joints formed by
joining the above-mentioned gold layer of the metal bumps 12 with
the gold layer of the wetting layer 240b. The specification of the
metal bumps 12, between the semiconductor chip 2 and the copper
traces 210, formed in the process as illustrated in the second case
shown in FIGS. 8B and 8C can be referred to as the specification of
the metal bumps 12, between the semiconductor chip 2 and the copper
traces 210, formed in the process as illustrated in the second case
shown in FIG. 3B.
[0226] The electronic device 60 can be connected to the contact
points 73 and 74 of the copper traces 210 of the flexible circuit
film 42 through gold joints formed by joining the above-mentioned
gold layer of the metal bumps 62 with the gold layer of the wetting
layer 240b. For example, the metal bumps 62 between the electronic
device 60 and the contact points 73 and 74 of the copper traces 210
may include a gold joint having a thickness of between 5 and 200
micrometers, and preferably of between 10 and 50 micrometers,
between the electronic device 60 and the contact points 73 and 74
of the copper traces 210. Alternatively, the metal bumps 62 between
the electronic device 60 and the contact points 73 and 74 of the
copper traces 210 may include a copper layer having a thickness of
between 0.5 and 45 micrometers, and preferably of between 5 and 35
micrometers, between the electronic device 60 and the contact
points 73 and 74 of the copper traces 210, a nickel layer having a
thickness of between 0.5 and 5 micrometers, and preferably of
between 1 and 3 micrometers, on the copper layer and between the
copper layer and the contact points 73 and 74 of the copper traces
210, and a gold joint having a thickness of between 0.5 and 5
micrometers, and preferably of between 1 and 3 micrometers, on the
nickel layer and between the nickel layer and the contact points 73
and 74 of the copper traces 210. Alternatively, the metal bumps 62
between between the electronic device 60 and the contact points 73
and 74 of the copper traces 210 may include a copper layer having a
thickness of between 0.5 and 45 micrometers, and preferably of
between 5 and 35 .mu.m, between the electronic device 60 and the
contact points 73 and 74 of the copper traces 210, and a gold joint
having a thickness of between 0.5 and 5 micrometers, and preferably
of between 1 and 3 micrometers, on the copper layer and between the
copper layer and the contact points 73 and 74 of the copper traces
210.
[0227] Referring to FIG. 8D, a polymer layer 260 is filled into the
gap between the semiconductor chip 2 and the flexible circuit film
42 and into the gap between the electronic device 60 and the
flexible circuit film 42, enclosing the metal bumps 12 and 62, by
dispensing a polymer on the flexible circuit film 42 close to the
semiconductor chip 2 and close to the electronic device 60, with
the polymer flowing into the gap between the semiconductor chip 2
and the flexible circuit film 42 and into the gap between the
electronic device 60 and the flexible circuit film 42, and then
curing the flowing polymer at a temperature of between 100 and
250.degree. C. The material of the polymer layer 260 may be expoxy,
polyester, polybenzoxazole or polyimide.
[0228] Referring to FIG. 8E, the flexible circuit film 42 is joined
with the substrate 300 shown in FIG. 6B by joining the wetting
layer 240c of the flexible circuit film 42 with the metal joints
410c, shown in FIG. 6B, screen printed on the metal pads 310a of
the substrate 300 in advance, wherein the metal joints 410c may be
pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy. There is no opening in the polymer layer 200
exposing the copper traces 210 to lead the copper traces 210 to be
connected to the substrate 300. The methods of bonding the flexible
circuit film 42 with the substrate 300, as shown in FIG. 8E, can be
referred to as the methods of bonding the flexible circuit film 42
with the substrate 300, as illustrated in the first and second
cases shown in FIGS. 6B and 6C.
[0229] Alternatively, the metal joints 410d can be replaced by an
anisotropic conductive film (ACF). The anisotropic conductive film
can be preformed on the metal pads 310a of the substrate 300 shown
in FIG. 3E, and then the wetting layer 240c on the copper traces
210 at the outer portion of the flexible circuit film 42 can be
pressed on the anisotropic conductive film, such that metal
particles in the anisotropic conductive film connects the wetting
layer 240c of the flexible circuit film 42 to the metal pads 310a
of the substrate 300.
[0230] Referring to FIG. 8F, after the flexible circuit film 42 is
bonded with the substrate 300, a polymer layer 350a can be filled
into the gap between the flexible circuit film 42 and the substrate
300, enclosing the metal joints 410d and the wetting layer 240c, by
dispensing a polymer on the substrate 300 close to the flexible
circuit film 42, with the polymer flowing into the gap between the
flexible circuit film 42 and the substrate 300, and then curing the
flowing polymer at a temperature of between 100 and 250.degree. C.
The material of the polymer layer 350a may be expoxy, polyester or
polyimide, and the polymer layer 350a between the flexible circuit
film 42 and the substrate 300 has a thickness t20 of between 1 and
30 micrometers.
[0231] Referring to FIG. 8G, a polymer compound 360 is formed on
the semiconductor chip 2, on the electronic device 60, on the
flexible circuit film 42 and on a peripheral region of the
substrate 300 by molding an epoxy-based polymer with carbon fillers
therein on the semiconductor chip 2, on the electronic device 60,
on the flexible circuit film 42 and on the peripheral region of the
substrate 300 at a temperature of between 130 and 250.degree. C.
Alternatively, the polymer compound 360 can be polyimide or
polyester. Preferably, the polymer compound 360 has a value of
Young's modulus less than 0.5 GPa.
[0232] Referring to FIG. 8H, after the polymer compound 360 is
formed, solder balls 502 may be formed, in a ball-grid-array
arrangement, on the metal pads 310b of the substrate 300 using a
ball placement process. The process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as shown in FIG.
8H can be referred to as the process, of forming the solder balls
502 on the metal pads 310b of the substrate 300, as illustrated in
FIGS. 6F and 6G. The specification of the solder balls 502 shown in
FIG. 8H can be referred to as the specification of the solder balls
502 illustrated in FIGS. 6F and 6G. After the solder balls 502 are
formed on the substrate 300, the substrate 300 and the polymer
compound 360 can be optionally cut into multiple units.
[0233] FIG. 8I is a perspective view showing FIG. 8H. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 42 by bonding the semiconductor chip 2 with the flexible
circuit film 42. The electronic device 60 is also can be fanned out
through the copper traces 210 of the flexible circuit film 42 by
bonding the electronic device 60 with the flexible circuit film 42,
and the electronic device 60 is connected to the semiconductor chip
2 through the copper traces 210 of the flexible circuit film 42.
The flexible circuit film 42 is bonded with the substrate 300 to
connect the fine-pitched metal bumps 12 of the semiconductor chip 2
with the circuit structure of the substrate 300, and to connect the
electronic device 60 with the circuit structure of the substrate
300. Thereby, the semiconductor chip 2 has the fine-pitched metal
bumps 12 connected to an external circuit, such as a printed
circuit board (PCB) comprising a glass fiber as a core, through the
copper traces 210 of the flexible circuit film 42 and the circuit
structure of the substrate 300, and to the electronic device 60
through the copper traces 210 of the flexible circuit film 42.
[0234] Alternatively, referring to FIGS. 8J and 8K, the step of
forming the polymer compound 360, as shown in FIG. 8G, can be
omitted, that is, the semiconductor chip 2, the electronic device
60 and the flexible circuit film 42 are uncovered by any polymer
compound. Alternatively, referring to FIG. 8L, the step of forming
the polymer layer 350a, as shown in FIG. 8F, can be omitted.
Alternatively, referring to FIG. 8M, the steps of forming the
polymer layer 350a, as shown in FIG. 8F, and of forming the polymer
compound 360, as shown in FIG. 8G, can be omitted, that is, the
semiconductor chip 2, the electronic device 60 and the flexible
circuit film 42 are uncovered by any polymer compound.
[0235] Alternatively, the solder balls 502 can be omitted, as shown
in FIG. 8G. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0236] Alternatively, the polymer compound 360 and the solder balls
502 can be omitted, as shown in FIG. 8F. The semiconductor chip 2,
the electronic device 60 and the flexible circuit film 42 are
uncovered by any polymer compound. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0237] Alternatively, the polymer layer 350a and the solder balls
502 can be omitted, as shown in FIG. 8N. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0238] Alternatively, the polymer layer 350a, the polymer compound
360 and the solder balls 502 can be omitted, as shown in FIG. 8E.
The semiconductor chip 2, the electronic device 60 and the flexible
circuit film 42 are uncovered by any polymer compound. The
substrate 300 can be optionally sawed into multiple units. After
sawing the substrate 300, the metal pads 310b of the substrate 300
can be joined with a solder, containing pure tin, a tin-silver
alloy, a tin-lead alloy or a tin-silver-copper alloy, preformed on
an external circuit or can contact with contact points of a
socket.
[0239] Referring to FIG. 8O, the above-mentioned flexible circuit
film 42 shown in FIG. 8H can be replaced by a flexible circuit film
44, that is, the semiconductor chip 2 and the electronic device 60
are bonded with the copper traces 210 at the center portion of the
flexible circuit film 44, followed by forming the polymer layer 260
on the semiconductor chip 2 and on the electronic device 60,
enclosing the metal bumps 12, the metal bumps 62 and the wetting
layer 240b, followed by performing the above-mentioned steps as
shown in FIGS. 8E-8H. The flexible circuit film 44 includes the
polymer layer 200, the polymer layer 220, the wetting layer 240b,
the wetting layer 240c and the copper traces 210 between the
polymer layers 200 and 220, wherein the polymer layers 200 and 220
uncover top and bottom sides of the copper traces 210 at the center
portion and the outer portion of the flexible circuit film 44. The
wetting layer 240b is on the copper traces 210 at the center
portion of the flexible circuit film 44, and the wetting layer 240c
is on the copper traces 210 at the outer portion of the flexible
circuit film 44. There is no opening in the polymer layer 200
exposing the copper traces 210 to lead the copper traces 210 to be
connected to the substrate 300. The metal bumps 12 of the
semiconductor chip 2 are bonded with the copper traces 210 at the
center portion of the flexible circuit film 44 through the
interface bonding layer 250, and the metal bumps 62 of the
electronic device 60 are bonded with the copper traces 210 at the
center portion of the flexible circuit film 44 through the
interface bonding layer 255.
[0240] The specification of the interface bonding layer 250 shown
in FIG. 8O can be referred to as the specification of the interface
bonding layer 250 between the metal bumps 12 and the copper traces
210 formed in the process as illustrated in the first case shown in
FIGS. 3A and 3B. The specification of the interface bonding layer
255 shown in FIG. 8O can be referred to as the specification of the
interface bonding layer 255 formed in the process as illustrated in
the first case shown in FIGS. 8A, 8B and 8C. The methods, of
bonding the metal bumps 12 of the semiconductor chip 2 and the
metal bumps 62 of the electronic device 60 with the copper traces
210 of the flexible circuit film 44, as shown in FIG. 8O can be
referred to as the methods, of bonding the metal bumps 12 of the
semiconductor chip 2 and the metal bumps 62 of the electronic
device 60 with the copper traces 210 of the flexible circuit film
42, as illustrated in the first and second cases shown in FIGS. 8B
and 8C. When the step of bonding a gold layer of the metal bumps 12
with the wetting layer 240b of a tin-containing layer is performed,
the specification of the metal bumps 12 between the semiconductor
chip 2 and the interface bonding layer 250 shown in FIG. 8O can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 8O can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B. When
the step of bonding a gold layer of the metal bumps 62 with the
wetting layer 240b of a tin-containing layer is performed, the
specification of the metal bumps 62 between the electronic device
60 and the interface bonding layer 255 shown in FIG. 8O can be
referred to as the specification of the metal bumps 62, between the
electronic device 60 and the interface bonding layer 255, formed in
the process as illustrated in the first case shown in FIGS. 8A, 8B
and 8C. Alternatively, when the step of bonding a gold layer of the
metal bumps 62 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 62 between the
electronic device 60 and the copper traces 210 shown in FIG. 8O can
be referred to as the specification of the metal bumps 62, between
the electronic device 60 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIGS. 8B and
8C.
[0241] Alternatively, the metal joints 410d shown in FIG. 8O can be
replaced by an anisotropic conductive film (ACF). The anisotropic
conductive film can be preformed on the metal pads 310a of the
substrate 300 shown in FIG. 3E, and then the wetting layer 240c on
the copper traces 210 at the outer portion of the flexible circuit
film 44 can be pressed on the anisotropic conductive film, such
that metal particles in the anisotropic conductive film connects
the wetting layer 240c of the flexible circuit film 44 to the metal
pads 310a of the substrate 300.
[0242] Alternatively, the polymer compound 360 shown in FIG. 8O can
be omitted, that is, the semiconductor chip 2, the electronic
device 60 and the flexible circuit film 44 are uncovered by any
polymer compound. Alternatively, the polymer layer 350a shown in
FIG. 8O can be omitted. Alternatively, the polymer layer 350a and
the polymer compound 360 shown in FIG. 8O can be omitted, that is,
the semiconductor chip 2, the electronic device 60 and the flexible
circuit film 44 are uncovered by any polymer compound.
[0243] Alternatively, the solder balls 502 shown in FIG. 8O can be
omitted. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0244] Alternatively, the polymer compound 360 and the solder balls
502 shown in FIG. 8O can be omitted. The semiconductor chip 2, the
electronic device 60 and the flexible circuit film 44 are uncovered
by any polymer compound. The substrate 300 can be optionally sawed
into multiple units. After sawing the substrate 300, the metal pads
310b of the substrate 300 can be joined with a solder, containing
pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
[0245] Alternatively, the polymer layer 350a and the solder balls
502 shown in FIG. 8O can be omitted. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0246] Alternatively, the polymer layer 350a, the polymer compound
360 and the solder balls 502 shown in FIG. 8O can be omitted. The
semiconductor chip 2, the electronic device 60 and the flexible
circuit film 44 are uncovered by any polymer compound. The
substrate 300 can be optionally sawed into multiple units. After
sawing the substrate 300, the metal pads 310b of the substrate 300
can be joined with a solder, containing pure tin, a tin-silver
alloy, a tin-lead alloy or a tin-silver-copper alloy, preformed on
an external circuit or can contact with contact points of a
socket.
[0247] Referring to FIGS. 8P and 8Q, the above-mentioned flexible
circuit film 42 shown in FIG. 8H can be replaced by a flexible
circuit film 46, and the substrate 300 shown in FIG. 8H can be
replaced by the substrate 300a shown in FIG. 7B, that is, the
semiconductor chip 2 and the electronic device 60 are bonded with
the copper traces 210 at the center portion of the flexible circuit
film 46, followed by performing the above-mentioned step as shown
in FIG. 8D, followed by joining the flexible circuit film 46,
bonded with the semiconductor chip 2 and with the electronic device
60, with the substrate 300a using a glue material 650, followed by
bonding wireboning wires 400, such as gold wires, having a diameter
of between 12 and 40 micrometers with a wirebondable layer 230 of
the flexible circuit film 46 and with the wirebonding pads 310c of
the substrate 300a via a wire-bonding process, followed by
performing the above-mentioned steps as shown in FIGS. 8G-8H.
[0248] The flexible circuit film 46 includes the polymer layer 200,
the polymer layer 220, the wirebondable layer 230, the wetting
layer 240b and the copper traces 210 between the polymer layers 200
and 220. The wetting layer 240b is on the copper traces 210 at the
center portion of the flexible circuit film 46, and the
wirebondable layer 230 is on the copper traces 210 at the outer
portion of the flexible circuit film 46. The wirebondable layer 230
having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.1 and 1 micrometer, may be gold, copper,
aluminum, nickel, silver, palladium or a composite of the
above-mentioned materials. For example, the wirebondable layer 230
may be a gold layer having a thickness of between 0.05 and 2
micrometers, and preferably of between 0.05 and 1 micrometer, on
the copper traces 210 at the outer portion of the flexible circuit
film 46. Alternatively, the wirebondable layer 230 may be a
palladium layer having a thickness of between 0.05 and 2
micrometers, and preferably of between 0.05 and 1 micrometer, on
the copper traces 210 at the outer portion of the flexible circuit
film 46. Alternatively, the wirebondable layer 230 may be a silver
layer having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.1 and 1 micrometer, on the copper traces
210 at the outer portion of the flexible circuit film 46.
Alternatively, the wirebondable layer 230 may be an aluminum layer
having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.1 and 1 micrometer, on the copper traces
210 at the outer portion of the flexible circuit film 46.
Alternatively, the wirebondable layer 230 comprises a nickel layer
having a thickness of between 0.05 and 1 micrometer on the copper
traces 210 at the outer portion of the flexible circuit film 46,
and a gold layer having a thickness of between 0.05 and 1
micrometer on the nickel layer. There is no opening in the polymer
layer 200 exposing the copper traces 210 to lead the copper traces
210 to be connected to the substrate 300a. The metal bumps 12 of
the semiconductor chip 2 are bonded with the copper traces 210 at
the center portion of the flexible circuit film 46 through the
interface bonding layer 250, and the metal bumps 62 of the
electronic device 60 are bonded with the copper traces 210 at the
center portion of the flexible circuit film 46 through the
interface bonding layer 255.
[0249] The specification of the substrate 300a shown in FIG. 8P can
be referred to as the specification of the substrate 300a
illustrated in FIG. 7B. The specification of the interface bonding
layer 250 shown in FIG. 8P can be referred to as the specification
of the interface bonding layer 250 between the metal bumps 12 and
the copper traces 210 formed in the process as illustrated in the
first case shown in FIGS. 3A and 3B. The specification of the
interface bonding layer 255 shown in FIG. 8P can be referred to as
the specification of the interface bonding layer 255 formed in the
process as illustrated in the first case shown in FIGS. 8A, 8B and
8C. The specification of the glue material 650 shown in FIG. 8P can
be referred to as the specification of the glue material 650
illustrated in FIGS. 7B and 7C. The process, of forming the glue
material 650, as shown in FIG. 8P can be referred to as the
process, of forming the glue material 650, as illustrated in FIGS.
7B and 7C. The methods, of bonding the metal bumps 12 of the
semiconductor chip 2 and the metal bumps 62 of the electronic
device 60 with the copper traces 210 of the flexible circuit film
46, as shown in FIG. 8P can be referred to as the methods, of
bonding the metal bumps 12 of the semiconductor chip 2 and the
metal bumps 62 of the electronic device 60 with the copper traces
210 of the flexible circuit film 42, as illustrated in the first
and second cases shown in FIGS. 8B and 8C. When the step of bonding
a gold layer of the metal bumps 12 with the wetting layer 240b of a
tin-containing layer is performed, the specification of the metal
bumps 12 between the semiconductor chip 2 and the interface bonding
layer 250 shown in FIG. 8P can be referred to as the specification
of the metal bumps 12, between the semiconductor chip 2 and the
interface bonding layer 250, formed in the process as illustrated
in the first case shown in FIGS. 3A and 3B. Alternatively, when the
step of bonding a gold layer of the metal bumps 12 with the wetting
layer 240b of a gold layer is performed, the specification of the
metal bumps 12 between the semiconductor chip 2 and the copper
traces 210 shown in FIG. 8P can be referred to as the specification
of the metal bumps 12, between the semiconductor chip 2 and the
copper traces 210, formed in the process as illustrated in the
second case shown in FIG. 3B. When the step of bonding a gold layer
of the metal bumps 62 with the wetting layer 240b of a
tin-containing layer is performed, the specification of the metal
bumps 62 between the electronic device 60 and the interface bonding
layer 255 shown in FIG. 8P can be referred to as the specification
of the metal bumps 62, between the electronic device 60 and the
interface bonding layer 255, formed in the process as illustrated
in the first case shown in FIGS. 8A, 8B and 8C. Alternatively, when
the step of bonding a gold layer of the metal bumps 62 with the
wetting layer 240b of a gold layer is performed, the specification
of the metal bumps 62 between the electronic device 60 and the
copper traces 210 shown in FIG. 8P can be referred to as the
specification of the metal bumps 62, between the electronic device
60 and the copper traces 210, formed in the process as illustrated
in the second case shown in FIGS. 8B and 8C.
[0250] Alternatively, the solder balls 502 shown in FIGS. 8P and 8Q
can be omitted. The substrate 300a can be optionally sawed into
multiple units. After sawing the substrate 300a, the metal pads
310b of the substrate 300a can be joined with a solder, containing
pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
[0251] Referring to FIG. 8R, the above-mentioned flexible circuit
film 42 shown in FIG. 8H can be replaced by a flexible circuit film
48, and the substrate 300 shown in FIG. 8H can be replaced by the
substrate 300a shown in FIG. 7B, that is, the semiconductor chip 2
and the electronic device 60 are bonded with the copper traces 210
at the center portion of the flexible circuit film 48, followed by
forming the polymer layer 260 on the semiconductor chip 2 and on
the electronic device 60, enclosing the metal bumps 12, the metal
bumps 62 and the wetting layer 240b, followed by joining the
flexible circuit film 48, bonded with the semiconductor chip 2 and
with the electronic device 60, with the substrate 300a using the
glue material 650, followed by bonding the wireboning wires 400,
such as gold wires, having a diameter of between 12 and 40
micrometers with the wirebondable layer 230 of the flexible circuit
film 48 and with the wirebonding pads 310c of the substrate 300a
via a wire-bonding process, followed by performing the
above-mentioned steps as shown in FIGS. 8G-8H.
[0252] The flexible circuit film 48 includes the polymer layer 200,
the polymer layer 220, the wirebondable layer 230, the wetting
layer 240b and the copper traces 210 between the polymer layers 200
and 220, wherein the polymer layers 200 and 220 uncover top and
bottom sides of the copper traces 210 at the center portion of the
flexible circuit film 48. The wetting layer 240b is on the copper
traces 210 at the center portion of the flexible circuit film 48,
and the wirebondable layer 230 is on the copper traces 210 at the
outer portion of the flexible circuit film 48. There is no opening
in the polymer layer 200 exposing the copper traces 210 to lead the
copper traces 210 to be connected to the substrate 300a. The metal
bumps 12 of the semiconductor chip 2 are bonded with the copper
traces 210 at the center portion of the flexible circuit film 48
through the interface bonding layer 250, and the metal bumps 62 of
the electronic device 60 are bonded with the copper traces 210 at
the center portion of the flexible circuit film 48 through the
interface bonding layer 255.
[0253] The specification of the substrate 300a shown in FIG. 8R can
be referred to as the specification of the substrate 300a
illustrated in FIG. 7B. The specification of the wirebondable layer
230 shown in FIG. 8R can be referred to as the specification of the
wirebondable layer 230 illustrated in FIGS. 8P and 8Q. The
specification of the interface bonding layer 250 shown in FIG. 8R
can be referred to as the specification of the interface bonding
layer 250 between the metal bumps 12 and the copper traces 210
formed in the process as illustrated in the first case shown in
FIGS. 3A and 3B. The specification of the interface bonding layer
255 shown in FIG. 8R can be referred to as the specification of the
interface bonding layer 255 formed in the process as illustrated in
the first case shown in FIGS. 8A, 8B and 8C. The specification of
the glue material 650 shown in FIG. 8R can be referred to as the
specification of the glue material 650 illustrated in FIGS. 7B and
7C. The process, of forming the glue material 650, as shown in FIG.
8R can be referred to as the process, of forming the glue material
650, as illustrated in FIGS. 7B and 7C. The methods, of bonding the
metal bumps 12 of the semiconductor chip 2 and the metal bumps 62
of the electronic device 60 with the copper traces 210 of the
flexible circuit film 48, as shown in FIG. 8R can be referred to as
the methods, of bonding the metal bumps 12 of the semiconductor
chip 2 and the metal bumps 62 of the electronic device 60 with the
copper traces 210 of the flexible circuit film 42, as illustrated
in the first and second cases shown in FIGS. 8B and 8C. When the
step of bonding a gold layer of the metal bumps 12 with the wetting
layer 240b of a tin-containing layer is performed, the
specification of the metal bumps 12 between the semiconductor chip
2 and the interface bonding layer 250 shown in FIG. 8R can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 8R can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B. When
the step of bonding a gold layer of the metal bumps 62 with the
wetting layer 240b of a tin-containing layer is performed, the
specification of the metal bumps 62 between the electronic device
60 and the interface bonding layer 255 shown in FIG. 8R can be
referred to as the specification of the metal bumps 62, between the
electronic device 60 and the interface bonding layer 255, formed in
the process as illustrated in the first case shown in FIGS. 8A, 8B
and 8C. Alternatively, when the step of bonding a gold layer of the
metal bumps 62 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 62 between the
electronic device 60 and the copper traces 210 shown in FIG. 8R can
be referred to as the specification of the metal bumps 62, between
the electronic device 60 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIGS. 8B and
8C.
[0254] Alternatively, the solder balls 502 shown in FIG. 8R can be
omitted. The substrate 300a can be optionally sawed into multiple
units. After sawing the substrate 300a, the metal pads 310b of the
substrate 300a can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0255] Referring to FIG. 8S, the above-mentioned flexible circuit
film 42 shown in FIG. 8H can be replaced by a flexible circuit film
36, that is, the semiconductor chip 2 and the electronic device 60
are bonded with the copper traces 210 at the center portion of the
flexible circuit film 36, followed by performing the
above-mentioned step as shown in FIG. 8D, followed by joining the
copper traces 210 with tin-containing joints preformed on the metal
pads 310a of the substrate 300 to provide metal joints 410b, such
as tin-containing joints, between the copper traces 210 of the
flexible circuit film 36 and the topmost copper traces 340a of the
substrate 300, followed by filling a polymer layer 350 into the gap
between the flexible circuit film 36 and the substrate 300,
enclosing the metal joints 410b, followed by performing the
above-mentioned steps as shown in FIGS. 8G-8H.
[0256] The flexible circuit film 36 includes the polymer layer 200,
the polymer layer 220, the wetting layer 240a, the wetting layer
240b and the copper traces 210 between the polymer layers 200 and
220. The wetting layer 240b is on the copper traces 210 at the
center portion of the flexible circuit film 36, and the wetting
layer 240a is on the copper traces 210 at the outer portion of the
flexible circuit film 36. The wetting layer 240a having a thickness
of between 0.05 and 5 micrometers, and preferably of between 0.1
and 1 micrometer, may be gold, copper, nickel, silver, tin or a
composite of the above-mentioned materials. For example, the
wetting layer 240a may be a tin-containing layer, such as pure tin,
a tin-silver alloy, a tin-silver-copper alloy or a tin-lead alloy,
having a thickness of between 0.05 and 5 micrometers, and
preferably of between 0.1 and 1 micrometer, directly on the copper
traces 210 at the outer portion of the flexible circuit film 36.
Alternatively, the wetting layer 240a may be a gold layer having a
thickness of between 0.05 and 5 micrometers, and preferably of
between 0.1 and 1 micrometer, directly on the copper traces 210 at
the outer portion of the flexible circuit film 36; optionally, a
nickel layer having a thickness between 0.05 and 1 micrometer may
be between the copper traces 210 and the gold layer. The metal
bumps 12 of the semiconductor chip 2 are bonded with the copper
traces 210 at the center portion of the flexible circuit film 36
through the interface bonding layer 250, and the metal bumps 62 of
the electronic device 60 are bonded with the copper traces 210 at
the center portion of the flexible circuit film 36 through the
interface bonding layer 255.
[0257] The specification of the interface bonding layer 250 shown
in FIG. 8S can be referred to as the specification of the interface
bonding layer 250 between the metal bumps 12 and the copper traces
210 formed in the process as illustrated in the first case shown in
FIGS. 3A and 3B. The specification of the interface bonding layer
255 shown in FIG. 8S can be referred to as the specification of the
interface bonding layer 255 formed in the process as illustrated in
the first case shown in FIGS. 8A, 8B and 8C. The specification of
the metal joints 410b shown in FIG. 8S can be referred to as the
specification of the metal joints 410b formed in the process as
illustrated in the first and second cases shown in FIGS. 3F and 3G.
The specification of the polymer layer 350 shown in FIG. 8S can be
referred to as the specification of the polymer layer 350
illustrated in FIG. 3H. The process, of forming the polymer layer
350, as shown in FIG. 8S can be referred to as the process, of
forming the polymer layer 350, as illustrated in FIG. 3H. The
methods, of joining the flexible circuit film 36 with the
tin-containing joints preformed on the metal pads 310a of the
substrate 300, as shown in FIG. 8S can be referred to as the
methods, of joining the flexible circuit film 36 with the
tin-containing joints 410a preformed on the metal pads 310a of the
substrate 300, as illustrated in the first and second cases shown
in FIGS. 3F and 3G. The methods, of bonding the metal bumps 12 of
the semiconductor chip 2 and the metal bumps 62 of the electronic
device 60 with the copper traces 210 of the flexible circuit film
36, as shown in FIG. 8S can be referred to as the methods, of
bonding the metal bumps 12 of the semiconductor chip 2 and the
metal bumps 62 of the electronic device 60 with the copper traces
210 of the flexible circuit film 42, as illustrated in the first
and second cases shown in FIGS. 8B and 8C. When the step of bonding
a gold layer of the metal bumps 12 with the wetting layer 240b of a
tin-containing layer is performed, the specification of the metal
bumps 12 between the semiconductor chip 2 and the interface bonding
layer 250 shown in FIG. 8S can be referred to as the specification
of the metal bumps 12, between the semiconductor chip 2 and the
interface bonding layer 250, formed in the process as illustrated
in the first case shown in FIGS. 3A and 3B. Alternatively, when the
step of bonding a gold layer of the metal bumps 12 with the wetting
layer 240b of a gold layer is performed, the specification of the
metal bumps 12 between the semiconductor chip 2 and the copper
traces 210 shown in FIG. 8S can be referred to as the specification
of the metal bumps 12, between the semiconductor chip 2 and the
copper traces 210, formed in the process as illustrated in the
second case shown in FIG. 3B. When the step of bonding a gold layer
of the metal bumps 62 with the wetting layer 240b of a
tin-containing layer is performed, the specification of the metal
bumps 62 between the electronic device 60 and the interface bonding
layer 255 shown in FIG. 8S can be referred to as the specification
of the metal bumps 62, between the electronic device 60 and the
interface bonding layer 255, formed in the process as illustrated
in the first case shown in FIGS. 8A, 8B and 8C. Alternatively, when
the step of bonding a gold layer of the metal bumps 62 with the
wetting layer 240b of a gold layer is performed, the specification
of the metal bumps 62 between the electronic device 60 and the
copper traces 210 shown in FIG. 8S can be referred to as the
specification of the metal bumps 62, between the electronic device
60 and the copper traces 210, formed in the process as illustrated
in the second case shown in FIGS. 8B and 8C.
[0258] Alternatively, the polymer compound 360 shown in FIG. 8S can
be omitted, that is, the semiconductor chip 2, the electronic
device 60 and the flexible circuit film 36 are uncovered by any
polymer compound. Alternatively, the polymer layer 350 shown in
FIG. 8S can be omitted. Alternatively, the polymer layer 350 and
the polymer compound 360 shown in FIG. 8S can be omitted, that is,
the semiconductor chip 2, the electronic device 60 and the flexible
circuit film 36 are uncovered by any polymer compound.
[0259] Alternatively, the solder balls 502 shown in FIG. 8S can be
omitted. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0260] Alternatively, the polymer compound 360 and the solder balls
502 shown in FIG. 8S can be omitted. The semiconductor chip 2, the
electronic device 60 and the flexible circuit film 36 are uncovered
by any polymer compound. The substrate 300 can be optionally sawed
into multiple units. After sawing the substrate 300, the metal pads
310b of the substrate 300 can be joined with a solder, containing
pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
[0261] Alternatively, the polymer layer 350 and the solder balls
502 shown in FIG. 8S can be omitted. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0262] Alternatively, the polymer layer 350, the polymer compound
360 and the solder balls 502 shown in FIG. 8S can be omitted. The
semiconductor chip 2, the electronic device 60 and the flexible
circuit film 36 are uncovered by any polymer compound. The
substrate 300 can be optionally sawed into multiple units. After
sawing the substrate 300, the metal pads 310b of the substrate 300
can be joined with a solder, containing pure tin, a tin-silver
alloy, a tin-lead alloy or a tin-silver-copper alloy, preformed on
an external circuit or can contact with contact points of a
socket.
[0263] Referring to FIG. 8T, the above-mentioned flexible circuit
film 42 shown in FIG. 8H can be replaced by a flexible circuit film
38, that is, the semiconductor chip 2 and the electronic device 60
are bonded with the copper traces 210 at the center portion of the
flexible circuit film 38, followed by forming the polymer layer 260
on the semiconductor chip 2 and on the electronic device 60,
enclosing the metal bumps 12, the metal bumps 62 and the wetting
layer 240b, followed by joining the copper traces 210 with
tin-containing joints preformed on the metal pads 310a of the
substrate 300 to provide the metal joints 410b, such as
tin-containing joints, between the copper traces 210 of the
flexible circuit film 38 and the topmost copper traces 340a of the
substrate 300, followed by filling the polymer layer 350 into the
gap between the flexible circuit film 38 and the substrate 300,
enclosing the metal joints 410b, followed by performing the
above-mentioned steps as shown in FIGS. 8G-8H.
[0264] The flexible circuit film 38 includes the polymer layer 200,
the polymer layer 220, the wetting layer 240a, the wetting layer
240b and the copper traces 210 between the polymer layers 200 and
220. The wetting layer 240b is on the copper traces 210 at the
center portion of the flexible circuit film 38, and the wetting
layer 240a is on the copper traces 210 at the outer portion of the
flexible circuit film 38. The metal bumps 12 of the semiconductor
chip 2 are bonded with the copper traces 210 at the center portion
of the flexible circuit film 38 through the interface bonding layer
250, and the metal bumps 62 of the electronic device 60 are bonded
with the copper traces 210 at the center portion of the flexible
circuit film 38 through the interface bonding layer 255. The
specification of the wetting layer 240a shown in FIG. 8T can be
referred to as the specification of the wetting layer 240a
illustrated in FIG. 8S.
[0265] The specification of the interface bonding layer 250 shown
in FIG. 8T can be referred to as the specification of the interface
bonding layer 250 between the metal bumps 12 and the copper traces
210 formed in the process as illustrated in the first case shown in
FIGS. 3A and 3B. The specification of the interface bonding layer
255 shown in FIG. 8T can be referred to as the specification of the
interface bonding layer 255 formed in the process as illustrated in
the first case shown in FIGS. 8A, 8B and 8C. The specification of
the metal joints 410b shown in FIG. 8T can be referred to as the
specification of the metal joints 410b formed in the process as
illustrated in the first and second cases shown in FIGS. 3F and 3G.
The specification of the polymer layer 350 shown in FIG. 8T can be
referred to as the specification of the polymer layer 350
illustrated in FIG. 3H. The process, of forming the polymer layer
350, as shown in FIG. 8T can be referred to as the process, of
forming the polymer layer 350, as illustrated in FIG. 3H. The
methods, of joining the flexible circuit film 38 with the
tin-containing joints preformed on the metal pads 310a of the
substrate 300, as shown in FIG. 8S can be referred to as the
methods, of joining the flexible circuit film 38 with the
tin-containing joints 410a preformed on the metal pads 310a of the
substrate 300, as illustrated in the first and second cases shown
in FIGS. 3F and 3G. The methods, of bonding the metal bumps 12 of
the semiconductor chip 2 and the metal bumps 62 of the electronic
device 60 with the copper traces 210 of the flexible circuit film
38, as shown in FIG. 8T can be referred to as the methods, of
bonding the metal bumps 12 of the semiconductor chip 2 and the
metal bumps 62 of the electronic device 60 with the copper traces
210 of the flexible circuit film 42, as illustrated in the first
and second cases shown in FIGS. 8B and 8C. When the step of bonding
a gold layer of the metal bumps 12 with the wetting layer 240b of a
tin-containing layer is performed, the specification of the metal
bumps 12 between the semiconductor chip 2 and the interface bonding
layer 250 shown in FIG. 8T can be referred to as the specification
of the metal bumps 12, between the semiconductor chip 2 and the
interface bonding layer 250, formed in the process as illustrated
in the first case shown in FIGS. 3A and 3B. Alternatively, when the
step of bonding a gold layer of the metal bumps 12 with the wetting
layer 240b of a gold layer is performed, the specification of the
metal bumps 12 between the semiconductor chip 2 and the copper
traces 210 shown in FIG. 8T can be referred to as the specification
of the metal bumps 12, between the semiconductor chip 2 and the
copper traces 210, formed in the process as illustrated in the
second case shown in FIG. 3B. When the step of bonding a gold layer
of the metal bumps 62 with the wetting layer 240b of a
tin-containing layer is performed, the specification of the metal
bumps 62 between the electronic device 60 and the interface bonding
layer 255 shown in FIG. 8T can be referred to as the specification
of the metal bumps 62, between the electronic device 60 and the
interface bonding layer 255, formed in the process as illustrated
in the first case shown in FIGS. 8A, 8B and 8C. Alternatively, when
the step of bonding a gold layer of the metal bumps 62 with the
wetting layer 240b of a gold layer is performed, the specification
of the metal bumps 62 between the electronic device 60 and the
copper traces 210 shown in FIG. 8T can be referred to as the
specification of the metal bumps 62, between the electronic device
60 and the copper traces 210, formed in the process as illustrated
in the second case shown in FIGS. 8B and 8C.
[0266] Alternatively, the polymer compound 360 shown in FIG. 8T can
be omitted, that is, the semiconductor chip 2, the electronic
device 60 and the flexible circuit film 38 are uncovered by any
polymer compound. Alternatively, the polymer layer 350 shown in
FIG. 8T can be omitted. Alternatively, the polymer layer 350 and
the polymer compound 360 shown in FIG. 8T can be omitted, that is,
the semiconductor chip 2, the electronic device 60 and the flexible
circuit film 38 are uncovered by any polymer compound.
[0267] Alternatively, the solder balls 502 shown in FIG. 8T can be
omitted. The substrate 300 can be optionally sawed into multiple
units. After sawing the substrate 300, the metal pads 310b of the
substrate 300 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0268] Alternatively, the polymer compound 360 and the solder balls
502 shown in FIG. 8T can be omitted. The semiconductor chip 2, the
electronic device 60 and the flexible circuit film 38 are uncovered
by any polymer compound. The substrate 300 can be optionally sawed
into multiple units. After sawing the substrate 300, the metal pads
310b of the substrate 300 can be joined with a solder, containing
pure tin, a tin-silver alloy, a tin-lead alloy or a
tin-silver-copper alloy, preformed on an external circuit or can
contact with contact points of a socket.
[0269] Alternatively, the polymer layer 350 and the solder balls
502 shown in FIG. 8T can be omitted. The substrate 300 can be
optionally sawed into multiple units. After sawing the substrate
300, the metal pads 310b of the substrate 300 can be joined with a
solder, containing pure tin, a tin-silver alloy, a tin-lead alloy
or a tin-silver-copper alloy, preformed on an external circuit or
can contact with contact points of a socket.
[0270] Alternatively, the polymer layer 350, the polymer compound
360 and the solder balls 502 shown in FIG. 8T can be omitted. The
semiconductor chip 2, the electronic device 60 and the flexible
circuit film 38 are uncovered by any polymer compound. The
substrate 300 can be optionally sawed into multiple units. After
sawing the substrate 300, the metal pads 310b of the substrate 300
can be joined with a solder, containing pure tin, a tin-silver
alloy, a tin-lead alloy or a tin-silver-copper alloy, preformed on
an external circuit or can contact with contact points of a
socket.
Embodiment 6
[0271] Referring to FIG. 9A, a lead frame 700 comprises multiple
leads 701 and a die pad 702 surrounded by the leads 701. Both the
leads 701 and the die pad 702 are made of copper or a copper alloy.
A wetting layer 510 is formed on the leads 701, and the wetting
layer 510 may be a gold layer or a tin-containing layer, such as
pure tin, a tin-silver alloy, a tin-silver-copper alloy or a
tin-lead alloy.
[0272] The methods, of bonding the metal bumps 12 of the
semiconductor chip 2 with the copper traces 210 of the flexible
circuit film 42, as shown in FIG. 9A can be referred to as the
methods, of bonding the metal bumps 12 of the semiconductor chip 2
with the copper traces 210 of the flexible circuit film 36, as
illustrated in the first and second cases shown in FIGS. 3B and 3C.
When the step of bonding a gold layer of the metal bumps 12 with
the wetting layer 240b of a tin-containing layer is performed, the
specification of the metal bumps 12 between the semiconductor chip
2 and the interface bonding layer 250 shown in FIG. 9A can be
referred to as the specification of the metal bumps 12, between the
semiconductor chip 2 and the interface bonding layer 250, formed in
the process as illustrated in the first case shown in FIGS. 3A and
3B. Alternatively, when the step of bonding a gold layer of the
metal bumps 12 with the wetting layer 240b of a gold layer is
performed, the specification of the metal bumps 12 between the
semiconductor chip 2 and the copper traces 210 shown in FIG. 9A can
be referred to as the specification of the metal bumps 12, between
the semiconductor chip 2 and the copper traces 210, formed in the
process as illustrated in the second case shown in FIG. 3B.
[0273] Referring to FIGS. 9A and 9B, a glue material 650 is first
formed on the die pad 702 of the lead frame 700 by a dispensing
process after the semiconductor chip 2 is bonded with the
above-mentioned flexible circuit film 42 shown in FIG. 6B. Next,
the polymer layer 200 of the flexible circuit film 42 adheres onto
the glue material 650, and then the glue material 650 is baked at a
temperature of between 100 and 200.degree. C. and to a thickness
t23 between 5 and 30 micrometers if the glue material 650 is an
epoxy. Alternatively, the glue material 650 can be polyimide or
polyester. Thereby, the flexible circuit film 42 can be joined with
the die pad 702. In another word, the flexible circuit film 42
bonded with the semiconductor chip 2 can be joined with the die pad
702 using the glue material 650.
[0274] Referring to FIG. 9C, after the flexible circuit film 42 is
joined with the die pad 702, the copper traces 210 at the outer
portion of the flexible circuit film 42 are bonded with the leads
701 of the lead frame 700. Four methods of bonding the copper
traces 210 at the outer portion of the flexible circuit film 42
with the leads 701 of the lead frame 700 are described as
follow.
[0275] In a first case, referring to FIGS. 9B and 9C, when the
wetting layer 510 is a gold layer, the wetting layer 510 can be
used to be joined with the wetting layer 240c of pure tin or an
above-mentioned tin alloy using a heat press process, which method
is described as below. First, the lead frame 700 joined with the
flexible circuit film 42 using the glue material 650 is placed on a
stage kept at a temperature of between 150 and 350.degree. C., and
preferably of between 200 and 300.degree. C. Next, the wetting
layer 240c of the flexible circuit film 42 is thermally pressed on
the wetting layer 510 on the leads 701 of the lead frame 700 at a
force of between 20 and 150N, and preferably of between 50 and 90N,
for a time of between 0.1 and 10 seconds, and preferably of between
0.5 and 3 seconds, by a tool head kept at a temperature of between
250 and 500.degree. C., and preferably of between 350 and
450.degree. C., to join the wetting layer 240c with the wetting
layer 510. In the step of joining the wetting layer 240c with the
wetting layer 510, metal joints 512 can be formed between the leads
701 of the lead frame 700 and the copper traces 210 at the outer
portion of the flexible circuit film 42. The metal joints 512 can
be tin-containing joints having a thickness t24 of between 0.1 and
10 micrometers, and preferably of between 0.2 and 2 micrometers,
wherein the tin-containing joints may include a tin-gold alloy, a
tin-silver-gold alloy, a tin-silver-gold-copper alloy or a
tin-lead-gold alloy due to the reaction between tin in the wetting
layer 240c and gold in the wetting layer 510. Next, the tool head
is removed from the flexible circuit film 42. Next, the lead frame
700 bonded with the flexible circuit film 42 is removed from the
stage.
[0276] In a second case, referring to FIGS. 9B and 9C, when the
wetting layer 510 is a tin-containing layer, the wetting layer 510
can be used to be joined with a gold layer of the wetting layer
240c using a heat press process, which method is described as
below. First, the lead frame 700 joined with the flexible circuit
film 42 using the glue material 650 is placed on a stage kept at a
temperature of between 150 and 350.degree. C., and preferably of
between 200 and 300.degree. C. Next, the wetting layer 240c of the
flexible circuit film 42 is thermally pressed on the wetting layer
510 on the leads 701 of the lead frame 700 at a force of between 20
and 150N, and preferably of between 50 and 90N, for a time of
between 0.1 and 10 seconds, and preferably of between 0.5 and 3
seconds, by a tool head kept at a temperature of between 250 and
500.degree. C., and preferably of between 350 and 450.degree. C.,
to join the wetting layer 240c with the wetting layer 510. In the
step of joining the wetting layer 240c with the wetting layer 510,
the metal joints 512 can be formed between the leads 701 of the
lead frame 700 and the copper traces 210 at the outer portion of
the flexible circuit film 42. The metal joints 512 can be
tin-containing joints having a thickness t24 of between 0.1 and 10
micrometers, and preferably of between 0.2 and 2 micrometers,
wherein the tin-containing joints may include a tin-gold alloy, a
tin-silver-gold alloy, a tin-silver-gold-copper alloy or a
tin-lead-gold alloy due to the reaction between gold in the wetting
layer 240c and tin in the wetting layer 510. Next, the tool head is
removed from the flexible circuit film 42. Next, the lead frame 700
bonded with the flexible circuit film 42 is removed from the
stage.
[0277] In a third case, referring to FIGS. 9B and 9C, when the
wetting layer 510 is a tin-containing layer, the wetting layer 510
can be used to be joined with the wetting layer 240c of pure tin or
an above-mentioned tin alloy using a heat press process, which
method is described as below. First, the lead frame 700 joined with
the flexible circuit film 42 using the glue material 650 is placed
on a stage kept at a temperature of between 150 and 350.degree. C.,
and preferably of between 200 and 300.degree. C. Next, the wetting
layer 240c of the flexible circuit film 42 is thermally pressed on
the wetting layer 510 on the leads 701 of the lead frame 700 at a
force of between 20 and 150N, and preferably of between 50 and 90N,
for a time of between 0.1 and 10 seconds, and preferably of between
0.5 and 3 seconds, by a tool head kept at a temperature of between
250 and 500.degree. C., and preferably of between 350 and
450.degree. C., to join the wetting layer 240c with the wetting
layer 510. Next, the tool head is removed from the flexible circuit
film 42. Next, the lead frame 700 bonded with the flexible circuit
film 42 is removed from the stage. Thereby, the leads 701 of the
lead frame 700 can be connected to the copper traces 210 of the
flexible circuit film 42 through tin-containing joints formed by
joining the tin-containing layer of the wetting layer 240b with the
tin-containing layer of the wetting layer 510, wherein the
tin-containing joints may include pure tin, a tin-silver alloy, a
tin-silver-copper alloy or a tin-lead alloy.
[0278] In a fourth case, referring to FIGS. 9B and 9C, when the
wetting layer 510 is a gold layer, the metal joints 510 can be used
to be joined with a gold layer of the wetting layer 240c using a
heat press process, which method is described as below. First, the
lead frame 700 joined with the flexible circuit film 42 using the
glue material 650 is placed on a stage kept at a temperature of
between 150 and 350.degree. C., and preferably of between 200 and
300.degree. C. Next, the wetting layer 240c of the flexible circuit
film 42 is thermally pressed on the wetting layer 510 on the leads
701 of the lead frame 700 at a force of between 20 and 150N, and
preferably of between 70 and 120N, for a time of between 0.1 and 10
seconds, and preferably of between 0.5 and 3 seconds, by a tool
head kept at a temperature of between 250 and 500.degree. C., and
preferably of between 350 and 450.degree. C., to join the wetting
layer 240c with the wetting layer 510. Next, the tool head is
removed from the flexible circuit film 42. Next, the lead frame 700
bonded with the flexible circuit film 42 is removed from the stage.
Thereby, the leads 701 of the lead frame 700 can be connected to
the copper traces 210 of the flexible circuit film 42 through gold
joints formed by joining the gold layer of the wetting layer 240b
with the gold layer of the wetting layer 510.
[0279] Referring to FIG. 9D, after the step shown in FIG. 9C, a
polymer compound 370 is formed using a molding process, enclosing
the die pad 702, an inner portion of the leads 701 close to the die
pad 702, the semiconductor chip 2 and the flexible circuit film 42.
For example, the polymer compound 370 can be formed by molding an
epoxy-based polymer with carbon fillers therein enclosing the die
pad 702, the inner portion of the leads 701, the semiconductor chip
2 and the flexible circuit film 42 at a temperature of between 130
and 250.degree. C. Alternatively, the polymer compound 370 can be
polyimide or polyester. Preferably, the polymer compound 370 has a
value of Young's modulus less than 0.5 GPa.
[0280] Referring to FIG. 9E, after the polymer compound 370 is
formed, a wetting layer 515, such as gold, pure tin, a tin-silver
alloy, a tin-silver-copper alloy or a tin-lead alloy, can be
electroplated or electroless plated on an outer portion of the
leads 701 unenclosed by the polymer compound 370.
[0281] Referring to FIG. 9F, after the wetting layer 515 is formed,
the steps of dejunking the residual of the polymer compound 370,
trimming dam bars and cutting and punching the leads 701 can be
performed, such that the leads 701 have a predetermined shape and
multiple chip packages are singularized.
[0282] FIG. 9G is a perspective view showing FIG. 9F. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 42 by bonding the semiconductor chip 2 with the flexible
circuit film 42. The flexible circuit film 42 is also joined with
the lead frame 700, and the flexible circuit film 42 can be
connected to the lead frame 700. Thereby, the semiconductor chip 2
has the fine-pitched metal bumps 12 connected to an external
circuit, such as a printed circuit board (PCB) comprising a glass
fiber as a core, through the copper traces 210 of the flexible
circuit film 42 and through the leads 701 of the lead frame 700.
Alternatively, the glue material 650 shown in FIGS. 9A-9F can be
omitted.
[0283] Referring to FIG. 9H, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS. 9A-9G
can be replaced by the above-mentioned flexible circuit film 44,
bonded with the semiconductor chip 2, shown in FIG. 6O, that is,
the flexible circuit film 44 bonded with the semiconductor chip 2
is joined with the lead frame 700 using the glue material 650,
followed by performing the above-mentioned steps as shown in FIGS.
9C-9F. The method, of joining the flexible circuit film 44 bonded
with the semiconductor chip 2 with the lead frame 700 using the
glue material 650, as shown in FIG. 9H can be referred to as the
method, of joining the flexible circuit film 42 bonded with the
semiconductor chip 2 with the lead frame 700 using the glue
material 650, as illustrated in FIGS. 9A and 9B.
[0284] Referring to FIGS. 9I and 9J, the above-mentioned flexible
circuit film 42, bonded with the semiconductor chip 2, shown in
FIGS. 9A-9G can be replaced by the above-mentioned flexible circuit
film 46, bonded with the semiconductor chip 2, shown in FIG. 7B,
that is, the flexible circuit film 46 bonded with the semiconductor
chip 2 is joined with the lead frame 700 using the glue material
650, followed by bonding wireboning wires 400, such as gold wires,
having a diameter of between 12 and 40 micrometers with the
wirebondable layer 230 and with the leads 701 via a wire-bonding
process, followed by performing the above-mentioned steps as shown
in FIGS. 9D-9F. Thereby, the wirebondable layer 230 of the flexible
circuit film 46 can be electrically connected to the leads 701 of
the lead frame 700 through the wireboning wires 400.
[0285] Referring to FIG. 9K, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS. 9A-9G
can be replaced by the above-mentioned flexible circuit film 48,
bonded with the semiconductor chip 2, shown in FIG. 7I, that is,
the flexible circuit film 48 bonded with the semiconductor chip 2
is joined with the lead frame 700 using the glue material 650,
followed by bonding the wireboning wires 400, such as gold wires,
having a diameter of between 12 and 40 micrometers with the
wirebondable layer 230 and with the leads 701 via a wire-bonding
process, followed by performing the above-mentioned steps as shown
in FIGS. 9D-9F. Thereby, the wirebondable layer 230 of the flexible
circuit film 48 can be electrically connected to the leads 701 of
the lead frame 700 through the wireboning wires 400.
[0286] Referring to FIG. 9L, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS. 9A-9G
can be replaced by the above-mentioned flexible circuit film 36,
bonded with the semiconductor chip 2, shown in FIG. 3D, that is,
the flexible circuit film 36 bonded with the semiconductor chip 2
is joined with the lead frame 700 using the glue material 650,
followed by joining the copper traces 210 with tin-containing
solder preformed on the leads 701 to provide metal joints 513, such
as tin-containing joints, between the copper traces 210 and the
leads 701, followed by performing the above-mentioned steps as
shown in FIGS. 9D-9F.
[0287] Referring to FIG. 9M, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS. 9A-9G
can be replaced by the above-mentioned flexible circuit film 38,
bonded with the semiconductor chip 2, shown in FIG. 3T, that is,
the flexible circuit film 38 bonded with the semiconductor chip 2
is joined with the lead frame 700 using the glue material 650,
followed by joining the copper traces 210 with a tin-containing
solder preformed on the leads 701 to provide the metal joints 513,
such as tin-containing joints, between the copper traces 210 and
the leads 701, followed by performing the above-mentioned steps as
shown in FIGS. 9D-9F.
[0288] Referring to FIG. 10A, after the step shown in FIG. 9C, a
polymer compound 380 is formed using a molding process, enclosing
the die pad 702, an inner portion of the leads 701 close to the die
pad 702, an outer portion of the leads 701, the semiconductor chip
2 and the flexible circuit film 42, and openings 380a in the
polymer compound 380 expose the bottom surface of the outer portion
of the leads 701. For example, the polymer compound 380 can be
formed by molding an epoxy-based polymer with carbon fillers
therein enclosing the die pad 702, the inner portion of the leads
701, the outer portion of the leads 701, the semiconductor chip 2
and the flexible circuit film 42 at a temperature of between 130
and 250.degree. C., and the openings 380a in the polymer compound
380 expose the bottom surface of the outer portion of the leads
701. Alternatively, the polymer compound 380 can be polyimide or
polyester. Preferably, the polymer compound 380 has a value of
Young's modulus less than 0.5 GPa.
[0289] Referring to FIG. 10B, after the polymer compound 380 is
formed, a wetting layer 514 can be electroplated or electroless
plated on the bottom surface of the outer portion of the leads 701
exposed by the openings 380a in the polymer compound 380. The
wetting layer 514 has a thickness of between 0.1 and 3 micrometers,
and may be gold, copper, silver, nickel, tin, aluminum, palladium
or a composite of the above-mentioned materials. For example, the
wetting layer 514 can be formed by electroless plating a nickel
layer having a thickness of between 0.05 and 1 .mu.m on the bottom
surface of the outer portion of the leads 701 exposed by the
openings 380a in the polymer compound 380, and electroless plating
a gold layer having a thickness of between 0.05 and 2 micrometers,
and preferably of between 0.05 and 0.3 micrometers, on the nickel
layer in the openings 380a. Alternatively, the wetting layer 514
can be formed by electroplating a nickel layer having a thickness
of between 0.05 and 1 .mu.m on the bottom surface of the outer
portion of the leads 701 exposed by the openings 380a in the
polymer compound 380, and electroplating a gold layer having a
thickness of between 0.05 and 2 micrometers, and preferably of
between 0.05 and 0.3 micrometers, on the nickel layer in the
openings 380a. Alternatively, the wetting layer 514 can be formed
by electroless plating a gold layer having a thickness of between
0.05 and 2 micrometers, and preferably of between 0.05 and 0.3
micrometers, on the bottom surface of the outer portion of the
leads 701 exposed by the openings 380a in the polymer compound 380.
Alternatively, the wetting layer 514 can be formed by
electroplating a gold layer having a thickness of between 0.05 and
2 micrometers, and preferably of between 0.05 and 0.3 micrometers,
on the bottom surface of the outer portion of the leads 701 exposed
by the openings 380a in the polymer compound 380. Alternatively,
the wetting layer 514 can be formed by electroless plating a
tin-containing layer, such as pure tin, a tin-silver alloy, a
tin-lead alloy or a tin-silver-copper alloy, having a thickness of
between 0.05 and 2 micrometers, and preferably of between 0.05 and
0.3 micrometers, on the bottom surface of the outer portion of the
leads 701 exposed by the openings 380a in the polymer compound 380.
Alternatively, the wetting layer 514 can be formed by
electroplating a tin-containing layer, such as pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.05 and 0.3 micrometers, on the bottom
surface of the outer portion of the leads 701 exposed by the
openings 380a in the polymer compound 380. Alternatively, the
wetting layer 514 can be formed by electroless plating an aluminum
layer having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.05 and 0.3 micrometers, on the bottom
surface of the outer portion of the leads 701 exposed by the
openings 380a in the polymer compound 380. Alternatively, the
wetting layer 514 can be formed by electroplating an aluminum layer
having a thickness of between 0.05 and 2 micrometers, and
preferably of between 0.05 and 0.3 micrometers, on the bottom
surface of the outer portion of the leads 701 exposed by the
openings 380a in the polymer compound 380.
[0290] Next, the steps of dejunking the residual of the polymer
compound 380, trimming dam bars and cutting and punching the leads
701 can be performed, such that multiple chip packages are
singularized. After singularizing the chip packages, the wetting
layer 514 can be joined with a solder, containing pure tin, a
tin-silver alloy, a tin-lead alloy or a tin-silver-copper alloy,
preformed on an external circuit or can contact with contact points
of a socket.
[0291] FIG. 10C is a perspective view showing FIG. 10B. The
fine-pitched metal bumps 12 of the semiconductor chip 2 can be
fanned out through the copper traces 210 of the flexible circuit
film 42 by bonding the semiconductor chip 2 with the flexible
circuit film 42. The flexible circuit film 42 is also joined with
the lead frame 700, and the flexible circuit film 42 can be
connected to the lead frame 700. Thereby, the semiconductor chip 2
has the fine-pitched metal bumps 12 connected to an external
circuit, such as a printed circuit board (PCB) comprising a glass
fiber as a core, through the copper traces 210 of the flexible
circuit film 42 and through the leads 701 of the lead frame
700.
[0292] Referring to FIG. 10D, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS.
10A-10B can be replaced by the above-mentioned flexible circuit
film 44, bonded with the semiconductor chip 2, shown in FIG. 6O,
that is, the flexible circuit film 44 bonded with the semiconductor
chip 2 is joined with the lead frame 700 using the glue material
650, followed by performing the above-mentioned steps as shown in
FIG. 9C, followed by performing the above-mentioned steps as shown
in FIG. 10A-10B. The methods, of joining the flexible circuit film
44 bonded with the semiconductor chip 2 with the lead frame 700
using the glue material 650, as shown in FIG. 10D can be referred
to as the methods, of joining the flexible circuit film 42 bonded
with the semiconductor chip 2 with the lead frame 700 using the
glue material 650, as illustrated in the first, second, third and
fourth cases shown in FIGS. 9A and 9B.
[0293] Referring to FIG. 10E, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS.
10A-10B can be replaced by the above-mentioned flexible circuit
film 46, bonded with the semiconductor chip 2, shown in FIG. 7B,
that is, the flexible circuit film 46 bonded with the semiconductor
chip 2 is joined with the lead frame 700 using the glue material
650, followed by bonding the wireboning wires 400, such as gold
wires, having a diameter of between 12 and 40 micrometers with the
wirebondable layer 230 and with the inner portion of the leads 701
via a wire-bonding process, followed by performing the
above-mentioned steps as shown in FIG. 10A-10B. Thereby, the
wirebondable layer 230 of the flexible circuit film 46 can be
electrically connected to the leads 701 of the lead frame 700
through the wireboning wires 400.
[0294] Referring to FIG. 10F, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS.
10A-10B can be replaced by the above-mentioned flexible circuit
film 48, bonded with the semiconductor chip 2, shown in FIG. 7I,
that is, the flexible circuit film 48 bonded with the semiconductor
chip 2 is joined with the lead frame 700 using the glue material
650, followed by bonding the wireboning wires 400, such as gold
wires, having a diameter of between 12 and 40 micrometers with the
wirebondable layer 230 and with the inner portion of the leads 701
via a wire-bonding process, followed by performing the
above-mentioned steps as shown in FIG. 10A-10B. Thereby, the
wirebondable layer 230 of the flexible circuit film 48 can be
electrically connected to the leads 701 of the lead frame 700
through the wireboning wires 400.
[0295] Referring to FIG. 10G, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS.
10A-10B can be replaced by the above-mentioned flexible circuit
film 36, bonded with the semiconductor chip 2, shown in FIG. 3D,
that is, the flexible circuit film 36 bonded with the semiconductor
chip 2 is joined with the lead frame 700 using the glue material
650, followed by joining the copper traces 210 with a
tin-containing solder preformed on the leads 701 to provide the
metal joints 513, such as tin-containing joints, between the copper
traces 210 and the leads 701, followed by performing the
above-mentioned steps as shown in FIGS. 10A-10B.
[0296] Referring to FIG. 10H, the above-mentioned flexible circuit
film 42, bonded with the semiconductor chip 2, shown in FIGS.
10A-10B can be replaced by the above-mentioned flexible circuit
film 38, bonded with the semiconductor chip 2, shown in FIG. 3T,
that is, the flexible circuit film 38 bonded with the semiconductor
chip 2 is joined with the lead frame 700 using the glue material
650, followed by joining the copper traces 210 with a
tin-containing solder preformed on the leads 701 to provide the
metal joints 513, such as tin-containing joints, between the copper
traces 210 and the leads 701, followed by performing the
above-mentioned steps as shown in FIGS. 10A-10B.
[0297] Those described above are the embodiments to exemplify the
present invention to enable the person skilled in the art to
understand, make and use the present invention. However, it is not
intended to limit the scope of the present invention. Any
equivalent modification and variation according to the spirit of
the present invention is to be also included within the scope of
the claims stated below.
* * * * *