U.S. patent application number 13/044628 was filed with the patent office on 2011-08-25 for sram cell with t-shaped contact.
This patent application is currently assigned to TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Thomas J. Aton, Theodore W. Houston, Scott W. Jessen.
Application Number | 20110204452 13/044628 |
Document ID | / |
Family ID | 43300138 |
Filed Date | 2011-08-25 |
United States Patent
Application |
20110204452 |
Kind Code |
A1 |
Houston; Theodore W. ; et
al. |
August 25, 2011 |
SRAM CELL WITH T-SHAPED CONTACT
Abstract
An integrated circuit containing an array of SRAM cells with
T-shaped contacts in the inverters, in which drain connecting
segments may extend beyond gate connecting segments by a distance
greater than 10 percent of a separation distance between ends of
opposite drain connecting segments. The drain connecting segments
may also extend beyond gate connecting segments by a distance
greater than one-third of the width of the gate connecting
segments. A process of forming an integrated circuit containing an
array of SRAM cells with T-shaped contacts in which drain
connecting segments may extend beyond gate connecting segments by a
distance greater than 10 percent of a separation distance between
ends of opposite drain connecting segments. A process may also form
the drain connecting segments to extend beyond gate connecting
segments by greater than one-third of the width of the gate
connecting segments.
Inventors: |
Houston; Theodore W.;
(Richardson, TX) ; Aton; Thomas J.; (Dallas,
TX) ; Jessen; Scott W.; (Allen, TX) |
Assignee: |
TEXAS INSTRUMENTS
INCORPORATED
Dallas
TX
|
Family ID: |
43300138 |
Appl. No.: |
13/044628 |
Filed: |
March 10, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12479266 |
Jun 5, 2009 |
|
|
|
13044628 |
|
|
|
|
Current U.S.
Class: |
257/393 ;
257/E27.099 |
Current CPC
Class: |
H01L 27/11 20130101;
H01L 21/823475 20130101; Y10S 257/903 20130101; H01L 27/1104
20130101; H01L 27/0207 20130101; H01L 23/5283 20130101 |
Class at
Publication: |
257/393 ;
257/E27.099 |
International
Class: |
H01L 27/11 20060101
H01L027/11 |
Claims
1. An integrated circuit containing an array of SRAM cells, each
said SRAM cell comprising: a first driver transistor of said SRAM
cell of said array within said integrated circuit, said first
driver transistor having a drain node and a channel region; a first
load transistor, said first load transistor having a drain node and
a channel region; a first inverter gate, said first inverter gate
overlapping said channel region of said first driver transistor and
overlapping said channel region of said first load transistor; a
second driver transistor, said second driver transistor having a
drain node and a channel region; a second load transistor, said
second load transistor having a drain node and a channel region; a
second inverter gate, said second inverter gate overlapping said
channel region of said second driver transistor and overlapping
said channel region of said second load transistor; a first
T-shaped contact, further including: a first drain connecting
segment, said first drain connecting segment overlapping said drain
node of said first driver transistor and overlapping said drain
node of said first load transistor; and a first gate connecting
segment, said first gate connecting segment overlapping said second
inverter gate and intersecting said first drain connecting segment;
and a second T-shaped contact, further including: a second drain
connecting segment, said second drain connecting segment
overlapping said drain node of said second driver transistor and
overlapping said drain node of said second load transistor; and a
second gate connecting segment, said second gate connecting segment
overlapping said first inverter gate and intersecting said second
drain connecting segment, such that; an end of said first drain
connecting segment overlapping said drain node of said first load
transistor extends beyond said intersection of said first gate
connecting segment by a distance greater than 10 percent of an end
separation distance between ends of said first drain connecting
segment and said second drain connecting segment; and an end of
said second drain connecting segment overlapping said drain node of
said second load transistor extends beyond said intersection of
said second gate connecting segment by a distance greater than 10
percent of said end separation distance between said ends of said
first drain connecting segment and said second drain connecting
segment; wherein, an end of said first gate connecting segment
overlapping said second inverter gate is inclined toward said end
of said first drain connecting segment by a first inclined
distance, said first inclined distance being greater than half said
distance by which said end of said first drain connecting segment
extends beyond said first gate connecting segment; and an end of
said second gate connecting segment overlapping said first inverter
gate is inclined toward said end of said second drain connecting
segment by a second inclined distance, said second inclined
distance being greater than half said distance by which said end of
said second drain connecting segment extends beyond said second
gate connecting segment.
2. The integrated circuit of claim 1, further including: a first
passgate transistor, said first passgate transistor having a
channel region; and a second passgate transistor, said second
passgate transistor having a channel region, such that; an outer
edge of said channel region of said first passgate transistor
extends beyond an outer edge of said channel region of said first
driver transistor by a distance greater than half said distance by
which said end of said first drain connecting segment extends
beyond said first gate connecting segment; and an outer edge of
said channel region of said second passgate transistor extends
beyond an outer edge of said channel region of said second driver
transistor by a distance greater than half said distance by which
said end of said second drain connecting segment extends beyond
said second gate connecting segment.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of application Ser. No.
12/479,266, filed Jun. 5, 2009, the content of which is hereby
incorporated by reference.
FIELD OF THE INVENTION
[0002] This invention relates to the field of integrated circuits.
More particularly, this invention relates to SRAMs in integrated
circuits.
DESCRIPTION OF THE VIEWS OF THE DRAWING
[0003] FIG. 1A through 1C are top views of a pair of cross-coupled
inverters in an SRAM cell contained in an integrated circuit, in
which T-shaped contacts are formed according to a first
embodiment.
[0004] FIG. 2A through 2C are top views of a pair of cross-coupled
inverters in an SRAM cell contained in an integrated circuit, in
which T-shaped contacts are formed according to a second embodiment
and depicted in successive stages of fabrication.
[0005] FIG. 3 is an integrated circuit containing an SRAM cell
array which includes SRAM cells with T-shaped contacts formed
according to one embodiment.
DETAILED DESCRIPTION
[0006] The present invention is described with reference to the
attached figures, wherein like reference numerals are used
throughout the figures to designate similar or equivalent elements.
The figures are not drawn to scale and they are provided merely to
illustrate the invention. Several aspects of the invention are
described below with reference to example applications for
illustration. It should be understood that numerous specific
details, relationships, and methods are set forth to provide an
understanding of the invention. One skilled in the relevant art,
however, will readily recognize that the invention can be practiced
without one or more of the specific details or with other methods.
In other instances, well-known structures or operations are not
shown in detail to avoid obscuring the invention. The present
invention is not limited by the illustrated ordering of acts or
events, as some acts may occur in different orders and/or
concurrently with other acts or events. Furthermore, not all
illustrated acts or events are required to implement a methodology
in accordance with the present invention.
[0007] For the purposes of this disclosure, the term "static random
access memory," referred to hereafter as SRAM, is understood to
mean any memory in which data is stored in cells as voltage levels
on cross-coupled inverters. SRAM cells are understood to include
six-transistor cells, cells with separate read ports and write
ports, cells with ferroelectric capacitors, and any other memory
cells with cross-coupled inverters.
[0008] In this disclosure, the term "driver transistor" is
understood to refer to a metal oxide semiconductor (MOS)
transistor, possibly a field effect transistor, a finFET transistor
or a carbon nanotube transistor (CNT), in an SRAM cell. A drain
node of the driver transistor is connected to a data node of the
SRAM cell. A gate node of the driver transistor is connected to an
opposite data node of the SRAM cell from the driver drain node. A
source node of the driver transistor is connected to a power supply
node, typically either Vdd for PMOS driver transistors or Vss for
NMOS driver transistors.
[0009] Similarly, the term "load transistor" is understood to refer
to another MOS transistor, possibly a field effect transistor, a
finFET transistor or a CNT, in the SRAM cell. A drain node of the
load transistor is connected to a data node of the SRAM cell. A
gate node of the load transistor is connected to an opposite data
node of the SRAM cell from the load drain node. A source node of
the load transistor is connected to a power supply node, typically
either Vdd for PMOS load transistors or Vss for NMOS load
transistors. A polarity of the load transistor is opposite a
polarity of driver transistors.
[0010] The term "passgate transistor" is understood to refer to yet
another MOS transistor, possibly a field effect transistor, a
finFET transistor or a CNT, in the SRAM cell, of which one
source/drain node is connected to a data node of the SRAM cell and
an opposite source/drain node is connected to a corresponding data
line of the SRAM cell. Similarly, the term "access transistor" is
understood to refer to an MOS transistor in the SRAM cell, of which
one source/drain node is connected to a data node of the SRAM cell
and an opposite source/drain node is connected to a read buffer
transistor. For the purposes of this disclosure, use of the term
passgate transistor will be distinguished from use of the term
access transistor by a convention in which passgate transistors are
never connected to read buffer transistors while access transistors
are always connected to read buffer transistors.
[0011] In some instances of integrated circuits containing SRAM
cell arrays, substantially all circuits in the integrated circuit
are dedicated to operation of the SRAM array. In these instances,
circuits which provide data to be stored in the SRAM array and
circuits which use data from the SRAM array are located outside the
integrated circuit containing the SRAM array. In other instances of
integrated circuits containing SRAM cell arrays, such as
microprocessors, digital signal processors and wireless telephony
controllers, the circuits which provide data to be stored in the
SRAM array and the circuits which use data from the SRAM array are
located within the integrated circuit.
[0012] An SRAM cell in an integrated circuit may contain T-shaped
contacts, in which each T-shaped contact provides an electrical
connection between a drain node of a driver transistor and a drain
node of a corresponding load transistor in one inverter and a gate
of an opposite inverter, where the two inverters form cross-coupled
inverters in the SRAM cell. A photolithographic exposure step for
drain connecting segments of the T-shaped contacts connecting the
drain nodes of the driver transistors and the load transistors may
be performed separately from a photolithographic exposure step for
the gate connecting segments of the T-shaped contacts connecting
the inverter gates to the drain connecting segments. In one
embodiment, an inner corner of the intersection of each gate
connecting segment with its corresponding drain connecting segment
may be laterally offset from a nearest end of the drain connecting
segment by an amount greater than 10 percent of a separation
between opposite drain connecting segments within the SRAM cell, so
as to increase a separation of the gate connecting segments. In
another embodiment, the inner corner of the intersection of each
gate connecting segment with its corresponding drain connecting
segment may be laterally offset from the nearest end of the drain
connecting segment by an amount greater than one-third of a width
of the gate connecting segment. In one embodiment, each gate
connecting segment may be substantially perpendicular to its
corresponding drain connecting segment. In another embodiment, each
gate connecting segment may be tilted with respect to its
corresponding drain connecting segment. In a further embodiment,
each gate connecting segment may have some curvature.
[0013] FIG. 1A through 1C are top views of a pair of cross-coupled
inverters in an SRAM cell (1002) contained in an integrated circuit
(1000), in which T-shaped contacts are formed according to a first
embodiment and depicted in successive stages of fabrication.
Referring to FIG. 1A, the SRAM cell (1002) includes a first
driver/passgate active strip (1004) and a second driver/passgate
active strip (1006). In some embodiments, the driver/passgate
active strips (1004, 1006) may be n-type. In other embodiments, the
driver/passgate active strips (1004, 1006) may be p-type. The SRAM
cell (1002) includes a first load active strip (1008) and a second
load active strip (1010). The load active strips (1008, 1010) are
an opposite conductivity type from the driver/passgate active
strips (1004, 1006).
[0014] The SRAM cell (1002) includes a first inverter gate (1012)
which crosses the first driver/passgate active strip (1004) and the
first load active strip (1008). An area of the first
driver/passgate active strip (1004) overlapped by the first
inverter gate (1012) forms a channel region (1014) of a first
driver transistor (1016) of the SRAM cell (1002). An area of the
first load active strip (1008) overlapped by the first inverter
gate (1012) forms a channel region (1018) of a first load
transistor (1020) of the SRAM cell (1002). The SRAM cell (1002)
also includes a first passgate gate (1022) which crosses the first
driver/passgate active strip (1004). An area of the first
driver/passgate active strip (1004) overlapped by the first
passgate gate (1022) forms a channel region (1024) of a first
passgate transistor (1026) of the SRAM cell (1002). The first
driver transistor (1016) and first load transistor (1020) are part
of a first inverter of the SRAM cell (1002).
[0015] Similarly, the SRAM cell (1002) includes a second inverter
gate (1028) which crosses the second driver/passgate active strip
(1006) and the second load active strip (1010). An area of the
second driver/passgate active strip (1006) overlapped by the second
inverter gate (1028) forms a channel region (1030) of a second
driver transistor (1032) of the SRAM cell (1002). An area of the
second load active strip (1010) overlapped by the second inverter
gate (1028) forms a channel region (1034) of a second load
transistor (1036) of the SRAM cell (1002). The SRAM cell (1002)
includes a second passgate gate (1038) which crosses the second
driver/passgate active strip (1006). An area of the second
driver/passgate active strip (1006) overlapped by the second
passgate gate (1038) forms a channel region (1040) of a second
passgate transistor (1042) of the SRAM cell (1002). The second
driver transistor (1032) and second load transistor (1036) are part
of a second inverter of the SRAM cell (1002).
[0016] During a manufacturing process, a dielectric layer (not
shown) is formed on the top surface of the integrated circuit
(1000) described supra. Then a layer of photoresist (not shown) is
formed over the dielectric layer. A first drain connecting segment
patterned area (1044) of a first T-shaped contact of the SRAM cell
(1002) is formed by a first photolithographic exposure step so that
the first drain connecting segment patterned area (1044) overlaps
the first driver/passgate active strip (1004) over a drain node
(1046) of the first driver transistor (1016), and also overlaps the
first load active strip (1008) over a drain node (1048) of the
first load transistor (1020). A second drain connecting segment
patterned area (1050) of a second T-shaped contact of the SRAM cell
(1002) is also formed by the first photolithographic exposure step
so that the second drain connecting segment patterned area (1050)
overlaps the second driver/passgate active strip (1006) over a
drain node (1052) of the second driver transistor (1032), and also
overlaps the second load active strip (1010) over a drain node
(1054) of the second load transistor (1036).
[0017] In another step of the manufacturing process, shown in FIG.
1B, a first gate connecting segment patterned area (1056) of the
first T-shaped contact is formed by a second photolithographic
exposure step so that the first gate connecting segment patterned
area (1056) overlaps the second inverter gate (1028) and intersects
the first drain connecting segment patterned area (1044) so that an
end of the first drain connecting segment patterned area (1044)
over the drain node (1048) of the first load transistor (1020)
extends beyond the first gate connecting segment patterned area
(1056) by a first pattern lateral offset distance (1058). In the
instant embodiment, the intersecting edges of the first drain
connecting segment patterned area (1044) and the first gate
connecting segment patterned area (1056) are substantially
perpendicular.
[0018] Similarly, a second gate connecting segment patterned area
(1060) of the second T-shaped contact is formed by the same second
photolithographic exposure step so that the second gate connecting
segment patterned area (1060) overlaps the first inverter gate
(1012) and intersects the second drain connecting segment patterned
area (1050) so that an end of the second drain connecting segment
patterned area (1050) over the drain node (1054) of the second load
transistor (1036) extends beyond the second gate connecting segment
patterned area (1060) by a second pattern lateral offset distance
(1062). In the instant embodiment, intersecting edges of the second
drain connecting segment patterned area (1050) and the second gate
connecting segment patterned area (1060) are substantially
perpendicular.
[0019] In one realization of the instant embodiment, the first
pattern lateral offset distance (1058) and the second pattern
lateral offset distance (1062) may each be greater than 10 percent
of an end separation distance (1064) between ends of the first
drain connecting segment patterned area (1044) and the second drain
connecting segment patterned area (1050). In an alternate
realization, the first pattern lateral offset distance (1058) may
be greater than one-third of a width (1066) of the first gate
connecting segment patterned area (1056), and the second pattern
lateral offset distance (1062) may be greater than one-third of a
width (1068) of the second gate connecting segment patterned area
(1060).
[0020] The outer edges of the first load active strip (1008) and
the second load active strip (1010) are separated by a load active
strip outer distance (1070). Inner edges of the first gate
connecting segment patterned area (1056) and the second gate
connecting segment patterned area (1060) are separated by a gate
connecting segment patterned area inner distance (1072).
[0021] In another realization of the instant embodiment, an outer
edge of the channel region (1024) of the first passgate transistor
(1026) may extend beyond an outer edge of the channel region (1014)
of the first driver transistor (1016) by a first driver/passgate
active offset distance (1074) which may be greater than half of the
first pattern lateral offset distance (1058). Similarly, an outer
edge of the channel region (1040) of the second passgate transistor
(1042) may extend beyond an outer edge of the channel region (1030)
of the second driver transistor (1032) by a second driver/passgate
active offset distance (1076) which may be greater than half of the
second pattern lateral offset distance (1062).
[0022] In yet another step of the manufacturing process, shown in
FIG. 1C, the first T-shaped contact (1078) is formed in an area
defined by the first drain connecting segment patterned area (1044)
and the first gate connecting segment patterned area (1056)
depicted in FIG. 1B. The first T-shaped contact (1078) includes a
first drain connecting segment (1080) in the area defined by the
first drain connecting segment patterned area (1044) of FIG. 1B and
a first gate connecting segment (1082) in the area defined by the
first gate connecting segment patterned area (1056) of FIG. 1B. The
first drain connecting segment (1080) makes electrical contact to
the drain node (1046) of the first driver transistor (1016) and to
the drain node (1048) of the first load transistor (1020). The
first gate connecting segment (1082) makes electrical contact to
the second inverter gate (1028). Thus, the first T-shaped contact
(1078) provides an electrical connection between the drain node
(1046) of the first driver transistor (1016), the drain node (1048)
of the first load transistor (1020), and the second inverter gate
(1028).
[0023] The second T-shaped contact (1084) is formed in an area
defined by the second drain connecting segment patterned area
(1050) and the second gate connecting segment patterned area
(1060). The second T-shaped contact (1084) is formed concurrently
with the first T-shaped contact (1078). The second T-shaped contact
(1084) includes a second drain connecting segment (1086) in the
area defined by the second drain connecting segment patterned area
(1050) of FIG. 1B and a second gate connecting segment (1088) in
the area defined by the second gate connecting segment patterned
area (1060) of FIG. 1B. The second drain connecting segment (1086)
makes electrical contact to the drain node (1052) of the second
driver transistor (1032) and to the drain node (1054) of the second
load transistor (1036). The second gate connecting segment (1088)
makes electrical contact to the first inverter gate (1012). Thus,
the second T-shaped contact (1084) provides an electrical
connection between the drain node (1052) of the second driver
transistor (1032), the drain node (1054) of the second load
transistor (1036), and the first inverter gate (1012).
[0024] An end of the first drain connecting segment (1080) over the
drain node (1048) of the first load transistor (1020) extends
beyond the first gate connecting segment (1082) by a first contact
lateral offset distance (1090). An end of the second drain
connecting segment (1086) over the drain node (1054) of the second
load transistor (1036) extends beyond the second gate connecting
segment (1088) by a second contact lateral offset distance (1092).
In one realization of the instant embodiment, the first contact
lateral offset distance (1090) and the second contact lateral
offset distance (1092) may each be greater than 10 percent of an
end separation distance (1094) between ends of the first drain
connecting segment (1080) and the second drain connecting segment
(1086). In an alternate realization, the first contact lateral
offset distance (1090) may be greater than one-third of a width
(1096) of the first gate connecting segment (1082), and the second
contact lateral offset distance (1092) may be greater than
one-third of a width (1098) of the second gate connecting segment
(1088).
[0025] The inner edges of the first gate connecting segment (1082)
and the second gate connecting segment (1088) are separated by a
gate connecting segment inner distance (1100). In one realization
of the instant embodiment, the first driver/passgate active offset
distance (1074) may be greater than half of the first contact
lateral offset distance (1090), and the second driver/passgate
active offset distance (1076) may be greater than half of the
second contact lateral offset distance (1092).
[0026] FIG. 2A through FIG. 2C are top views of a pair of
cross-coupled inverters in an SRAM cell (2002) contained in an
integrated circuit (2000), in which T-shaped contacts are formed
according to a second embodiment, depicted in successive stages of
fabrication. Referring to FIG. 2A, the SRAM cell (2002) includes a
first driver/passgate active strip (2004), a second driver/passgate
active strip (2006), a first load active strip (2008) and a second
load active strip (2010) with the properties described in reference
to FIG. 1A. The SRAM cell (2002) includes a first inverter gate
(2012) which crosses the first driver/passgate active strip (2004)
and the first load active strip (2008). An area of the first
driver/passgate active strip (2004) overlapped by the first
inverter gate (2012) forms a channel region (2014) of a first
driver transistor (2016) of the SRAM cell (2002). An area of the
first load active strip (2008) overlapped by the first inverter
gate (2012) forms a channel region (2018) of a first load
transistor (2020) of the SRAM cell (2002). The SRAM cell (2002)
includes a first passgate gate (2022) which crosses the first
driver/passgate active strip (2004). An area of the first
driver/passgate active strip (2004) overlapped by the first
passgate gate (2022) forms a channel region (2024) of a first
passgate transistor (2026) of the SRAM cell (2002). The first
driver transistor (2016) and first load transistor (2020) are part
of a first inverter of the SRAM cell (2002). Similarly, the SRAM
cell (2002) includes a second inverter gate (2028) which crosses
the second driver/passgate active strip (2006) and the second load
active strip (2010). An area of the second driver/passgate active
strip (2006) overlapped by the second inverter gate (2028) forms a
channel region (2030) of a second driver transistor (2032) of the
SRAM cell (2002). An area of the second load active strip (2010)
overlapped by the second inverter gate (2028) forms a channel
region (2034) of a second load transistor (2036) of the SRAM cell
(2002). The SRAM cell (2002) includes a second passgate gate (2038)
which crosses the second driver/passgate active strip (2006). An
area of the second driver/passgate active strip (2006) overlapped
by the second passgate gate (2038) forms a channel region (2040) of
a second passgate transistor (2042) of the SRAM cell (2002). The
second driver transistor (2032) and second load transistor (2036)
are part of a second inverter of the SRAM cell (2002).
[0027] During a manufacturing process, a dielectric layer (not
shown) is formed on the top surface of the integrated circuit
(2000) of the second embodiment, described supra. Then a layer of
photoresist (not shown) is formed over the dielectric layer. A
first drain connecting segment patterned area (2044) of a first
T-shaped contact of the SRAM cell (2002) is formed by a first
photolithographic exposure step so that the first drain connecting
segment patterned area (2044) overlaps the first driver/passgate
active strip (2004) over a drain node (2046) of the first driver
transistor (2016), and also overlaps the first load active strip
(2008) over a drain node (2048) of the first load transistor
(2020). A second drain connecting segment patterned area (2050) of
a second T-shaped contact of the SRAM cell (2002) is also formed by
the first photolithographic exposure step so that the second drain
connecting segment patterned area (2050) overlaps the second
driver/passgate active strip (2006) over a drain node (2052) of the
second driver transistor (2032), and also overlaps the second load
active strip (2010) over a drain node (2054) of the second load
transistor (2036).
[0028] In another step of the manufacturing process, shown in FIG.
2B, a first gate connecting segment patterned area (2056) of the
first T-shaped contact is formed by a second photolithographic
exposure step so that the first gate connecting segment patterned
area (2056) overlaps the second inverter gate (2028) and intersects
the first drain connecting segment patterned area (2044) so that an
end of the first drain connecting segment patterned area (2044)
over the drain node (2048) of the first load transistor (2020)
extends beyond the first gate connecting segment patterned area
(2056) by a first pattern lateral offset distance (2058). In the
instant embodiment, an end of the first gate connecting segment
patterned area (2056) overlapping the second inverter gate (2028)
is inclined toward the end of the first drain connecting segment
patterned area (2044) by a first pattern inclined distance (2060)
which may be greater than half of the first pattern lateral offset
distance (2058).
[0029] Similarly, a second gate connecting segment patterned area
(2062) of the second T-shaped contact is formed by the same second
photolithographic exposure step so that the second gate connecting
segment patterned area (2062) overlaps the first inverter gate
(2012) and intersects the second drain connecting segment patterned
area (2050) so that an end of the second drain connecting segment
patterned area (2050) over the drain node (2054) of the second load
transistor (2036) extends beyond the second gate connecting segment
patterned area (2062) by a second pattern lateral offset distance
(2064). In the instant embodiment, an end of the second gate
connecting segment patterned area (2062) overlapping the first
inverter gate (2012) is inclined toward the end of the second drain
connecting segment patterned area (2050) by a second pattern
inclined distance (2066) which may be greater than half of the
second pattern lateral offset distance (2064).
[0030] In one realization of the instant embodiment, the first
pattern lateral offset distance (2058) and the second pattern
lateral offset distance (2064) may each be greater than 10 percent
of an end separation distance (2068) between ends of the first
drain connecting segment patterned area (2044) and the second drain
connecting segment patterned area (2050). In an alternate
realization, the first pattern lateral offset distance (2058) may
be greater than one-third of a width (2070) of the first gate
connecting segment patterned area (2056), and the second pattern
lateral offset distance (2064) may be greater than one-third of a
width (2072) of the second gate connecting segment patterned area
(2062).
[0031] In another realization of the instant embodiment, an outer
edge of the channel region (2024) of the first passgate transistor
(2026) may extend beyond an outer edge of the channel region (2014)
of the first driver transistor (2016) by a first driver/passgate
active offset distance (2074) which may be greater than half of the
end separation distance (2068). Similarly, an outer edge of the
channel region (2040) of the second passgate transistor (2042) may
extend beyond an outer edge of the channel region (2030) of the
second driver transistor (2032) by a second driver/passgate active
offset distance (2076) which may be greater than half of the end
separation distance (2068).
[0032] Referring to FIG. 2C, the first T-shaped contact (2078) is
formed in an area defined by the first drain connecting segment
patterned area (2044) and the first gate connecting segment
patterned area (2056) depicted in FIG. 2B. The first T-shaped
contact (2078) includes a first drain connecting segment (2080) in
the area defined by the first drain connecting segment patterned
area (2044) of FIG. 2B and a first gate connecting segment (2082)
in the area defined by the first gate connecting segment patterned
area (2056) of FIG. 2B. The first drain connecting segment (2080)
makes electrical contact to the drain node (2046) of the first
driver transistor (2016) and to the drain node (2048) of the first
load transistor (2020). The first gate connecting segment (2082)
also makes electrical contact to the second inverter gate (2028).
Thus, the first T-shaped contact (2078) provides an electrical
connection between the drain node (2046) of the first driver
transistor (2016), the drain node (2048) of the first load
transistor (2020), and the second inverter gate (2028).
[0033] The second T-shaped contact (2084) is formed in an area
defined by the second drain connecting segment patterned area
(2050) and the second gate connecting segment patterned area (2062)
depicted in FIG. 2B. The second T-shaped contact (2084) is formed
concurrently with the first T-shaped contact (2078). The second
T-shaped contact (2084) includes a second drain connecting segment
(2086) in the area defined by the second drain connecting segment
patterned area (2050) of FIG. 2B and a second gate connecting
segment (2088) in the area defined by the second gate connecting
segment patterned area (2062) of FIG. 2B. The second drain
connecting segment (2086) makes electrical contact to the drain
node (2052) of the second driver transistor (2032) and to the drain
node (2054) of the second load transistor (2036). The second gate
connecting segment (2088) also makes electrical contact to the
first inverter gate (2012). Thus, the second T-shaped contact
(2084) provides an electrical connection between the drain node
(2052) of the second driver transistor (2032), the drain node
(2054) of the second load transistor (2036), and the first inverter
gate (2012).
[0034] An end of the first drain connecting segment (2080) over the
drain node (2048) of the first load transistor (2020) extends
beyond the first gate connecting segment (2082) by a first contact
lateral offset distance (2090). In the instant embodiment, an end
of the first gate connecting segment (2082) overlapping the second
inverter gate (2028) is inclined toward the end of the first drain
connecting segment (2080) by a first contact inclined distance
(2092) which may be greater than half of the first contact lateral
offset distance (2090). An end of the second drain connecting
segment (2086) over the drain node (2052) of the second load
transistor (2032) extends beyond the second gate connecting segment
(2088) by a second contact lateral offset distance (2094). In the
instant embodiment, an end of the second gate connecting segment
(2088) overlapping the first inverter gate (2012) is inclined
toward the end of the second drain connecting segment (2086) by a
second contact inclined distance (2096) which may be greater than
half of the second contact lateral offset distance (2094).
[0035] In one realization of the instant embodiment, the first
contact lateral offset distance (2090) and the second contact
lateral offset distance (2094) may be each greater than 10 percent
of an end separation distance (2098) between ends of the first
drain connecting segment (2080) and the second drain connecting
segment (2086). In an alternate realization, the first contact
lateral offset distance (2090) may be greater than one-third of a
width (2100) of the first gate connecting segment (2082), and the
second contact lateral offset distance (2094) may be greater than
one-third of a width (2102) of the second gate connecting segment
(2088).
[0036] FIG. 3 is an integrated circuit (3000) containing an SRAM
cell array (3002) which includes SRAM cells (3004) with T-shaped
contacts formed according to one embodiment. The SRAM cells (3004)
are arranged in rows (3006) and columns (3008). Each word line bus
(3010) is connected to SRAM cells (3004) in a row (3006). Each word
line bus (3010) may include more than one word line. Each bit line
bus (3012) is connected to SRAM cells (3004) in a column (3008).
Each bit line bus (3012) may include one or more bit or bit-bar
lines. A row decoder circuit (3014) applies appropriate biases to
word lines in the word line buses (3010). A column decoder circuit
(3016) applies appropriate biases to bit or bit-bar lines in the
bit line buses (3012). A data input/output (10) circuit (3018)
reads data from the bit or bit-bar lines in the bit line buses
(3012) during read operations and applies appropriate potentials to
the bit or bit-bar lines in the bit line buses (3012) during single
sided write operations. The integrated circuit further includes a
data bus (3020) which carries data bits between the data 10 circuit
(3018) and circuits in the integrated circuit (3000), and an
address bus (3022) which is used to select SRAM cells (3004) in the
SRAM cell array (3002) for read and write operations. The address
bus (3022) is connected to the row decoder circuit (3014) and the
column decoder circuit (3016). The integrated circuit (3000) may
also contain a data generation circuit (3024) which connects to the
data bus (3020) and address bus (3022). The data generation circuit
(3024) produces incoming data bits for storage in the SRAM cell
array (3002). The data bus (3020) carries the incoming data bits
from the data generation circuit (3024) to the SRAM cell array
(3002). The integrated circuit (3000) may also contain a data usage
circuit (3026) which connects to the data bus (3020) and address
bus (3022). The data usage circuit (3026) uses outgoing data bits
which were stored in the SRAM cell array (3002). The data bus
(3020) carries the outgoing data bits from the SRAM cell array
(3002) to the data usage circuit (3026).
[0037] While various embodiments of the present invention have been
described above, it should be understood that they have been
presented by way of example only and not limitation. Numerous
changes to the disclosed embodiments can be made in accordance with
the disclosure herein without departing from the spirit or scope of
the invention. Thus, the breadth and scope of the present invention
should not be limited by any of the above described embodiments.
Rather, the scope of the invention should be defined in accordance
with the following claims and their equivalents.
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