Houston; Theodore W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Houston; Theodore W..The latest application filed is for "sram cell with t-shaped contact".

Company Profile

6.200.157

Houston; Theodore W. - Richardson TX
Houston; Theodore W. - Richardon TX
Houston; Theodore W - Richardson TX
Houston; Theodore W. - Dallas County TX
Houston; Theodore W. - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
SRAM cell with T-shaped contact Grant 10,756,095 - Houston , et al. A	2020-08-25
SRAM cell with T-shaped contact Grant 10,748,913 - Houston , et al. A	2020-08-18
SRAM cell having an n-well bias Grant 10,629,250 - Seshadri , et al.	2020-04-21
Sram Cell With T-shaped Contact App 20190148386 - Houston; Theodore W. ; et al.	2019-05-16
Sram Cell With T-shaped Contact App 20190081051 - Houston; Theodore W. ; et al.	2019-03-14
SRAM cell with T-shaped contact Grant 10,199,380 - Houston , et al. Fe	2019-02-05
SRAM cell with T-shaped contact Grant 10,163,911 - Houston , et al. Dec	2018-12-25
Integrated circuit with low power SRAM Grant 9,858,986 - Houston , et al. January 2, 2	2018-01-02
Read assist for an SRAM using a word line suppression circuit Grant 9,236,113 - Holla , et al. January 12, 2	2016-01-12
Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same Grant 9,124,263 - Houston , et al. September 1, 2	2015-09-01
Read assist circuit for an SRAM, including a word line suppression circuit Grant 9,082,507 - Holla , et al. July 14, 2	2015-07-14
SRAM cell parameter optimization Grant 9,059,032 - Houston , et al. June 16, 2	2015-06-16
SRAM cell with different crystal orientation than associated logic Grant 8,945,999 - Houston February 3, 2	2015-02-03
SRAM cell having a p-well bias Grant 8,891,287 - Seshadri , et al. November 18, 2	2014-11-18
8T SRAM cell with one word line Grant 8,891,288 - Houston November 18, 2	2014-11-18
Sram Cell With Different Crystal Orientation Than Associated Logic App 20140322870 - Houston; Theodore W.	2014-10-30
8T SRAM cell with one word line Grant 8,873,279 - Houston October 28, 2	2014-10-28
8t Sram Cell With One Word Line App 20140293681 - Houston; Theodore W.	2014-10-02
Read Assist Circuit For An Sram Technical Field App 20140241089 - Holla; Lakshmikantha V. ; et al.	2014-08-28
Read Assist Circuit For An Sram Technical Field App 20140241083 - Holla; Lakshmikantha V. ; et al.	2014-08-28
Read assist circuit for an SRAM Grant 8,755,239 - Holla , et al. June 17, 2	2014-06-17
SRAM cell having an N-well bias Grant 8,724,375 - Seshadri , et al. May 13, 2	2014-05-13
10T SRAM cell with near dual port functionality Grant 8,654,569 - Houston February 18, 2	2014-02-18
10T SRAM cell with near dual port functionality Grant 8,654,572 - Houston February 18, 2	2014-02-18
10T SRAM cell with near dual port functionality Grant 8,654,568 - Houston February 18, 2	2014-02-18
SRAM cell with different crystal orientation than associated logic Grant 8,535,990 - Houston September 17, 2	2013-09-17
8t Sram Cell With One Word Line App 20130229859 - Houston; Theodore W.	2013-09-05
Offset geometries for area reduction in memory arrays Grant 8,492,205 - Houston , et al. July 23, 2	2013-07-23
10t Sram Cell With Near Dual Port Functionality App 20130182492 - Houston; Theodore W.	2013-07-18
Sram Cell Having An N-well Bias App 20130148416 - Seshadri; Anand ; et al.	2013-06-13
Read Assist Circuit For An Sram App 20130128680 - Holla; Lakshmikantha V. ; et al.	2013-05-23
Memory cell employing reduced voltage Grant 8,437,214 - Mikan , et al. May 7, 2	2013-05-07
Characterization of bits in a functional memory Grant 8,437,213 - Deng , et al. May 7, 2	2013-05-07
Structure and methods for measuring margins in an SRAM bit Grant 8,379,467 - Deng , et al. February 19, 2	2013-02-19
Statistical evaluation of circuit robustness separating local and global variation Grant 8,380,478 - Houston February 19, 2	2013-02-19
Integrated DRAM process/structure using contact pillars Grant 8,378,405 - Houston February 19, 2	2013-02-19
SRAM cell for single sided write Grant 8,379,434 - Houston , et al. February 19, 2	2013-02-19
3T DRAM cell with added capacitance on storage node Grant 8,379,433 - Houston , et al. February 19, 2	2013-02-19
Smart well assisted SRAM read and write Grant 8,379,435 - McMullan , et al. February 19, 2	2013-02-19
Memory Cell Employing Reduced Voltage App 20130003471 - Mikan, JR.; Donald George ; et al.	2013-01-03
SRAM cell for single sided write Grant 8,339,839 - Houston , et al. December 25, 2	2012-12-25
Memory with low power mode for write Grant 8,331,187 - Houston , et al. December 11, 2	2012-12-11
SRAM cell with different crystal orientation than associated logic Grant 8,324,665 - Houston December 4, 2	2012-12-04
Sram Strap Row Substrate Contact App 20120300537 - Garcia; Robert R. ; et al.	2012-11-29
Sram Strap Row Well Contact App 20120300536 - Houston; Theodore W.	2012-11-29
Sram Cell With Different Crystal Orientation Than Associated Logic App 20120302013 - Houston; Theodore W.	2012-11-29
Sram Strap Row Double Well Contact App 20120300538 - Houston; Theodore W.	2012-11-29
SRAM strap row substrate contact Grant 8,320,165 - Garcia , et al. November 27, 2	2012-11-27
SRAM strap row well contact Grant 8,315,086 - Houston November 20, 2	2012-11-20
SRAM strap row double well contact Grant 8,310,860 - Houston November 13, 2	2012-11-13
Sram Cell Parameter Optimization App 20120275207 - Houston; Theodore W. ; et al.	2012-11-01
Two word line SRAM cell with strong-side word line boost for write provided by weak-side word line Grant 8,300,451 - Mair , et al. October 30, 2	2012-10-30
Apparatus and method for accelerating simulations and designing integrated circuits and other systems Grant 8,301,431 - Heragu , et al. October 30, 2	2012-10-30
Sram Cell With T-shaped Contact App 20120264294 - Houston; Theodore W. ; et al.	2012-10-18
Sram Cell With Asymmetrical Pass Gate App 20120261768 - Houston; Theodore W. ; et al.	2012-10-18
Sram Cell With T-shaped Contact App 20120264293 - Houston; Theodore W. ; et al.	2012-10-18
Sram Cell With T-shaped Contact App 20120258593 - Houston; Theodore W. ; et al.	2012-10-11
Sram Cell With T-shaped Contact App 20120228722 - Houston; Theodore W. ; et al.	2012-09-13
8T SRAM Cell With One Word Line App 20120230088 - Houston; Theodore W.	2012-09-13
Memory cell employing reduced voltage Grant 8,248,867 - Mikan, Jr. , et al. August 21, 2	2012-08-21
Sram Cell Having An N-well Bias App 20120201072 - Seshadri; Anand ; et al.	2012-08-09
Sram Cell Having A P-well Bias App 20120195108 - Seshadri; Anand ; et al.	2012-08-02
Temperature responsive back bias control for integrated circuit Grant 8,217,322 - Houston , et al. July 10, 2	2012-07-10
SRAM cell with asymmetrical pass gate Grant 8,216,903 - Houston , et al. July 10, 2	2012-07-10
SRAM cell with asymmetrical pass gate Grant 8,211,773 - Houston , et al. July 3, 2	2012-07-03
10T SRAM Cell with Near Dual Port Functionality App 20120163068 - Houston; Theodore W.	2012-06-28
8T SRAM cell with one word line Grant 8,203,867 - Houston June 19, 2	2012-06-19
SRAM Cell for Single Sided Write App 20120127783 - Houston; Theodore W. ; et al.	2012-05-24
Asymmetric SRAM cell with split transistors on the strong side Grant 8,184,474 - Seshadri , et al. May 22, 2	2012-05-22
8T SRAM cell with four load transistors Grant 8,179,715 - Houston May 15, 2	2012-05-15
8T SRAM cell with two single sided ports Grant 8,164,945 - Houston April 24, 2	2012-04-24
6T SRAM cell with single sided write Grant 8,159,863 - Houston , et al. April 17, 2	2012-04-17
Structure and methods for measuring margins in an SRAM bit Grant 8,139,431 - Deng , et al. March 20, 2	2012-03-20
3t Dram Cell With Added Capacitance On Storage Node App 20120063202 - Houston; Theodore W. ; et al.	2012-03-15
Offset geometries for area reduction in memory arrays Grant 8,110,855 - Houston , et al. February 7, 2	2012-02-07
Integrated Circuit With Low Power SRAM App 20120026808 - Houston; Theodore W. ; et al.	2012-02-02
Local sensing and feedback for an SRAM array Grant 8,064,275 - Houston , et al. November 22, 2	2011-11-22
Structure and method for screening SRAMS Grant 8,064,279 - Houston , et al. November 22, 2	2011-11-22
Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same Grant 8,064,271 - Houston November 22, 2	2011-11-22
Two Word Line Sram Cell With Strong-side Word Line Boost For Write Provided By Weak-side Word Line App 20110242879 - Mair; Hugh T. ; et al.	2011-10-06
Body Bias Coordinator, Method Of Coordinating A Body Bias And Sub-circuit Power Supply Employing The Same App 20110221515 - Houston; Theodore W. ; et al.	2011-09-15
Temperature dependent back-bias for a memory array Grant 8,018,780 - Houston , et al. September 13, 2	2011-09-13
Sram Cell With T-shaped Contact App 20110204452 - Houston; Theodore W. ; et al.	2011-08-25
10T SRAM Cell with Near Dual Port Functionality App 20110182112 - Houston; Theodore W.	2011-07-28
SRAM cell with read buffer controlled for low leakage current Grant 7,986,566 - Houston July 26, 2	2011-07-26
Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same Grant 7,978,004 - Houston , et al. July 12, 2	2011-07-12
Sram Cell With T-shaped Contact App 20110159684 - Houston; Theodore W. ; et al.	2011-06-30
Structure and Methods for Measuring Margins in an SRAM Bit App 20110158018 - Deng; Xiaowei ; et al.	2011-06-30
Sram Cell With T-shaped Contact App 20110156168 - Houston; Theodore W. ; et al.	2011-06-30
Adaptive voltage control for SRAM Grant 7,936,589 - Houston May 3, 2	2011-05-03
SRAM Cell with Different Crystal Orientation than Associated Logic App 20110092029 - Houston; Theodore W.	2011-04-21
Memory Cell Employing Reduced Voltage App 20110069565 - Mikan, JR.; Donald George ; et al.	2011-03-24
Memory having circuitry controlling the voltage differential between the word line and array supply voltage Grant 7,907,456 - Houston , et al. March 15, 2	2011-03-15
10T SRAM Cell with Near Dual Port Functionality App 20110044094 - Houston; Theodore W.	2011-02-24
Temperature Responsive Back Bias Control For Integrated Circuit App 20110043255 - Houston; Theodore W. ; et al.	2011-02-24
Asymmetrical SRAM cell with separate word lines Grant 7,894,280 - Houston February 22, 2	2011-02-22
Offset Geometries for Area Reduction in Memory Arrays App 20110018035 - Houston; Theodore W. ; et al.	2011-01-27
Smart Well Assisted SRAM Read and Write App 20110019464 - McMullan; Russell C. ; et al.	2011-01-27
Offset Geometries for Area Reduction In Memory Arrays App 20110020986 - Houston; Theodore W. ; et al.	2011-01-27
Structure and Method for Screening SRAMS App 20110013470 - Houston; Theodore W. ; et al.	2011-01-20
Local Sensing And Feedback For An Sram Array App 20110007580 - Houston; Theodore W. ; et al.	2011-01-13
Memory cell employing reduced voltage Grant 7,864,600 - Mikan, Jr. , et al. January 4, 2	2011-01-04
SRAM Cell with T-Shaped Contact App 20100308419 - Houston; Theodore W. ; et al.	2010-12-09
8T SRAM Cell with Two Single Sided Ports App 20100296336 - Houston; Theodore W.	2010-11-25
8T SRAM Cell With One Word Line App 20100296333 - Houston; Theodore W.	2010-11-25
8T SRAM Cell with Four Load Transistors App 20100296337 - Houston; Theodore W.	2010-11-25
6T SRAM Cell with Single Sided Write App 20100296334 - Houston; Theodore W. ; et al.	2010-11-25
Asymmetric SRAM Cell with Split Transistors on the Strong Side App 20100296335 - Sashadri; Anand ; et al.	2010-11-25
SRAM Cell for Single Sided Write App 20100296332 - Houston; Theodore W. ; et al.	2010-11-25
Method for constructing Shmoo plots for SRAMs Grant 7,821,816 - Deng , et al. October 26, 2	2010-10-26
Partial write-back in read and write-back of a memory Grant 7,821,843 - Houston October 26, 2	2010-10-26
SRAM Cell with Different Crystal Orientation than Associated Logic App 20100264465 - Houston; Theodore W.	2010-10-21
Sram Cell With Read Buffer Controlled For Low Leakage Current App 20100254199 - Houston; Theodore W.	2010-10-07
Method for Constructing Shmoo Plots for SRAMS App 20100232242 - Deng; Xiaowei ; et al.	2010-09-16
Partial Write-back In Read And Write-back Of A Memory App 20100226186 - Houston; Theodore W.	2010-09-09
Structure and Methods for Measuring Margins in an SRAM bit App 20100208536 - Deng; Xiaowei ; et al.	2010-08-19
SRAM Cell with Asymmetrical Pass Gate App 20100207183 - Houston; Theodore W. ; et al.	2010-08-19
Feedback structure for an SRAM cell Grant 7,768,820 - Houston , et al. August 3, 2	2010-08-03
SRAM employing a read-enabling capacitance Grant 7,755,924 - Houston July 13, 2	2010-07-13
Integrated DRAM process/structure using contact pillars Grant 7,745,867 - Houston June 29, 2	2010-06-29
Integrated virtual voltage circuit Grant 7,714,642 - Marshall , et al. May 11, 2	2010-05-11
SRAM cell using separate read and write circuitry Grant 7,710,763 - Houston May 4, 2	2010-05-04
Sub-lithographics opening for back contact or back gate Grant 7,704,811 - Houston April 27, 2	2010-04-27
Tunable voltage controller for a sub-circuit and method of operating the same Grant 7,671,663 - Houston , et al. March 2, 2	2010-03-02
Adaptive Voltage Control for SRAM App 20100020591 - Houston; Theodore W.	2010-01-28
Memory Cell Employing Reduced Voltage App 20090316500 - Mikan, JR.; Donald George ; et al.	2009-12-24
Adaptive voltage control for SRAM Grant 7,626,852 - Houston December 1, 2	2009-12-01
Integrated circuit having a supply voltage controller capable of floating a variable supply voltage Grant 7,619,947 - Houston November 17, 2	2009-11-17
Static random-access memory having reduced bit line precharge voltage and method of operating the same Grant 7,570,527 - Houston August 4, 2	2009-08-04
SRAM bias for read and write Grant 7,564,725 - Houston July 21, 2	2009-07-21
Feedback Structure For An Sram Cell App 20090175062 - Houston; Theodore W. ; et al.	2009-07-09
Sram Employing A Read-enabling Capacitance App 20090175067 - Houston; Theodore W.	2009-07-09
Characterization Of Bits In A Functional Memory App 20090175113 - Deng; Xiaowei ; et al.	2009-07-09
Apparatus And Method For Accelerating Simulations And Designing Integrated Circuits And Other Systems App 20090177451 - HERAGU; KEERTHINARAYAN P. ; et al.	2009-07-09
Seven Transistor Sram Cell App 20090161410 - Houston; Theodore W.	2009-06-25
Method of fabricating etch-stopped SOI back-gate contact Grant 7,534,668 - Houston May 19, 2	2009-05-19
Integrated Circuit Having Supply Voltage Controller App 20090109764 - Houston; Theodore W.	2009-04-30
Memory Having Circuitry Controlling The Voltage Differential Between The Word Line And Array Supply Voltage App 20090109785 - Houston; Theodore W. ; et al.	2009-04-30
Asymmetrical Sram Cell With Separate Word Lines App 20090109732 - Houston; Theodore W.	2009-04-30
SRAM Cell Using Separate Read and Write Circuitry App 20090103375 - Houston; Theodore W.	2009-04-23
Memory array with a delayed wordline boost Grant 7,508,698 - Houston March 24, 2	2009-03-24
Memory array with a delayed wordline boost Grant 7,502,247 - Houston March 10, 2	2009-03-10
Sram Bias For Read And Write App 20090059685 - Houston; Theodore W.	2009-03-05
Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same Grant 7,499,354 - Houston , et al. March 3, 2	2009-03-03
Adaptive Voltage Control For Sram App 20090027990 - Houston; Theodore W.	2009-01-29
SRAM cell using separate read and write circuitry Grant 7,483,332 - Houston January 27, 2	2009-01-27
Static random access memory device having reduced leakage current during active mode and a method of operating thereof Grant 7,453,743 - Houston November 18, 2	2008-11-18
Sram Cell With Asymmetrical Transistors For Reduced Leakage App 20080237745 - YANG; Shyh-Horng ; et al.	2008-10-02
Temperature Dependent Back-bias For A Memory Array App 20080175068 - Houston; Theodore W. ; et al.	2008-07-24
Sub-lithographics Opening For Back Contact Or Back Gate App 20080166839 - Houston; Theodore W.	2008-07-10
Integrated Dram Process/structure Using Contact Pillars App 20080150078 - Houston; Theodore W.	2008-06-26
Tunable Voltage Controller For A Sub-circuit And Method Of Operating The Same App 20080136497 - Houston; Theodore W. ; et al.	2008-06-12
Static random access memory device having a voltage-controlled word line driver for retain till accessed mode and method of operating the same Grant 7,385,841 - Houston June 10, 2	2008-06-10
SRAM cell with asymmetrical transistors for reduced leakage Grant 7,384,839 - Yang , et al. June 10, 2	2008-06-10
Sub-lithographics opening for back contact or back gate Grant 7,372,101 - Houston May 13, 2	2008-05-13
Integrated Virtual Voltage Circuit App 20080100369 - Marshall; Andrew ; et al.	2008-05-01
Method and system for contiguous proximity correction for semiconductor masks Grant 7,341,808 - Houston , et al. March 11, 2	2008-03-11
Static Random Access Memory Device Having Reduced Leakage Current During Active Mode And A Method Of Operating Thereof App 20080043542 - HOUSTON; Theodore W.	2008-02-21
Static random access memory device having reduced leakage current during active mode and a method of operating thereof Grant 7,333,357 - Houston February 19, 2	2008-02-19
Memory Array With A Delayed Wordline Boost App 20080037346 - Houston; Theodore W.	2008-02-14
Staggered memory cell array Grant 7,327,591 - Sadra , et al. February 5, 2	2008-02-05
Memory Array With A Delayed Wordline Boost App 20080019202 - Houston; Theodore W.	2008-01-24
SRAM device and a method of operating the same to reduce leakage current during a sleep mode Grant 7,307,907 - Houston December 11, 2	2007-12-11
System for reducing row periphery power consumption in memory devices Grant 7,301,849 - Deng , et al. November 27, 2	2007-11-27
Bit line control for low power in standby Grant 7,298,663 - Houston , et al. November 20, 2	2007-11-20
Memory array with a delayed wordline boost Grant 7,289,354 - Houston October 30, 2	2007-10-30
Area efficient implementation of small blocks in an SRAM array Grant 7,236,396 - Houston , et al. June 26, 2	2007-06-26
Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same App 20070121390 - Houston; Theodore W. ; et al.	2007-05-31
Design method and system for optimum performance in integrated circuits that use power management Grant 7,216,310 - Chatterjee , et al. May 8, 2	2007-05-08
Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same App 20070096794 - Houston; Theodore W. ; et al.	2007-05-03
Write assist for latch and memory circuits App 20070081379 - Clinton; Michael Patrick ; et al.	2007-04-12
Method and apparatus for reducing capacitive coupling between lines in an integrated circuit Grant 7,199,471 - Houston April 3, 2	2007-04-03
Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same App 20070070773 - Houston; Theodore W.	2007-03-29
SRAM cell with asymmetrical pass gate App 20070069290 - Houston; Theodore W. ; et al.	2007-03-29
SRAM cell with asymmetrical transistors for reduced leakage App 20070069277 - Yang; Shyh-Horng ; et al.	2007-03-29
Thermostatic biasing controller, method of thermostatic biasing and an integrated circuit employing the same App 20070068915 - Houston; Theodore W. ; et al.	2007-03-29
SRAM cell using separate read and write circuitry App 20070035986 - Houston; Theodore W.	2007-02-15
Static random access memory device having a voltage-controlled word line driver for retain till accessed mode and method of operating the same App 20070035987 - Houston; Theodore W.	2007-02-15
Memory array with a delayed wordline boost App 20070025169 - Houston; Theodore W.	2007-02-01
Sram Cell With Column Select Line App 20070025162 - Deng; Xiaowei ; et al.	2007-02-01
SRAM cell with column select line Grant 7,164,596 - Deng , et al. January 16, 2	2007-01-16
Area efficient implementation of small blocks in an SRAM array App 20070002617 - Houston; Theodore W. ; et al.	2007-01-04
Asymmetric static random access memory device having reduced bit line leakage Grant 7,158,402 - Houston January 2, 2	2007-01-02
Bonded SOI with buried interconnect to handle or device wafer Grant 7,153,756 - Houston December 26, 2	2006-12-26
Semiconductor on insulator device architecture and method of construction Grant 7,148,121 - Houston December 12, 2	2006-12-12
Static random-access memory having reduced bit line precharge voltage and method of operating the same App 20060274587 - Houston; Theodore W.	2006-12-07
Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs Grant 7,132,340 - Sadra , et al. November 7, 2	2006-11-07
System for reducing row periphery power consumption in memory devices Grant 7,120,082 - Deng , et al. October 10, 2	2006-10-10
Means for forming SOI Grant 7,101,772 - Houston , et al. September 5, 2	2006-09-05
Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs App 20060134889 - Sadra; Kayvan ; et al.	2006-06-22
Low leakage SRAM scheme Grant 7,039,818 - Deng , et al. May 2, 2	2006-05-02
Bit line control for low power in standby Grant 7,027,346 - Houston , et al. April 11, 2	2006-04-11
Sub-lithographics opening for back contact or back gate App 20060027867 - Houston; Theodore W.	2006-02-09
Integrated circuit cells Grant 6,996,787 - Houston February 7, 2	2006-02-07
Method and system for contiguous proximity correction for semiconductor masks App 20060019202 - Houston; Theodore W. ; et al.	2006-01-26
SRAM with temperature-dependent voltage control in sleep mode Grant 6,982,915 - Houston , et al. January 3, 2	2006-01-03
Staggered memory cell array App 20050281098 - Sadra, Kayvan ; et al.	2005-12-22
Method and apparatus for fabricating self-aligned contacts in an integrated circuit Grant 6,974,968 - Houston December 13, 2	2005-12-13
Statistical evaluation of circuit robustness separating local and global variation App 20050273308 - Houston, Theodore W.	2005-12-08
Sub-lithographics opening for back contact or back gate Grant 6,972,448 - Houston December 6, 2	2005-12-06
Integrated circuit cells Grant 6,954,918 - Houston October 11, 2	2005-10-11
Bit line control for low power in standby App 20050180200 - Houston, Theodore W. ; et al.	2005-08-18
SRAM device and a method of powering-down the same Grant 6,925,025 - Deng , et al. August 2, 2	2005-08-02
Static random access memory device having decreased sensitivity to variations in channel physical characteristics Grant 6,925,010 - Houston August 2, 2	2005-08-02
High performance SRAM device and method of powering-down the same Grant 6,922,370 - Deng , et al. July 26, 2	2005-07-26
Design method and system for optimum performance in integrated circuits that use power management App 20050149887 - Chatterjee, Amitava ; et al.	2005-07-07
SRAM with temperature-dependent voltage control in sleep mode App 20050135175 - Houston, Theodore W. ; et al.	2005-06-23
Static random access memory device having reduced leakage current during active mode and a method of operating thereof App 20050128790 - Houston, Theodore W.	2005-06-16
SRAM device and a method of operating the same to reduce leakage current during a sleep mode App 20050128789 - Houston, Theodore W.	2005-06-16
High Performance Sram Device And Method Of Powering-down The Same App 20050128852 - Deng, Xiaowei ; et al.	2005-06-16
Method of testing an integrated circuit and an integrated circuit test apparatus Grant 6,900,656 - Houston , et al. May 31, 2	2005-05-31
Method Of Testing An Integrated Circuit And An Integrated Circuit Test Apparatus App 20050099202 - Houston, Theodore W. ; et al.	2005-05-12
SRAM device and a method of powering-down the same App 20050094474 - Deng, Xiaowei ; et al.	2005-05-05
Asymmetrical devices for short gate length performance with disposable sidewall Grant 6,873,008 - Houston , et al. March 29, 2	2005-03-29
Multi-gate one-transistor dynamic random access memory App 20050062088 - Houston, Theodore W.	2005-03-24
Asymmetric static random access memory device having reduced bit line leakage App 20050041449 - Houston, Theodore W.	2005-02-24
System for reducing row periphery power consumption in memory devices App 20050036385 - Deng, Xiaowei ; et al.	2005-02-17
System for reducing row periphery power consumption in memory devices App 20050007861 - Deng, Xiaowei ; et al.	2005-01-13
Static random access memory device having decreased sensitivity to variations in channel physical characteristics App 20050007831 - Houston, Theodore W.	2005-01-13
System and method for controlling current in an integrated circuit Grant 6,826,730 - Houston November 30, 2	2004-11-30
Semiconductor apparatus having contacts of multiple heights and method of making same App 20040219759 - Houston, Theodore W. ; et al.	2004-11-04
Integrated DRAM process/structure using contact pillars Grant 6,800,523 - Houston October 5, 2	2004-10-05
Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device App 20040192027 - Houston, Theodore W. ; et al.	2004-09-30
Column voltage control for write Grant 6,791,864 - Houston September 14, 2	2004-09-14
Double pattern and etch of poly with hard mask Grant 6,787,469 - Houston , et al. September 7, 2	2004-09-07
Integrated DRAM process/structure using contact pillars App 20040169217 - Houston, Theodore W.	2004-09-02
Method and apparatus for reducing leakage current in an SRAM array Grant 6,768,144 - Houston , et al. July 27, 2	2004-07-27
Low leakage sram scheme App 20040143769 - Deng, Xiaowei ; et al.	2004-07-22
Column voltage control for write App 20040130930 - Houston, Theodore W.	2004-07-08
Bit line control for low power in standby App 20040130960 - Houston, Theodore W. ; et al.	2004-07-08
Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device Grant 6,750,543 - Houston June 15, 2	2004-06-15
Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device Grant 6,737,347 - Houston , et al. May 18, 2	2004-05-18
Integrated circuit cells Grant 6,734,521 - Houston May 11, 2	2004-05-11
System for reducing power consumption in memory devices Grant 6,735,143 - Houston May 11, 2	2004-05-11
Semiconductor on insulator device architecture and method of construction App 20040087108 - Houston, Theodore W.	2004-05-06
Loadless 4T SRAM cell with PMOS drivers Grant 6,731,533 - Deng , et al. May 4, 2	2004-05-04
Integrated circuit cells App 20040080016 - Houston, Theodore W.	2004-04-29
Integrated circuit cells App 20040083440 - Houston, Theodore W.	2004-04-29
Asymmetrical devices for short gate length performance with disposable sidewall App 20040077138 - Houston, Theodore W. ; et al.	2004-04-22
Integrated DRAM process/structure using contact pillars App 20040061164 - Houston, Theodore W.	2004-04-01
Integrated DRAM process/structure using contact pillars Grant 6,710,391 - Houston March 23, 2	2004-03-23
SOI DRAM having P-doped poly gate for a memory pass transistor Grant 6,703,673 - Houston March 9, 2	2004-03-09
Integrated circuit cells App 20040041228 - Houston, Theodore W.	2004-03-04
Static random access memory cell and method Grant 6,687,145 - Houston February 3, 2	2004-02-03
Self-aligned body contact in a semiconductor device Grant 6,677,190 - Houston January 13, 2	2004-01-13
Integrated Dram Process/structure Using Contact Pillars App 20040000686 - Houston, Theodore W.	2004-01-01
Method and apparatus for fabricating self-aligned contacts in an integrated circuit App 20030203613 - Houston, Theodore W.	2003-10-30
Hydrogen anneal before gate oxidation App 20030203578 - Houston, Theodore W. ; et al.	2003-10-30
Memory cell operation using ramped wordlines Grant 6,639,826 - Houston October 28, 2	2003-10-28
Semiconductor on insulator device architecture and method of construction Grant 6,635,550 - Houston October 21, 2	2003-10-21
Bias cell for four transistor (4T) SRAM operation Grant 6,628,540 - Marshall , et al. September 30, 2	2003-09-30
Etch-stopped SOI back-gate contact App 20030173621 - Houston, Theodore W.	2003-09-18
Memory array and wordline driver supply voltage differential in standby Grant 6,611,451 - Houston August 26, 2	2003-08-26
Semiconductor apparatus having contacts of multiple heights and method of making same App 20030141597 - Houston, Theodore W. ; et al.	2003-07-31
System and method for providing stability for a low power static random access memory cell Grant 6,597,610 - Houston July 22, 2	2003-07-22
Double pattern and etch of poly with hard mask App 20030124847 - Houston, Theodore W. ; et al.	2003-07-03
System for reducing power consumption in memory devices App 20030122201 - Houston, Theodore W.	2003-07-03
Method and apparatus for reducing leakage current in an SRAM array App 20030122160 - Houston, Theodore W. ; et al.	2003-07-03
Dynamic threshold voltage 6T SRAM cell Grant 6,573,549 - Deng , et al. June 3, 2	2003-06-03
Method And Apparatus For Fabricating Self-aligned Contacts In An Integrated Circuit App 20030100159 - Houston, Theodore W.	2003-05-29
Method And Apparatus For Voltage Stiffening In An Integrated Circuit App 20030094642 - Houston, Theodore W. ; et al.	2003-05-22
SRAM with write-back on read Grant 6,552,923 - Houston April 22, 2	2003-04-22
System And Method For Providing Stability For A Low Power Static Random Access Memory Cell App 20030007380 - Houston, Theodore W.	2003-01-09
SOI DRAM having P-doped poly gate for a memory pass transistor App 20020180069 - Houston, Theodore W.	2002-12-05
Instant replay system Grant 6,477,312 - Houston November 5, 2	2002-11-05
Selectively increased interlevel capacitance App 20020149112 - Houston, Theodore W.	2002-10-17
Asymmetrical devices for short gate length performance with disposable sidewall App 20020145154 - Houston, Theodore W. ; et al.	2002-10-10
SPIMOX/SIMOX combination with ITOX option Grant 6,461,933 - Houston October 8, 2	2002-10-08
Refresh at beginning of 4T active cycle App 20020122330 - Houston, Theodore W.	2002-09-05
Partial trench body ties in sram cell App 20020112137 - Houston, Theodore W.	2002-08-15
4T memory with boost of stored voltage between standby and active App 20020105824 - Houston, Theodore W.	2002-08-08
Body-tied-to-source with partial trench App 20020105014 - Houston, Theodore W.	2002-08-08
Bias cell for four transistor (4T) SRAM operation App 20020105825 - Marshall, Andrew ; et al.	2002-08-08
Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device App 20020098672 - Houston, Theodore W.	2002-07-25
SOI DRAM having P-doped polysilicon gate for a memory pass transistor Grant 6,424,016 - Houston July 23, 2	2002-07-23
Stacked vias and method App 20020086519 - Houston, Theodore W. ; et al.	2002-07-04
Means for forming SOI App 20020086463 - Houston, Theodore W. ; et al.	2002-07-04
Static random access memory cell and method App 20020085409 - Houston, Theodore W.	2002-07-04
Sub-lithographics opening for back contact or back gate App 20020086465 - Houston, Theodore W.	2002-07-04
Etch-stopped SOI back-gate contact App 20020084488 - Houston, Theodore W.	2002-07-04
SPIMOX/SIMOX combination with ITOX option App 20020086464 - Houston, Theodore W.	2002-07-04
Method and apparatus for reducing capacitive coupling between lines in an integrated circuit App 20020079587 - Houston, Theodore W.	2002-06-27
Semiconductor on insulator device architecture and method of construction App 20020079537 - Houston, Theodore W.	2002-06-27
Method For Manufacturing A High-frequency Integrated Circuit For Reducing Cross-talk And Facilitating Energy Storage App 20020064928 - Houston, Theodore W.	2002-05-30
Loadless 4T SRAM cell with PMOS drivers App 20020051379 - Deng, Xiaowei ; et al.	2002-05-02
Local Interconnect Structures And Methods App 20020036347 - HOUSTON, THEODORE W	2002-03-28
Hydrogen anneal before gate oxidation App 20020036324 - Houston, Theodore W. ; et al.	2002-03-28
Method of making integrated circuit with closely spaced components Grant 6,362,117 - Houston March 26, 2	2002-03-26
SRAM with write-back on read App 20010052624 - Houston, Theodore W.	2001-12-20
System and method for controlling current in an integrated circuit App 20010047506 - Houston, Theodore W.	2001-11-29
System and method for reducing power dissipation in a circuit Grant 6,307,281 - Houston October 23, 2	2001-10-23
Differential SOI amplifiers having tied floating body connections Grant 6,261,879 - Houston , et al. July 17, 2	2001-07-17
Integrated circuit having dynamic logic with reduced standby leakage current Grant 6,255,853 - Houston July 3, 2	2001-07-03
Process for defining ultra-thin geometries Grant 6,225,175 - Houston May 1, 2	2001-05-01
Self-aligned trenched-channel lateral-current-flow transistor Grant 6,207,511 - Chapman , et al. March 27, 2	2001-03-27
Memory with storage cells having SOI drive and access transistors with tied floating body connections Grant 6,177,300 - Houston , et al. January 23, 2	2001-01-23
Apparatus and method for programmable fast comparison of a result of a logic operation with an selected result Grant 6,114,945 - Houston September 5, 2	2000-09-05
Self-aligned implant under transistor gate Grant 6,074,920 - Houston June 13, 2	2000-06-13
Memory circuits, systems, and methods with cells using back bias to control the threshold voltage of one or more corresponding cell transistors Grant 6,061,267 - Houston May 9, 2	2000-05-09
Self-aligned implant under transistor gate Grant 6,043,535 - Houston March 28, 2	2000-03-28
Differential SOI amplifiers having tied floating body connections Grant 6,037,808 - Houston , et al. March 14, 2	2000-03-14
Tunable threshold SOI device using back gate well Grant 5,942,781 - Burr , et al. August 24, 1	1999-08-24
Memory with storage cells having SOI drive and access transistors with tied floating body connections Grant 5,943,258 - Houston , et al. August 24, 1	1999-08-24
Semiconductor on silicon (SOI) transistor with a halo implant Grant 5,936,278 - Hu , et al. August 10, 1	1999-08-10
Single event upset hardened memory cell Grant 5,905,290 - Houston May 18, 1	1999-05-18
Selective power to memory Grant 5,615,162 - Houston March 25, 1	1997-03-25
Circuit and method for compensating variations in delay Grant 5,600,274 - Houston February 4, 1	1997-02-04
Method and system for screening reliability of semiconductor circuits Grant 5,521,524 - Houston May 28, 1	1996-05-28
Efficient control of the body voltage of a field effect transistor Grant 5,498,882 - Houston March 12, 1	1996-03-12
Capacitor and diode circuitry for on chip power spike detection Grant 5,477,151 - Houston December 19, 1	1995-12-19
Comprehensive logic circuit layout system Grant 5,461,577 - Shaw , et al. October 24, 1	1995-10-24
Synchronous memory with reduced power access mode Grant 5,438,548 - Houston August 1, 1	1995-08-01
Method for forming a semiconductor on insulator device Grant 5,436,173 - Houston July 25, 1	1995-07-25
Method and system for screening logic circuits Grant 5,422,852 - Houston , et al. June 6, 1	1995-06-06
Memory device with end of cycle precharge utilizing write signal and data transition detectors Grant 5,404,327 - Houston April 4, 1	1995-04-04
Pulse generator circuit and method Grant 5,396,110 - Houston March 7, 1	1995-03-07
Temperature compensation circuit and method of operation Grant 5,376,846 - Houston December 27, 1	1994-12-27
On chip bi-stable power-spike detection circuit Grant 5,361,033 - Houston November 1, 1	1994-11-01
Method and system for screening reliability of semiconductor circuits Grant 5,325,054 - Houston June 28, 1	1994-06-28
Digitally controlled delay applied to address decoder for write vs. read Grant 5,313,422 - Houston May 17, 1	1994-05-17
Method for forming a transistor device with resistive coupling Grant 5,310,694 - Houston May 10, 1	1994-05-10
Memory with selective address transition detection for cache operation Grant 5,214,610 - Houston May 25, 1	1993-05-25
Memory circuit with extended valid data output time Grant 5,210,715 - Houston May 11, 1	1993-05-11
Multiple compound domino logic circuit Grant 5,208,489 - Houston May 4, 1	1993-05-04
Transistor device with resistive coupling Grant 5,206,533 - Houston April 27, 1	1993-04-27
Control of sense amplifier latch timing Grant 5,193,076 - Houston March 9, 1	1993-03-09
Method of fabricating a SOI transistor with pocket implant and body-to-source (BTS) contact Grant 5,185,280 - Houston , et al. February 9, 1	1993-02-09
Extended body contact for semiconductor over insulator transistor Grant 5,160,989 - Houston November 3, 1	1992-11-03
On-chip error detection circuit Grant 5,157,335 - Houston October 20, 1	1992-10-20
Chip error detector Grant 5,084,873 - Houston January 28, 1	1992-01-28
Memory having selected state on power-up Grant 5,018,102 - Houston May 21, 1	1991-05-21
Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry Grant 4,980,860 - Houston , et al. December 25, 1	1990-12-25
Column select circuit Grant 4,975,597 - Houston December 4, 1	1990-12-04
Memory cell with increased stability Grant 4,956,815 - Houston September 11, 1	1990-09-11
Memory circuit with extended valid data output time Grant 4,953,130 - Houston August 28, 1	1990-08-28