U.S. patent application number 12/758918 was filed with the patent office on 2011-08-25 for method of making fine-pitch circuit lines.
This patent application is currently assigned to SUBTRON TECHNOLOGY CO., LTD. Invention is credited to Guan-Wei Huang, Chien-Nan WU.
Application Number | 20110204021 12/758918 |
Document ID | / |
Family ID | 44475626 |
Filed Date | 2011-08-25 |
United States Patent
Application |
20110204021 |
Kind Code |
A1 |
WU; Chien-Nan ; et
al. |
August 25, 2011 |
METHOD OF MAKING FINE-PITCH CIRCUIT LINES
Abstract
A method of making fine-pitch circuit lines includes steps of
preparing an insulative substrate, disposing a conductive metal
layer on the insulative substrate, disposing on a whole or a part
of a top surface of the conductive metal layer a hetero layer
having an etching rate smaller than that of the conductive metal
layer, forming a patterned mask of circuit lines on the hetero
layer, wet etching the hetero layer and the conductive metal layer,
and removing the patterned mask and the hetero layer so as to form
fin-pitch circuit lines having a high etching factor on the
insulative substrate.
Inventors: |
WU; Chien-Nan; (Taipei City,
TW) ; Huang; Guan-Wei; (Yunlin County, TW) |
Assignee: |
SUBTRON TECHNOLOGY CO., LTD
Hsin-chu
TW
|
Family ID: |
44475626 |
Appl. No.: |
12/758918 |
Filed: |
April 13, 2010 |
Current U.S.
Class: |
216/20 ; 205/184;
216/13 |
Current CPC
Class: |
C23F 1/44 20130101; C23F
1/14 20130101; C23F 1/02 20130101; H05K 3/06 20130101 |
Class at
Publication: |
216/20 ; 216/13;
205/184 |
International
Class: |
C23F 1/02 20060101
C23F001/02; C25D 5/00 20060101 C25D005/00 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 24, 2010 |
TW |
99105378 |
Claims
1. A method of making fine-pitch circuit lines, comprising the
steps of: preparing an insulative substrate; disposing a conductive
metal layer on the insulative substrate; disposing on a whole or a
part of a top surface of the conductive metal layer a hetero layer
having an etching rate smaller than that of the conductive metal
layer; forming a patterned mask of circuit lines on the hetero
layer; etching the hetero layer and the conductive metal layer with
a liquid etchant, and removing the patterned mask and the hetero
layer.
2. The method as claimed in claim 1, wherein the conductive metal
layer comprises one selected from the group consisting of copper
and a copper alloy.
3. The method as claimed in claim 2, wherein the hetero layer
comprises nickel.
4. The method as claimed in claim 2, wherein the hetero layer
comprises tin.
5. The method as claimed in claim 1, wherein the hetero layer has a
thickness smaller than that of the conductive metal layer.
6. The method as claimed in claim 3, wherein the hetero layer is
disposed on the conductive metal layer by the process selected from
the group consisting of electroplating, chemical vapor deposition
and sputtering.
7. The method as claimed in claim 3, wherein the liquid etchant is
FeCl.sub.3.
8. A method of making fine-pitch circuit lines, comprising the
steps of: preparing an insulative substrate; preparing a laminate
comprising a conductive metal layer and a hetero layer disposed on
the conductive metal layer and having an etching rate smaller than
that of the conductive metal layer, and disposing the laminate on
the insulative substrate in a way that the conductive metal layer
is bonded on the insulative substrate; forming a patterned mask of
circuit lines on the hetero layer of the laminate; etching the
hetero layer and the conductive metal layer with a liquid etchant,
and removing the patterned mask and the hetero layer.
9. The method as claimed in claim 8, wherein the conductive metal
layer comprises one selected from the group consisting of copper
and a copper alloy.
10. The method as claimed in claim 9, wherein the hetero layer
comprises nickel.
11. The method as claimed in claim 10, wherein the liquid etchant
is FeCl.sub.3.
12. The method as claimed in claim 9, wherein the hetero layer
comprises tin.
13. The method as claimed in claim 8, wherein the hetero layer has
a thickness smaller than that of the conductive metal layer.
14. A method of making fine-pitch circuit lines, comprising the
steps of: preparing an insulative substrate; disposing a conductive
metal layer on the insulative substrate; disposing on a top surface
of the conductive metal layer a hetero layer having an etching rate
smaller than that of the conductive metal layer; forming a
patterned mask of circuit lines on the hetero layer; removing the
portion of the hetero layer that is located above a to-be-etched
portion of the conductive metal layer; etching the to-be-etched
portion of the conductive metal layer with a liquid etchant, and
removing the patterned mask and the hetero layer.
15. A method of making fine-pitch circuit lines, comprising the
steps of: preparing an insulative substrate; disposing a conductive
metal layer on the insulative substrate; forming a patterned mask
of circuit lines on the conductive metal layer; disposing on the
portion of a top surface of the conductive metal layer that is
intended not to be etched off a hetero layer having an etching rate
smaller than that of the conductive metal layer; removing the
patterned mask; etching the conductive metal layer with a liquid
etchant, and removing the hetero layer.
16. The method as claimed in claim 15, wherein the liquid etchant
comprises hydrogen peroxide and sulfuric acid.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to a method of
making a printed circuit board (hereinafter referred to as "PCB"),
and more specifically to a method of making a PCB having fine-pitch
circuit lines thereon.
[0003] 2. Description of the Related Art
[0004] Conventionally, integrated circuit chips or electronic
components are mechanically supported by and electrically connected
with a PCB or a wiring substrate for a chip package. For electrical
connection with the chips or the electronic components, the circuit
board or the substrate is provided at the top thereof with circuit
lines forming a specific circuit pattern. It is well known that the
circuit pattern is mainly made by wet etching. In the known
conventional etching methods, the wet etching, which is developed
and adopted by manufacturers long time ago, is nowadays still being
used extensively because of its economic advantage. Basically, the
production of circuit lines involving a wet etching process
includes the steps of disposing a conductive layer on an insulative
substrate, forming an etching resist mask having the desired
circuit lines on the conductive layer, and removing the areas of
the conductive layer that are not protected by the patterned
etching resist mask by a strong acid or alkali liquid etchant so as
to form the desired circuit lines on the substrate.
[0005] Because the liquid etchant used in the wet etching process
has an isotropic etching characteristic, the etchant will not only
attack the target in a vertical direction but also in a transverse
direction, resulting in the so-called undercut phenomenon.
Specifically speaking, if the conductive layer is a copper layer
and the etchant is FeCl.sub.3 for example, the etchant will also
attack the sidewalls of the copper conductive layer that are not
protected by the photoresist in addition to the desired vertical
etching, causing a mushroom defect.
[0006] In practice, the etching quality can be identified by the
so-called etching factor. High etching factor represents that the
pitch between circuit lines is small, such that fine-pitch or
ultra-fine-pitch circuit lines can be realized. FIG. 1 is a
schematic drawing illustrating the etching factor. The so-called
etching factor is defined as an inverse of a value F, i.e. etching
factor is equal to 1/F. While the value F is equal to the equation
of (D1-D2)/2H, i.e. F=(D1-D2)/2H; wherein D1 represents the width
of the bottom of the circuit line, D2 represents the width of the
top of the circuit line and H represents the height of circuit
line, i.e. the thickness of the conductive layer. When the etching
factor is small, the top of the circuit line is narrow and the
bottom is broad. This means that the undercut phenomenon is severe
and the pitch between two adjacent circuit lines is reduced, such
that an electron migration is likely to occur. In addition, the
fine-pitch circuit layout can not be realized due to the sectional
area of the circuit line is not in a rectangular shape
completely.
[0007] To resolve the above-mentioned problems, a solution of
forming a granular copper electrodeposit between a copper foil and
an insulative substrate is disclosed by Saida et al. in U.S. Pat.
No. 5,545,466. According to this patent, the etching factor is
enhanced up to about 8.4 to 9.
SUMMARY OF THE INVENTION
[0008] As discussed above, it is desired to provide a method that
can exactly form fine-pitch circuit lines for a PCB. Therefore, it
is an objective of the present invention to provide a method of
making fine-pitch circuit lines exhibiting a high etching factor on
a PCB substrate or a substrate for a chip package.
[0009] Another objective of the present invention is to provide a
method of making fine-pitch circuit lines exhibiting a high etching
factor even though a conventional etchant is used.
[0010] Still another objective of the present invention is to
provide a method of making fine-pitch circuit lines, which can
reduce the etching time.
[0011] To attain the above-mentioned objectives, the method of
making fine-pitch circuit lines provided by the present invention
comprises the steps of preparing an insulative substrate and then
disposing a conductive metal layer on the insulative substrate,
disposing on a whole or a part of a top surface of the conductive
metal layer a hetero layer having an etching rate smaller than that
of the conductive metal layer, forming a patterned mask of circuit
lines on the hetero layer, performing wet etching, and removing the
patterned mask and the hetero layer so as to form fine-pitch
circuit lines having a high etching factor.
[0012] Another feature of the method of making fine-pitch circuit
lines of the present invention lies in that the conductive metal
layer and the hetero layer may be pre-formed into a laminate and
the laminate my be disposed on the insulative substrate after the
insulative substrate is prepared.
[0013] Still another feature of the method of making fine-pitch
circuit lines of the present invention lies in that the hetero
layer may be disposed on the whole top surface of the conductive
metal layer, and then the portion of the hetero layer that is
located above a to-be-etched portion of the conductive metal layer
is removed after the patterned mask is formed, and the etching
process follows thereafter.
[0014] Still another feature of the method of making fine-pitch
circuit lines of the present invention lies in that the hetero
layer may be disposed on the portion of a top surface of the
conductive metal layer that is intended not to be etched off after
the patterned mask of circuit lines is formed on the top surface of
the conductive metal layer, and then the patterned mask is removed
and the etching process follows thereafter.
[0015] Still another feature of the method of making fine-pitch
circuit lines of the present invention lies in that the thickness
of the hetero layer is smaller than the thickness of the conductive
metal layer. Preferably, the hetero layer may have a thickness of
about 0.4 to 1.2 .mu.m under a condition of that the conductive
metal layer has a thickness of about 8 .mu.m.
[0016] Further scope of applicability of the present invention will
become apparent from the detailed description given hereinafter.
However, it should be understood that the detailed description and
specific examples, while indicating preferred embodiments of the
invention, are given by way of illustration only, since various
changes and modifications within the spirit and scope of the
invention will become apparent to those skilled in the art from
this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention will become more fully understood from
the detailed description given herein below and the accompanying
drawings which are given by way of illustration only, and thus are
not limitative of the present invention, and wherein:
[0018] FIG. 1 is a schematic drawing illustrating the etching
factor for a circuit line;
[0019] FIG. 2 is a schematic drawing showing a step of the method
of making fine-pitch circuit lines according to a first preferred
embodiment of the present invention, in which a conductive metal
layer and a hetero layer are stacked in succession on an insulative
substrate to form a blank PCB;
[0020] FIG. 3 is a schematic drawing showing a wet etching step of
the method of making fine-pitch circuit lines according to the
first preferred embodiment of the present invention, in which a
patterned mask is provided on the blank PCB;
[0021] FIG. 4 is an electron microscope photo showing a sectional
view of a circuit line made by a conventional method of making
circuit lines;
[0022] FIG. 5 is an electron microscope photo showing a sectional
view of a circuit line made by the method of making fine-pitch
circuit lines according to the first preferred embodiment of the
present invention;
[0023] FIG. 6 is a schematic drawing showing a step of the method
of making fine-pitch circuit lines according to a second preferred
embodiment of the present invention, in which a conductive metal
layer is disposed on an insulative substrate and a patterned mask
is disposed on the conductive metal layer;
[0024] FIG. 7 is a schematic drawing showing another step of the
method of making fine-pitch circuit lines according to the second
preferred embodiment of the present invention, in which a hetero
layer is formed on the portion of the conductive layer that is not
covered by the patterned mask; and
[0025] FIG. 8 is a schematic drawing showing an etching step of the
method of making fine-pitch circuit lines according to the second
preferred embodiment of the present invention, in which the
patterned mask is removed.
DETAILED DESCRIPTION OF THE INVENTION
[0026] Referring to FIGS. 2-5, the method of making fine-pitch
circuit lines according to a first preferred embodiment of the
present invention is carried out as follows. First, an insulative
substrate 10 made of polyimide is provided. Thereafter, on the
insulative substrate 10 a copper conductive layer 20 having a
thickness of about 7.97 .mu.m is disposed. And then, a hetero layer
30 having a thickness of about 0.792 .mu.m is disposed on the top
surface of the conductive layer 20 by electroplating, chemical
vapor deposition or sputtering. It is to be noted that the term
"hetero layer" defined in the present invention means that the
layer is made of a material different from the material that the
conductive layer is made of. In this embodiment, the hetero layer
30 can be made of, but not limited to, nickel (Ni) or tin (Sn). On
the other hand, the copper conductive layer 20 and the hetero layer
30 can be pre-formed into a laminate which can be directly disposed
on the insulative substrate 10 after the insulative substrate 10 is
prepared.
[0027] Next, a photoresist (not shown in the drawings) is applied
on the top surface of the hetero layer 30 and exposed and developed
into a patterned mask 40 having a predetermined circuit line
layout. Since the formation of the patterned mask 40 is a
well-known prior art, no more detailed description in this regard
will be presented hereinafter.
[0028] Thereafter, the copper conductive layer 20 and the hetero
layer 30 are etched by a liquid etchant of FeCl.sub.3 under a
specific temperature, for example in a range of 15 to 45.degree. C.
After the circuit lines are formed, the patterned mask 40 is
removed and then the hetero layer 30 is removed by an appropriate
etchant.
[0029] Since the hetero layer 30 made of nickel or tin has an
etching rate smaller than that of the copper conductive layer 20
when a conventional FeCl.sub.3 etchant is used in the method of
making fine-pitch circuit lines of the present invention, the
undercut phenomenon will be minimized because the sidewalls of
etched zone of the copper conductive layer 20 will be protected by
the hetero layer 30. As a result, the etchant can efficiently
attack the target vertically, resulting in that the etching time
can be reduced and on the other hand, the difference between the
width D2 of top of the circuit line and the width D1 of the bottom
of the circuit line can be also reduced, i.e. the etching factor is
increased. As shown in FIG. 5, the width D1, the width D2 and the
height H of the circuit line, i.e. the thickness of the conductive
layer 20, are 8.40 .mu.m, 7.29 .mu.m and 7.97 .mu.m respectively,
resulting in that the etching factor is 14.4. On the other hand,
the circuit line formed by etching a conventional conductive layer
of copper foil has, as shown in FIG. 4, a width D1 of 14.14 .mu.m,
a width D2 of 7.41 .mu.m and a conductive layer thickness of 7.09
.mu.m. Therefore, the etching factor, which is calculated from the
aforesaid parameters, will be 2.2.
[0030] In practice, the method of making fine-pitch circuit lines
according to the first embodiment of the present invention can be
carried out with a step of removing the portion of the hetero layer
30 that is located above the to-be-etched portion of the conductive
layer after the patterned mask is formed on the hetero layer 30,
followed by an etching step.
[0031] Referring to FIGS. 6-8 again, a method of making fine-pitch
circuit lines in accordance with a second preferred embodiment of
the present invention is recited hereinafter. First, an insulative
substrate 60 is provided and then a copper conductive layer 62
having a predetermined thickness is disposed on the substrate 60.
Next, on the top surface of the conductive layer 62 a patterned
mask 64 having a specific circuit line layout is formed. And then,
a hetero layer 70 is disposed on the portion of the top surface of
the conductive layer 62 that is intended not to be etched off, i.e.
the portion of the top surface of the conductive layer 62 that is
not covered by the patterned mask 64, and then the patterned mask
64 is removed. Finally, an etching step using an etchant of a
mixture of hydrogen peroxide and sulfuric acid is carried out and
thereafter the hetero layer 62 is removed so as to form fine-pitch
circuit lines having a high etching factor.
[0032] The invention being thus described, it will be obvious that
the same may be varied in many ways. Such variations are not to be
regarded as a departure from the spirit and scope of the invention,
and all such modifications as would be obvious to one skilled in
the art are intended to be included within the scope of the
following claims.
* * * * *