U.S. patent application number 13/025338 was filed with the patent office on 2011-06-09 for memory cell.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Garo Derderian, Nirmal Ramaswamy.
Application Number | 20110133265 13/025338 |
Document ID | / |
Family ID | 35941836 |
Filed Date | 2011-06-09 |
United States Patent
Application |
20110133265 |
Kind Code |
A1 |
Derderian; Garo ; et
al. |
June 9, 2011 |
MEMORY CELL
Abstract
A memory cell has a tunnel dielectric over a first
silicon-containing material, a second silicon-containing material
over the tunnel dielectric, a first silicon oxide layer on an edge
of the second silicon-containing material and extending across a
first portion of an edge of the tunnel dielectric, and a second
silicon oxide layer on a side of the first silicon-containing
material and extending across a second portion of the edge of the
tunnel dielectric. The first and second silicon oxide layers are
two distinct layers and are in contact with the tunnel dielectric
layer.
Inventors: |
Derderian; Garo; (Boise,
ID) ; Ramaswamy; Nirmal; (Boise, ID) |
Assignee: |
Micron Technology, Inc.
|
Family ID: |
35941836 |
Appl. No.: |
13/025338 |
Filed: |
February 11, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11600357 |
Nov 16, 2006 |
7898017 |
|
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13025338 |
|
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|
10932795 |
Sep 2, 2004 |
7390710 |
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11600357 |
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Current U.S.
Class: |
257/315 ;
257/324; 257/E29.242; 257/E29.3 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 29/42336 20130101; H01L 27/115 20130101 |
Class at
Publication: |
257/315 ;
257/324; 257/E29.242; 257/E29.3 |
International
Class: |
H01L 29/788 20060101
H01L029/788; H01L 29/772 20060101 H01L029/772 |
Claims
1. A memory cell, comprising: a tunnel dielectric over a first
silicon-containing material; a second silicon-containing material
over the tunnel dielectric; a first silicon oxide layer on an edge
of the second silicon-containing material and extending across a
first portion of an edge of the tunnel dielectric; and a second
silicon oxide layer on a side of the first silicon-containing
material and extending across a second portion of the edge of the
tunnel dielectric, wherein the first and second silicon oxide
layers are two distinct layers and are in contact with the tunnel
dielectric layer.
2. The memory cell of claim 1, wherein the first and second silicon
oxide layers comprise oxidized epitaxial silicon.
3. The memory cell of claim 1, wherein the second silicon oxide
layer is in contact with the side of the first silicon-containing
material.
4. The memory cell of claim 1, further comprising another
dielectric over the second silicon-containing material.
5. The memory cell of claim 4, wherein the other dielectric over
the second silicon-containing material comprises nitride on oxide
and another oxide on the nitride.
6. The memory cell of claim 4, further comprising a conductor over
the other dielectric over the second silicon-containing
material.
7. The memory cell of claim 6, wherein the second
silicon-containing material over the tunnel dielectric is
configured to hold a charge.
8. A memory cell, comprising: a tunnel dielectric over a first
silicon-containing material and adjacent to an opening formed in
the first silicon-containing material; a second silicon-containing
material over the tunnel dielectric; a first silicon oxide layer
formed on an edge of the second silicon-containing material and
extending across a first portion of an edge of the tunnel
dielectric; and a second silicon oxide layer formed on an edge of
the opening and extending across a second portion of the edge of
the tunnel dielectric, wherein the first and second silicon oxide
layers are two distinct layers and are in contact with the tunnel
dielectric layer.
9. The memory cell of claim 8, wherein the tunnel dielectric
comprises silicon oxide.
10. The memory cell of claim 8, wherein the second
silicon-containing material is polysilicon.
11. The memory cell of claim 8, further comprising a conductor over
the second silicon-containing material.
12. The memory cell of claim 11, further comprising another
dielectric between the second silicon-containing material and the
conductor.
13. The memory cell of claim 12, wherein the other dielectric
between the second silicon-containing material and the conductor
comprises nitride.
14. The memory cell of claim 8, further comprising another
dielectric within the opening and over the first and second silicon
oxide layers.
15. The memory cell of claim 8, further comprising another
dielectric within the opening that comprises a first dielectric
layer over a portion of the second silicon oxide layer and a second
dielectric layer over the first dielectric layer, the second
dielectric layer further over another portion of the second silicon
oxide layer and the first silicon oxide layer.
16. The memory cell of claim 8, wherein the first silicon oxide
layer comprises oxidized polysilicon and the second silicon oxide
layer comprises oxidized monocrystalline silicon.
17. A memory cell, comprising: a tunnel oxide layer over a first
silicon-containing material; a second silicon-containing material
over the tunnel dielectric; first silicon oxide layers formed on
opposing edges of the second silicon-containing material and
extending across a first portion of opposing edges of the tunnel
oxide layer; and second silicon oxide layers formed on opposing
sides of the first silicon-containing material and extending across
a second portion of the opposing edges of the tunnel oxide layer;
wherein the first silicon oxide layers are distinct from the second
silicon oxide layers; and wherein the first silicon oxide layers
are in contact with the tunnel oxide layer and the second silicon
oxide layers are in contact with the tunnel oxide layer.
18. The memory cell of claim 17, further comprising a dielectric
adjacent to the first and second silicon oxide layers.
19. The memory cell of claim 17, further comprising a first
dielectric adjacent to a first portion of the second silicon oxide
layers and a second dielectric over the first dielectric and
adjacent to a second portion of the second silicon oxide layers and
adjacent to the first silicon oxide layers.
20. The memory cell of claim 17, wherein the first silicon oxide
layer comprises oxidized epitaxial polysilicon and the second
silicon oxide layer comprises oxidized epitaxial monocrystalline
silicon.
Description
RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 11/600,357, titled "FLOATING-GATE MEMORY CELL AND MEMORY DEVICE
AND ELECTRONIC SYSTEM THEREWITH," filed Nov. 16, 2006 (allowed),
which application is a divisional application of U.S. application
Ser. No. 10/932,795, titled "PROTECTION OF TUNNEL DIELECTRIC USING
EPITAXIAL SILICON," filed Sep. 2, 2004, and issued as U.S. Pat. No.
7,390,710 on Jun. 24, 2008. Both applications are assigned to the
assignee of the present invention and are incorporated herein by
reference in their entirety.
FIELD
[0002] The present invention relates generally to semiconductor
memory devices, and in particular, the present invention relates to
the protection of tunnel dielectric layers in the fabrication of
memory cells.
BACKGROUND
[0003] Memory devices are typically provided as internal storage
areas in the computer. The term memory identifies data storage that
comes in the form of integrated circuit chips. In general, memory
devices contain an array of memory cells for storing data, and row
and column decoder circuits coupled to the array of memory cells
for accessing the array of memory cells in response to an external
address.
[0004] One type of memory is a non-volatile memory known as Flash
memory. A flash memory is a type of EEPROM (electrically-erasable
programmable read-only memory) that can be erased and reprogrammed
in blocks. Many modern personal computers (PCs) have their BIOS
stored on a flash memory chip so that it can easily be updated if
necessary. Such a BIOS is sometimes called a flash BIOS. Flash
memory is also popular in wireless electronic devices because it
enables the manufacturer to support new communication protocols as
they become standardized and to provide the ability to remotely
upgrade the device for enhanced features.
[0005] A typical flash memory comprises a memory array that
includes a large number of memory cells arranged in row and column
fashion. Each of the memory cells includes a floating-gate
field-effect transistor capable of holding a charge. The cells are
usually grouped into blocks. Each of the cells within a block can
be electrically programmed in a random basis by charging the
floating gate. The charge can be removed from the floating gate by
a block erase operation. The data in a cell is determined by the
presence or absence of the charge in the floating gate.
[0006] Flash memory typically utilizes one of two basic
architectures known as NOR flash and NAND flash. The designation is
derived from the logic used to read the devices. In NOR flash
architecture, a column of memory cells are coupled in parallel with
each memory cell coupled to a bit line. In NAND flash architecture,
a column of memory cells are coupled in series with only the first
memory cell of the column coupled to a bit line.
[0007] Isolation is typically required or desired between rows or
columns of memory cells. This isolation often takes the form of
shallow trench isolation (STI). STI generally involves forming a
trench between adjacent rows or columns of memory cells and filling
the trench with a dielectric material. However, for trenches formed
adjacent a tunnel dielectric layer of a floating-gate memory cell,
the tunnel dielectric layer may be damaged by oxidation of the fill
material. This damage often takes the form of "smiles" formed at
the edges of the tunnel dielectric layer, effectively reducing the
gate width of the device. Additionally, an etch-back of the fill
material in a two-step fill process may also damage the tunnel
dielectric layer by removing exposed portions at the edges of the
tunnel dielectric layer.
[0008] For the reasons stated above, and for other reasons stated
below which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for alternative memory device structures and
methods of forming memory devices.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a simplified block diagram of a memory system in
accordance with an embodiment of the invention.
[0010] FIG. 2 is a schematic of a NAND memory array in accordance
with an embodiment of the invention.
[0011] FIG. 3 is a schematic of a NOR memory array in accordance
with an embodiment of the invention.
[0012] FIGS. 4A-4E are cross-sectional views of a portion of a
memory array at various stages of fabrication in accordance with
one embodiment of the invention.
[0013] FIGS. 5A-5C are cross-sectional views of a portion of a
memory array at various stages of fabrication in accordance with
another embodiment of the invention.
DETAILED DESCRIPTION
[0014] In the following detailed description of the present
embodiments, reference is made to the accompanying drawings that
form a part hereof, and in which is shown by way of illustration
specific embodiments in which the inventions may be practiced.
These embodiments are described in sufficient detail to enable
those skilled in the art to practice the invention, and it is to be
understood that other embodiments may be utilized and that process,
electrical or mechanical changes may be made without departing from
the scope of the present invention. The terms wafer and substrate
used previously and in the following description include any base
semiconductor structure. Both are to be understood as including
silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)
technology, thin film transistor (TFT) technology, doped and
undoped semiconductors, epitaxial layers of silicon supported by a
base semiconductor, as well as other semiconductor structures well
known to one skilled in the art. Furthermore, when reference is
made to a wafer or substrate in the following description, previous
process steps may have been utilized to form regions/junctions in
the base semiconductor structure. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims and equivalents thereof.
[0015] FIG. 1 is a simplified block diagram of a memory system 100,
according to an embodiment of the invention. Memory system 100
includes an integrated circuit flash memory device 102, e.g., a
NAND memory device, that includes an array of floating-gate memory
cells 104, an address decoder 106, row access circuitry 108, column
access circuitry 110, control circuitry 112, Input/Output (I/O)
circuitry 114, and an address buffer 116. Memory system 100
includes an external microprocessor 120, or memory controller,
electrically connected to memory device 102 for memory accessing as
part of an electronic system. The memory device 102 receives
control signals from the processor 120 over a control link 122. The
memory cells are used to store data that are accessed via a data
(DQ) link 124. Address signals are received via an address link 126
that are decoded at address decoder 106 to access the memory array
104. Address buffer circuit 116 latches the address signals. The
memory cells are accessed in response to the control signals and
the address signals. It will be appreciated by those skilled in the
art that additional circuitry and control signals can be provided,
and that the memory device of FIG. 1 has been simplified to help
focus on the invention. The memory array 104 includes isolation
regions and/or memory cells formed in accordance with the
invention.
[0016] FIG. 2 is a schematic of a NAND memory array 200 as a
portion of memory array 104 of FIG. 1 in accordance with another
embodiment of the invention. As shown in FIG. 2, the memory array
200 includes word lines 202.sub.1 to 202.sub.N and intersecting
local bit lines 204.sub.1 to 204.sub.M. For ease of addressing in
the digital environment, the number of word lines 202 and the
number of bit lines 204 are each some power of two, e.g., 256 word
lines 202 by 4,096 bit lines 204. The local bit lines 204 are
coupled to global bit lines (not shown) in a many-to-one
relationship.
[0017] Memory array 200 includes NAND strings 206.sub.1 to
206.sub.M. Each NAND string includes floating-gate transistors
208.sub.1 to 208.sub.N, each located at an intersection of a word
line 202 and a local bit line 204. The floating-gate transistors
208 represent non-volatile memory cells for storage of data. The
floating-gate transistors 208 of each NAND string 206 are connected
in series source to drain between a source select gate 210, e.g., a
field-effect transistor (FET), and a drain select gate 212, e.g.,
an FET. Each source select gate 210 is located at an intersection
of a local bit line 204 and a source select line 214, while each
drain select gate 212 is located at an intersection of a local bit
line 204 and a drain select line 215.
[0018] A source of each source select gate 210 is connected to a
common source line 216. The drain of each source select gate 210 is
connected to the source of the first floating-gate transistor 208
of the corresponding NAND string 206. For example, the drain of
source select gate 210.sub.1 is connected to the source of
floating-gate transistor 208.sub.1 of the corresponding NAND string
206.sub.1. A control gate 220 of each source select gate 210 is
connected to source select line 214.
[0019] The drain of each drain select gate 212 is connected to a
local bit line 204 for the corresponding NAND string at a drain
contact 228. For example, the drain of drain select gate 212.sub.1
is connected to the local bit line 204.sub.1 for the corresponding
NAND string 206.sub.1 at drain contact 228.sub.1. The source of
each drain select gate 212 is connected to the drain of the last
floating-gate transistor 208 of the corresponding NAND string 206.
For example, the source of drain select gate 212.sub.1 is connected
to the drain of floating-gate transistor 208.sub.N of the
corresponding NAND string 206.sub.1.
[0020] Typical construction of floating-gate transistors 208
includes a source 230 and a drain 232, a floating gate 234, and a
control gate 236, as shown in FIG. 2. Floating-gate transistors 208
have their control gates 236 coupled to a word line 202. A column
of the floating-gate transistors 208 are those NAND strings 206
coupled to a given local bit line 204. A row of the floating-gate
transistors 208 are those transistors commonly coupled to a given
word line 202.
[0021] FIG. 3 is a schematic of a NOR memory array 300 as a portion
of memory array 104 of FIG. 1 in accordance with another embodiment
of the invention. Memory array 300 includes word lines 302.sub.1 to
302.sub.P and intersecting local bit lines 304.sub.1 to 304.sub.Q.
For ease of addressing in the digital environment, the number of
word lines 302 and the number of bit lines 304 are each some power
of two, e.g., 256 word lines 302 by 4,096 bit lines 304. The local
bit lines 304 are coupled to global bit lines (not shown) in a
many-to-one relationship.
[0022] Floating-gate transistors 308 are located at each
intersection of a word line 302 and a local bit line 304. The
floating-gate transistors 308 represent non-volatile memory cells
for storage of data. Typical construction of such floating-gate
transistors 308 includes a source 310 and a drain 312, a floating
gate 314, and a control gate 316.
[0023] Floating-gate transistors 308 having their control gates 316
coupled to a word line 302 typically share a common source depicted
as array source 318. As shown in FIG. 3, floating-gate transistors
308 coupled to two adjacent word lines 302 may share the same array
source 318. Floating-gate transistors 308 have their drains 312
coupled to a local bit line 304. A column of the floating-gate
transistors 308 includes those transistors commonly coupled to a
given local bit line 304. A row of the floating-gate transistors
308 includes those transistors commonly coupled to a given word
line 302.
[0024] To reduce problems associated with high resistance levels in
the array source 318, the array source 318 is regularly coupled to
a metal or other highly conductive line to provide a low-resistance
path to ground. The array ground 320 serves as this low-resistance
path.
[0025] FIGS. 4A-4E generally depict a method of forming a portion
of a memory array in accordance with one embodiment of the
invention. FIG. 4A depicts a portion of the memory array after
several processing steps have occurred. Formation of the type of
structure depicted in FIG. 4A is well known and will not be
detailed herein. In general, FIG. 4A depicts a silicon-containing
substrate 400 upon which tunnel dielectric layer 405, a
silicon-containing layer 410 and a hard mask layer 415 have been
formed. For one embodiment, the substrate 400 is a monocrystalline
silicon substrate. For a further embodiment, substrate 400 is a
P-type monocrystalline silicon substrate. The silicon-containing
layer 410 is preferably a polysilicon (polycrystalline silicon)
layer, but could also include other forms of doped or undoped
silicon materials, such as monocrystalline silicon, nanocrystalline
silicon and amorphous silicon. For convenience, the
silicon-containing layer 410 will be referred to as polysilicon
layer 410 in the following description.
[0026] The tunnel dielectric layer 405 is formed overlying an
active region of the substrate 400, over which memory cells will be
formed. Isolation regions 420 are formed in the substrate 400. For
the embodiment as shown in FIG. 4A, the isolation regions are
shallow-trench isolation (STI) regions, commonly formed by creating
a trench in the substrate 400 and filling the trench with a
dielectric material. The isolation regions 420 would generally be
formed after forming the layers 405, 410 and 415. Typical process
for forming isolation regions 420 could utilize photolithographic
processing including depositing, exposing and developing a
photoresist material to define areas for the isolation regions 420,
and then removing the layers 405, 410 and 415, as well as a portion
of the substrate 400, in those areas.
[0027] The tunnel dielectric layer 405 might be formed by thermal
oxidation of the silicon substrate 400. Alternatively, the tunnel
dielectric layer 405 could be formed by a blanket deposition of a
dielectric material, such as by chemical vapor deposition (CVD) or
physical vapor deposition (PVD). Tunnel dielectric layer 405 is
generally a silicon oxide, but may include other dielectric
materials.
[0028] The polysilicon layer 410 may be used to form a portion of a
floating-gate layer for the future floating-gate memory cells. The
polysilicon layer 410 may be conductively doped either during or
after formation. The hard mask layer 415 is formed overlying the
polysilicon layer 410 to protect its upper surface during
subsequent processing. In general, hard mask layer 415 is of a
material that will be substantially resistant to formation of
epitaxial silicon. For one embodiment, the hard mask layer 415 is a
silicon nitride material.
[0029] In FIG. 4B, epitaxial silicon layers 425 and 430 are formed.
Epitaxial silicon growth will be selective to areas of exposed
silicon, such as the exposed portions of the substrate 400 and the
polysilicon layer 410. Such selective growth will produce the
layers of epitaxial silicon 425 and 430 on the polysilicon layer
410 and substrate 400, respectively. Because the epitaxial silicon
growth will occur both horizontally and vertically, the layers of
epitaxial silicon 425 and 430 will grow across the edges of the
tunnel dielectric layer 405. In this manner, the thickness of
growth of the layers of epitaxial silicon 425 and 430 need only be
approximately one-half the thickness of the tunnel dielectric layer
405 in order to completely cover the edges.
[0030] Epitaxial deposition of silicon is a chemical vapor
deposition (CVD) process. The process will replicate the structure
of the silicon material upon which it is formed. For example, if
the base structure is of monocrystalline silicon, the epitaxial
growth will maintain the same monocrystalline structure. Similarly,
if the base structure is of polycrystalline silicon (polysilicon),
the epitaxial growth will likewise be polysilicon. Silicon
precursors are transported to, and adsorbed on, the exposed silicon
structures. Common silicon precursors for the production of
epitaxial silicon include silicon tetrachloride (SiCl.sub.4),
trichlorosilane (SiHCl.sub.3), dichlorosilane (SiH.sub.2Cl.sub.2)
and silane (SiH.sub.4).
[0031] The process of epitaxial silicon growth is well understood
in the art. Typical deposition temperatures range from about
600.degree. C. to about 1250.degree. C. Thickness of the epitaxial
growth is typically controlled through reaction time, or time that
the silicon structures are exposed to the reactant gases and their
reaction conditions. Typical reaction times may range from about 1
minute to about 15 minutes or more, depending upon the desired
depth of deposition.
[0032] Selective epitaxial deposition occurs when silicon atoms
having high surface mobility are deposited from the silicon source
or precursor. These silicon atoms migrate to sites on exposed
silicon structures, where nucleation is favored. Others have
observed that silicon mobility is enhanced by the presence of
halides in the reaction gases. Other factors recognized to enhance
the selective nature of the silicon deposition include reduced
reaction pressure, increased reaction temperature and decreased
mole fraction of silicon in the reaction gases.
[0033] In FIG. 4C, the layers of epitaxial silicon 425 and 430 are
oxidized, such as by thermal oxidation, to form layers of silicon
oxide 435 and 440, respectively. Because the layers of epitaxial
silicon 425 and 430 were formed to cover the edges of the tunnel
dielectric layer 405, oxidation of the tunnel dielectric layer 405
will be limited in comparison to an oxidation of the exposed
portions of the substrate 400 in the isolation regions 420 had the
layers of epitaxial silicon 425 and 430 not been present.
[0034] In FIG. 4D, the isolation regions 420 are filled with a
dielectric material or dielectric fill layer 445, e.g., a
high-density plasma (HDP) oxide material, spin-on dielectric (SOD)
material or other dielectric fill. If necessary, a portion of the
dielectric fill layer 445 may be removed, such as by
chemical-mechanical planarization (CMP) to obtain the structure as
shown in FIG. 4D. Because the layers of epitaxial silicon 425 and
430 can be formed at very low thicknesses, e.g., if the tunnel
dielectric layer is 80 .ANG., the epitaxial growth can be as low as
40 .ANG., and because the layers of epitaxial silicon 425 and 430
are not formed at the top of the isolation regions 420, the layers
of epitaxial silicon 425 and 430 do not significantly impact the
ability to fill the isolation regions 420 with dielectric
material.
[0035] In FIG. 4E, the fabrication of the memory cells can be
completed using techniques well understood in the art. While the
polysilicon layer 410 may be used as a floating-gate layer of a
floating-gate memory cell, it is generally desirable to increase
its volume as well as its coupling area. As such, a second
polysilicon layer 450 may optionally be formed overlying the
polysilicon layer 410, with the polysilicon layer 410 and second
polysilicon layer 450 collectively forming the floating-gate layer
of a memory cell. An intergate dielectric layer 455 is then formed
overlying this floating-gate layer. The intergate dielectric layer
455 may be one or more layers of dielectric material. For example,
the intergate dielectric layer 455 could be of a multi-layer
dielectric material commonly referred to as ONO
(oxide-nitride-oxide). Other dielectric materials may be
substituted for the ONO, such as tantalum oxide, barium strontium
titanate, silicon nitride and other materials providing dielectric
properties.
[0036] The control gate layer 460 is formed overlying the intergate
dielectric layer 456 and patterned to define word lines of the
memory device. The control gate layer 460 is generally one or more
layers of conductive material. For one embodiment, the control gate
layer 460 contains a conductively-doped polysilicon. For a further
embodiment, the control gate layer 460 includes a metal-containing
layer overlying a polysilicon layer, e.g., a refractory metal
silicide layer formed on a conductively-doped polysilicon layer.
The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum
(Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W),
vanadium (V) and zirconium (Zr) are generally recognized as
refractory metals. For another embodiment, the control gate layer
460 contains multiple metal-containing layers, e.g., a titanium
nitride (TiN) barrier layer overlying the intergate dielectric
layer 456, a titanium (Ti) adhesion layer overlying the barrier
layer and a tungsten (W) layer overlying the adhesion layer. An
insulative cap layer (not shown) is often formed overlying the
control gate layer 460 to protect and isolate the control gate from
further processing.
[0037] It is noted that FIGS. 4A-4E depict a portion of a row of
memory cells running parallel to a face plane of the drawings.
Columns of memory cells, separated by the isolation regions 420 run
perpendicular to the drawings, with source and drain regions formed
at opposing ends of the tunnel dielectric layer 405, one above the
face plane of the figures and one below the face plane of the
figures. It is noted that FIGS. 4A-4E can depict either a NOR-type
memory device or a NAND-type memory device, with the differences
occurring in the column direction in manners that are well
understood in the art of memory fabrication.
[0038] FIGS. 5A-5C generally depict a method of forming a portion
of a memory array in accordance with another embodiment of the
invention. The method described with reference to FIGS. 5A-5C is
useful for processes requiring a two-step fill process. In
particular, for trenches having high aspect ratios (depth/width),
undesirable voids may be formed in the trench due to pinch-off at
the top of the trench during the formation of the dielectric fill
material. To rectify this situation, the top portion of the fill
layer is often removed, such as by a wet etch, to expose or remove
the void. This results in a trench having a lower aspect ratio,
allowing the trench to be filled during the formation of a second
layer of dielectric fill material. While silicon oxide layers can
be protected during the removal of a silicon oxide fill material by
first lining the trench with a silicon nitride material, this
solution is undesirable in floating-gate memory cells as the
silicon nitride liner acts as a charge trapping layer and can
interfere with the reliability of the floating-gate device.
[0039] FIG. 5A depicts a portion of the memory array after several
processing steps have occurred. Formation of the type of structure
depicted in FIG. 5A can proceed generally as described with
reference to FIGS. 4A-B. However, instead of oxidizing the layers
of epitaxial silicon 425 and 430 as described with reference to
FIG. 4C, the isolation regions 420 are filled with a dielectric
material or first dielectric fill layer 550, e.g., a high-density
plasma (HDP) oxide material, spin-on dielectric (SOD) material or
other dielectric fill, without oxidizing the layers of epitaxial
silicon 425 and 430.
[0040] In FIG. 5B, an upper portion of the first dielectric fill
layer 550 is removed, such as by an etch-back process. The removal
process is chosen to be selective to the removal of the first
dielectric fill layer 550 over the removal of epitaxial silicon.
For example, using a silicon oxide fill material, a wet etch
containing HF (hydrofluoric acid) can be used to remove an exposed
portion of the silicon oxide material without significantly
affecting the layers of epitaxial silicon 425 and 430.
[0041] In FIG. 5C, the isolation regions 420 are filled with a
dielectric material or second dielectric fill layer 555, e.g., a
high-density plasma (HDP) oxide material, spin-on dielectric (SOD)
material or other dielectric fill. The second dielectric fill layer
555 may contain the same dielectric material or a different
dielectric material than the first dielectric fill layer 550.
Portions of the layers of epitaxial silicon 425 and 430 exposed
following the removal of a portion of the first dielectric fill
layer 550 should be oxidized either before, or concurrently with,
the formation of the second dielectric fill layer 555. If
necessary, a portion of the second dielectric fill layer 555 may be
removed, such as by chemical-mechanical planarization (CMP) to
obtain the structure as shown in FIG. 5C. Further processing to
form memory cells can occur as generally described with reference
to FIG. 4E.
CONCLUSION
[0042] Layers of epitaxial silicon are used to protect the tunnel
dielectric layer of a floating-gate memory cell from excessive
oxidation or removal during the formation of shallow trench
isolation (STI) regions. Following trench formation, the layers of
epitaxial silicon are grown from silicon-containing layers on
opposing sides of the tunnel dielectric layer, thereby permitting
their thickness to be limited to approximately one-half of the
thickness of the tunnel dielectric layer. The epitaxial silicon may
be oxidized prior to filling the trench with a dielectric material
or a dielectric fill may occur prior to oxidizing at least the
epitaxial silicon covering the ends of the tunnel dielectric
layer.
[0043] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement that is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
Many adaptations of the invention will be apparent to those of
ordinary skill in the art. Accordingly, this application is
intended to cover any adaptations or variations of the invention.
It is manifestly intended that this invention be limited only by
the following claims and equivalents thereof.
* * * * *