U.S. patent application number 12/958329 was filed with the patent office on 2011-06-02 for chip package and fabrication method thereof.
Invention is credited to Chia-Ming Cheng, Nan-Chun Lin, Ching-Yu NI.
Application Number | 20110127681 12/958329 |
Document ID | / |
Family ID | 44068251 |
Filed Date | 2011-06-02 |
United States Patent
Application |
20110127681 |
Kind Code |
A1 |
NI; Ching-Yu ; et
al. |
June 2, 2011 |
CHIP PACKAGE AND FABRICATION METHOD THEREOF
Abstract
A chip package and a fabrication method thereof are provided
according to an embodiment of the invention. The chip package
includes a semiconductor substrate containing a chip and having a
device area and a peripheral bonding pad area. A plurality of
conductive pads is disposed at the peripheral bonding pad area and
a passivation layer is formed over the semiconductor substrate to
expose the conductive pads. An insulating protective layer is
formed on the passivation layer at the device area. A packaging
layer is disposed over the insulating protective layer to expose
the conductive pads and the passivation layer at the peripheral
bonding pad area. The method includes forming an insulating
protective layer to cover a plurality of conductive pads during a
cutting process and removing the insulating protective layer on the
conductive pads through an opening of a packaging layer.
Inventors: |
NI; Ching-Yu; (Hsinchu City,
TW) ; Cheng; Chia-Ming; (Xinzhuang City, TW) ;
Lin; Nan-Chun; (Zhonghe City, TW) |
Family ID: |
44068251 |
Appl. No.: |
12/958329 |
Filed: |
December 1, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61265708 |
Dec 1, 2009 |
|
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|
Current U.S.
Class: |
257/786 ;
257/E21.506; 257/E23.02; 438/612 |
Current CPC
Class: |
H01L 2224/05624
20130101; H01L 23/3114 20130101; H01L 2924/1461 20130101; H01L
2924/15788 20130101; H01L 2924/01013 20130101; H01L 24/06 20130101;
H01L 2224/05647 20130101; H01L 23/498 20130101; H01L 2924/16195
20130101; H01L 23/3192 20130101; H01L 2924/01029 20130101; H01L
2924/16235 20130101; H01L 2224/05624 20130101; H01L 2924/01033
20130101; H01L 21/78 20130101; H01L 2924/01014 20130101; H01L
2924/1461 20130101; H01L 2924/05042 20130101; H01L 2224/05647
20130101; H01L 2924/14 20130101; H01L 2924/014 20130101; H01L
2924/15788 20130101; H01L 2924/01082 20130101; H01L 2924/00
20130101; H01L 2924/00014 20130101; H01L 2924/00 20130101; H01L
2924/00014 20130101 |
Class at
Publication: |
257/786 ;
438/612; 257/E23.02; 257/E21.506 |
International
Class: |
H01L 23/485 20060101
H01L023/485; H01L 21/60 20060101 H01L021/60 |
Claims
1. A chip package, comprising: a semiconductor substrate, having a
device area and a peripheral bonding pad area, wherein the
peripheral bonding pad area surrounds the device area; a plurality
of conductive pads disposed at the peripheral bonding pad area of
the semiconductor substrate; a chip passivation layer disposed over
the semiconductor substrate and exposing the conductive pads; an
insulating protective layer disposed over the device area; and a
packaging layer disposed on the insulating protective layer and
exposing the conductive pads.
2. The chip package as claimed in claim 1, wherein the insulating
protective layer covers the device area, not reaching to the
peripheral bonding pad area, and the conductive pads and the chip
passivation layer at the peripheral bonding pad area are exposed by
the packaging layer.
3. The chip package as claimed in claim 1, further comprising a
spacer disposed between the packaging layer and the insulating
protective layer.
4. The chip package as claimed in claim 1, further comprising a
cavity formed between the packaging layer and the insulating
protective layer, wherein the cavity is surrounded by the
spacer.
5. The chip device package as claimed in claim 1, wherein the
material of the insulating protective layer is different from the
material of the chip passivation layer.
6. The chip device package as claimed in claim 5, wherein the
material of the chip passivation layer comprises silicon nitride
and the material of the insulating protective layer comprises
silicon oxide.
7. The chip package as claimed in claim 5, wherein the material of
the insulating protective layer comprises a photosensitive
insulating material.
8. The chip package as claimed in claim 4, wherein a portion of the
insulating protective layer under the spacer has hardness which is
greater than that of other portions of the insulating protective
layer.
9. The chip package as claimed in claim 5, wherein the packaging
layer comprises a transparent substrate or a semiconductor
substrate.
10. A method for fabricating a chip package, comprising: providing
a semiconductor wafer, containing a plurality of device areas and a
peripheral bonding pad area disposed between any two adjacent
device areas, wherein the peripheral bonding pad area includes a
plurality of conductive pads, and a chip passivation layer covering
the semiconductor wafer and exposing the conductive pads; forming
an insulating protective layer on the chip passivation layer,
covering the conductive pads; providing a packaging layer; bonding
the semiconductor wafer with the packaging layer; patterning the
packaging layer to form a plurality of openings, exposing the
insulating protective layer at the peripheral bonding pad area; and
using the packaging layer as a hard mask to remove the insulating
protective layer at the peripheral bonding pad area, exposing the
conductive pads.
11. The method as claimed in claim 10, wherein the step of
patterning the packaging layer comprises a cutting process and
wherein during the cutting process, the conductive pads are covered
with the insulating protective layer.
12. The method as claimed in claim 11, wherein the step of removing
the insulating protective layer comprises an etching process.
13. The method as claimed in claim 10, wherein the material of the
insulating protective layer is different from the material of the
chip passivation layer.
14. The method as claimed in claim 13, wherein the material of the
chip passivation layer comprises silicon nitride and the material
of the insulating protective layer comprises silicon oxide.
15. The method as claimed in claim 10, wherein the material of the
insulating protective layer comprises a photosensitive insulating
material.
16. The method as claimed in claim 10, further comprising; forming
a spacer between the packaging layer and the insulating protective
layer; and forming a cavity between the packaging layer and the
insulating protective layer, wherein the cavity is surrounded by
the spacer.
17. The method as claimed in claim 16, further comprising
performing an exposure process to the photosensitive insulating
material, wherein a portion of the photosensitive insulating
material disposed under the spacer are exposed to an exposure
extent smaller than that of other portions of the photosensitive
insulating material.
18. The method as claimed in claim 17, wherein the portion of the
insulating protective layer disposed under the spacer has hardness
which is greater than that of the other portions of the insulating
protective layer.
19. The method as claimed in claim 16, wherein the packaging layer
comprises a transparent substrate or a semiconductor substrate.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 61/265,708, filed on Dec. 1, 2009, the entirety of
which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a chip package, and in
particular relates to a chip package which can protect conductive
pads from damage during a cutting process and a redistribution
stack layer and a fabrication method thereof.
[0004] 2. Description of the Related Art
[0005] Wafer level packaging technology has been developed for
packaging chips. After a wafer level package is completed, a
cutting process is performed between chips to separate the chips
from each other.
[0006] However, when using a cutter to form an opening between the
chips in the cutting process, a lot of chipping is produced. The
chippings damage and scratch bonding pads of the chip during the
cutting process, such that the reliability of wire bonding of the
chip package is reduced following subsequent processes and the
electrical property of the conventional chip package is poor.
[0007] Thus, a chip package which can mitigate the above mentioned
problems and prevent the conductive pads of chips from damage
during a cutting process is desired.
BRIEF SUMMARY OF THE INVENTION
[0008] According to an illustrative embodiment, a chip package is
provided. The chip package comprises a semiconductor substrate
containing a chip, having a device area and a peripheral bonding
pad area. A plurality of conductive pads is disposed at the
peripheral bonding pad area. A chip passivation layer is disposed
over the semiconductor substrate, exposing the conductive pads. An
insulating protective layer is disposed over the device area and a
packaging layer is disposed over the insulating protective layer,
exposing the conductive pads.
[0009] According to another illustrative embodiment, a method for
fabricating a chip package is provided. The method comprises
providing a semiconductor wafer containing a plurality of device
areas and a peripheral bonding pad area disposed between any two
adjacent device areas, wherein the peripheral bonding pad area
includes a plurality of conductive pads, and a chip passivation
layer covering the semiconductor wafer, exposing the conductive
pads. An insulating protective layer is formed on the chip
passivation layer, covering the conductive pads. A packaging layer
is provided and the semiconductor wafer is bonded to the packaging
layer. The packaging layer is patterned to form a plurality of
openings to expose the insulating protective layer at the
peripheral bonding pad area. Then, the insulating protective layer
at the peripheral bonding pad area is removed to expose the
conductive pads by using the packaging layer as a hard mask.
[0010] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The present invention can be more fully understood by
reading the subsequent detailed description and examples with
references made to the accompanying drawings, wherein:
[0012] FIGS. 1A-1F are illustrative cross sections showing the
steps for fabricating a chip package according to an embodiment of
the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0013] The following description is of a mode for carrying out the
invention. This description is made for the purpose of illustrating
the general principles of the invention and should not be taken in
a limiting sense. The scope of the invention is best determined by
reference to the appended claims. Wherever possible, the same
reference numbers are used in the drawings and the descriptions to
refer the same or like parts. In the drawings, the size of some of
the elements may be exaggerated and not drawn to scale for
illustrative purposes. The dimensions and the relative dimensions
do not correspond to actual dimensions to practice of the
invention. Further, parts of the elements in the drawings are
illustrated by the following description. Some elements not shown
in the drawings are known by one skilled the art.
[0014] The embodiments of chip packages of the invention and
fabrication methods thereof are illustrated by embodiments of
fabricating image sensor packages in the following description.
However, it should be appreciated that the invention may also be
applied to forming other semiconductor chip packages. Therefore,
the packages of the embodiments of the invention may be applied to
active or passive devices, or electronic components with digital or
analog circuits, such as optoelectronic devices, micro electro
mechanical systems (MEMS), micro fluidic systems, and physical
sensors for detecting heat, light, or pressure. Particularly, a
wafer scale package (WSP) process may be applied to package
semiconductor chips, such as image sensors, solar cells, RF
circuits, accelerators, gyroscopes, micro actuators, surface
acoustic wave devices, pressure sensors, and ink printer heads.
[0015] The wafer level packaging process herein mainly means that
after the packaging process is accomplished during a wafer stage, a
wafer with chips is cut to obtain separate independent packages.
However, in an embodiment of the invention, separate independent
chips may be redistributed overlying a supporting wafer and then be
packaged, which may also be referred to as a wafer level packaging
process. In addition, the wafer level packaging process may also be
adapted to form chip packages of multi-layered integrated circuit
devices by stacking a plurality of wafers having integrated
circuits together.
[0016] An embodiment of the invention provides a chip packages and
a fabrication method thereof. After a wafer level package of the
above mentioned devices is completed and the devices are separated
from each other to form separate independent chip packages by a
cutting process, the conductive pads of the chip packages are
protected to prevent from damage by residues produced from the
cutting process, or scratching the conductive pads.
[0017] Referring to FIGS. 1A-1F, cross sections illustrating the
steps for fabricating a chip package according to an embodiment of
the invention are shown. As shown in FIG. 1A, first, a
semiconductor wafer 100 containing a plurality of chips is
provided. The semiconductor substrate 100 has a plurality of device
areas 100A and a peripheral bonding pad area 100B disposed between
any two adjacent device areas 100A. A plurality of conductive pads
104 is disposed at the peripheral bonding pad area 100B. Moreover,
in general, the semiconductor wafer 100 is covered with a chip
passivation layer 106 when it is produced from a semiconductor
wafer factory. The chip passivation layer 106 may be a silicon
nitride layer. Meanwhile, in order to electrically connect the
devices of the chip to external circuits, the chip passivation
layer 106 is defined by the semiconductor wafer factory to form a
plurality of openings beforehand to expose conductive pads 104
therein.
[0018] Next, referring to FIG. 1B, an insulating protective layer
108 is formed on the overall surface of the semiconductor wafer 100
to cover the chip passivation layer 106 and the conductive pads
104. The material of the insulating protective layer 108 is
different from the material of the chip passivation layer 106. The
insulating protective layer 108 may be a silicon oxide layer formed
by a chemical vapor deposition method.
[0019] Then, referring to FIG. 1C, a packaging layer 200 is
provided to bond with the semiconductor wafer 100. The packaging
layer 200 may be a glass substrate or another blank silicon wafer.
In an embodiment, the packaging layer 200 is separated from the
semiconductor wafer 100 by a spacer 110 and thereby a cavity 116
surrounded by the spacer 110 is formed. The spacer 100 may be a
sealant or a photosensitive insulating material, such as epoxy
resin, solder mask materials, etc. Moreover, the spacer 100 may be
firstly formed on the insulating protective layer 108 and then
bonded to the packaging layer 200 through an adhesive layer (not
shown). On the other hand, the spacer 100 may be firstly formed on
the packaging layer 200 and then bonded to the insulating
protective layer 108 through an adhesive layer (not shown).
[0020] Referring to FIG. 1D, in a cutting process, a cutter knife
(not shown) is used to form openings 114 in the packaging layer 200
to expose the surface of the peripheral bonding pad area 100B.
Meanwhile, chipping 118, formed from the cutting process, for
example glass or silicon wafer chipping, fall down onto the
insulating protective layer 108. Because the conductive pads 104
are covered with the insulating protective layer 108, the
conductive pads 104 are prevented from damage or scratching by the
chipping 118 during the cutting process.
[0021] Next, referring to FIG. 1E, at least a portion of the
insulating protective layer 108 at the peripheral bonding pad area
100B is removed through the openings 114 of the packaging layer
200. Thus, the conductive pads 104 and the chip passivation layer
106 are exposed to subsequently form electrical connections between
the conductive pads 104 and external circuits. Meanwhile, the
residual insulating protective layer 108 covers all of the device
area 100A surrounded by the spacer 110. In the embodiment, the
insulating protective layer 108 may be a non-photosensitive
insulating material, such as silicon oxides. Accordingly, the
packaging layer 200 having the openings 114 can be used as a hard
mask, and the insulating protective layer 108 at the peripheral
bonding pad area 100B can be removed by an etching process.
Therefore, there is no need to use an extra photolithography
process to form a patterned photoresist as a mask in the embodiment
of the invention. Moreover, the material of the insulating
protective layer 108 is different from the material of the chip
passivation layer 106, such that the chip passivation layer 106 can
be used as an etch stop layer for the insulating protective layer
108. In another embodiment, the insulating protective layer 108 at
the peripheral bonding pad area 100B can be defined by a
photolithography process to form openings to expose the conductive
pads 104.
[0022] In addition, the insulating protective layer 108 can be
selected from a photosensitive material and an exposure process is
performed to the insulating protective layer 108. Then, a
development process is performed to remove the insulating
protective layer 108 at the peripheral bonding pad area 100B
through the openings 114 of the packaging layer 200. In the
embodiment, the material of the spacer 100 is an opaque material. A
portion of the insulating protective layer 108a disposed under the
spacer 110 is not exposed or an exposure extent thereof is smaller
than other portions of the insulating protective layer, such that
the portion of insulating protective layer 108a disposed under the
spacer 110 has hardness which is greater than the hardness of other
portions of the insulating protective layer 108a; for example the
portions of the insulating protective layer 108a disposed under the
cavity 116, which is exposed but not developed. Therefore, the
mechanical strength of the structure below the spacer 110 is
enhanced.
[0023] Moreover, because the adhesion between the spacer 110 and
the material of silicon oxides is greater than the adhesion between
the spacer 110 and the material of silicon nitrides, in the
embodiments of the invention, the interface adhesion between the
spacer 110 and the chip passivation layer 106 made of silicon
nitrides is less than the interface adhesion between the spacer 110
and the insulating protective layer 108a made of silicon oxides.
Thus, the extra insulating protective layer 108a formed from
silicon oxide can improve reliability of chip packages.
[0024] Next, referring to FIGS. 1E and 1F, the semiconductor wafer
100 is divided along a scribe line 112 at the peripheral bonding
pad area 100B to form a plurality of separated independent chip
packages as shown in FIG. 1F.
[0025] Referring to FIG. 1F, a cross section of a chip package
according to an embodiment of the invention is shown. The
semiconductor wafer is divided along the scribe line 112 to form
the chip packages 102. The semiconductor substrate 100 of the chip
package 102 is, for example formed from dicing the semiconductor
wafer containing the chips. The semiconductor substrate 100 can be
divided into the device area 100A and the peripheral bonding pad
area 100B, wherein the device area 100A is surrounded by the
peripheral bonding pad area 100B.
[0026] The peripheral bonding pad area 100B of the semiconductor
substrate 100 has a plurality of conductive pads 104 thereon. The
conductive pad 104 is, for example a bonding pad, which is
electrically connected to the inner portion of the chip through
metal interconnects (not shown). The surface of the semiconductor
substrate 100 is covered with the chip passivation layer 106; for
example a layer made of silicon nitrides or silicon oxynitrides.
The conductive pads 104 are exposed by the chip passivation layer
106 and can be electrically connected to an external circuit by a
wire bonding method. The chip passivation layer 106 disposed at the
device area 100A is covered with the insulating protective layer
108a; for example a layer made of silicon oxides. In addition, the
packaging layer 200 is further disposed on the insulating
protective layer 108a.
[0027] In an embodiment, the chip packages can be applied to, but
are not limited to, image sensor devices, such as complementary
metal oxide semiconductor (CMOS) devices or charge-couple devices
(CCD). Moreover, the chip packages can also be applied to micro
electro mechanical system (MEMS) devices.
[0028] It is preferable that the conductive pads 104 are formed
from copper (Cu), aluminum (Al) or other suitable metal materials.
The spacer 110 can be disposed between the packaging layer 200 and
the semiconductor substrate 100 to form the cavity 116 between the
packaging layer 200 and the semiconductor substrate 100, wherein
the cavity 116 is surrounded by the spacer 110.
[0029] In an embodiment, the packaging layer 200 may be a
transparent substrate made of glass, quartz, opal, plastic or other
materials permit light passing through. Moreover, a filter and/or
an anti-reflective layer can be selectively formed on the packaging
layer 200. In the embodiments of chip packages for
non-photosensitive devices, the packaging layer 200 can be a
semiconductor layer, for example a silicon covering layer.
[0030] In another embodiment, the spacer 100 can completely fill
between the insulating protective layer 108a and the packaging
layer 200, such that no cavity is formed between the insulating
protective layer 108a and the packaging layer 200.
[0031] The spacer 110 can be made of epoxy resin, a solder mask or
other suitable insulating materials.
[0032] According to an embodiment of the invention, the insulating
protective layer is formed on the conductive pads during the
cutting process for wafer scale packages, thus the conductive pads
can be prevented from damage and scratching by the chipping formed
from the cutting process. Moreover, in the subsequent process for
removing the insulating protective layer, the packaging layer with
openings formed by the cutting process can be used as a hard mask,
such that there is no need to form an extra patterned photoresist
to serve as a mask.
[0033] While the invention has been described by way of example and
in terms of the preferred embodiments, it is to be understood that
the invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *