U.S. patent application number 12/838901 was filed with the patent office on 2011-01-20 for method of forming shallow trench isolation structure.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. Invention is credited to Chien-Chang FANG, Hue Mei JAO, Chien-Hua LI, Jin-Lin LIANG, Shian Wei MAO, Cheng-Long TAO, Tai-Yung YU.
Application Number | 20110014726 12/838901 |
Document ID | / |
Family ID | 43465591 |
Filed Date | 2011-01-20 |
United States Patent
Application |
20110014726 |
Kind Code |
A1 |
YU; Tai-Yung ; et
al. |
January 20, 2011 |
METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE
Abstract
A method for forming a shallow trench isolation (STI) structure
with a predetermined target height is provided. A substrate having
a pad oxide layer formed on the substrate is provided. A
nitride-containing layer with a thickness is formed on the pad
oxide. A STI structure is formed and extends through the
nitride-containing layer, the pad oxide layer, into the substrate.
The thickness of the nitride-containing layer is measured to
calculate the height of STI structure according to a correlation
between the thickness of the nitride-containing layer and the
height of STI structure. A thickness of the top portion STI
structure to be removed is determined according to the difference
between the height of the STI structure and the predetermined
target height and is removed in a first etching process. The
nitride-containing layer is removed without etching the STI
structure or the pad oxide layer in a second etching process.
Inventors: |
YU; Tai-Yung; (Rende
Township, TW) ; JAO; Hue Mei; (Tainan City, TW)
; LIANG; Jin-Lin; (Alian Township, TW) ; LI;
Chien-Hua; (Tainan City, TW) ; TAO; Cheng-Long;
(Hsindian City, TW) ; MAO; Shian Wei; (Taipei
City, TW) ; FANG; Chien-Chang; (Fongshan City,
TW) |
Correspondence
Address: |
Lowe Hauptman Ham & Berner, LLP (TSMC)
1700 Diagonal Road, Suite 300
Alexandria
VA
22314
US
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY, LTD.
Hsinchu
TW
|
Family ID: |
43465591 |
Appl. No.: |
12/838901 |
Filed: |
July 19, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61226971 |
Jul 20, 2009 |
|
|
|
Current U.S.
Class: |
438/8 ;
257/E21.53; 257/E21.543; 438/424 |
Current CPC
Class: |
H01L 21/762 20130101;
H01L 22/26 20130101; H01L 21/30604 20130101; H01L 21/304 20130101;
H01L 22/12 20130101; H01L 21/02112 20130101; H01L 21/76229
20130101; H01L 22/20 20130101; H01L 21/76224 20130101 |
Class at
Publication: |
438/8 ;
257/E21.543; 438/424; 257/E21.53 |
International
Class: |
H01L 21/76 20060101
H01L021/76; H01L 21/66 20060101 H01L021/66 |
Claims
1. A method of forming a shallow trench isolation structure with a
target height above a pad oxide layer on a substrate, the method
comprising: forming a nitride-containing layer on a top surface of
the pad oxide layer, the nitride-containing layer having a
thickness; forming a shallow trench isolation (STI) structure
extending through the nitride-containing layer, the pad oxide
layer, and into the substrate, wherein the STI structure has a top
surface and a height above the top surface of the pad oxide layer;
establishing a correlation between the thickness of the
nitride-containing layer and the height of the STI structure;
measuring the thickness of the nitride-containing layer to
calculate the height of the STI structure according to the
correlation; determining a thickness of the STI structure to be
removed according to a difference between the height of the STI and
a predetermined target height of the STI structure above the top
surface of the pad oxide; selectively removing the thickness of the
STI structure in a first etch process, and selectively removing the
nitride-containing layer without substantially etching the STI
structure or the pad oxide layer in a second etch process, whereby
the resulting STI structure has the predetermined target
height.
2. The method of claim 1, wherein said establishing comprises
polishing the STI structure to the nitride-containing layer until
the top surfaces of the nitride-containing layer and the STI
structure are substantially coplanar.
3. The method of claim 1, wherein said establishing comprises
polishing the STI structure to the nitride-containing layer, while
leaving a step height difference between the top surfaces of the
nitride-containing layer and the STI structure.
4. The method of claim 3, further comprising: measuring the step
height difference between top surfaces of the nitride-containing
layer and the STI structure to calculate the height of the STI
structure according to the correlation.
5. The method of claim 1, wherein said forming the STI structure
comprises: etching a trench extending through the
nitride-containing layer, the pad oxide layer, and into the
substrate; and depositing an isolation oxide layer to overfill the
trench.
6. The method of claim 1, wherein the first etch process comprises
dipping the substrate in a HF solution.
7. The method of claim 1, wherein the second etch process comprises
dipping the substrate in a phosphoric acid solution.
8. The method of claim 7, further comprising: controlling a silicon
concentration in the phosphoric acid solution within a range of
about 57 to 110 parts per million (ppm).
9. The method of claim 7, further comprising: controlling a silicon
concentration in the phosphoric acid solution to be under an
aggregate silicon concentration, whereby the STI structure is not
removed.
10. The method of claim 7, further comprising: during said dipping,
maintaining the phosphoric acid solution at a predetermined
temperature.
11. A method of forming a shallow trench isolation structure with a
target height above a pad oxide layer on a substrate, the method
comprising: forming a nitride-containing layer on the pad oxide
layer, wherein the nitride-containing layer has a thickness;
forming a shallow trench isolation (STI) structure extending
through the nitride-containing layer, the pad oxide layer and into
the substrate, wherein top surfaces of the STI structure and the
nitride-containing layer are substantially coplanar; measuring the
thickness of the nitride-containing layer to determine a height of
the STI structure above the pad oxide; calculating an etching time
to selectively etch a thickness of the STI structure in a HF
solution, wherein the thickness of the STI structure is a
difference between the determined height of the STI structure and a
predetermined target height of the STI structure above the pad
oxide; selectively etching the thickness of the STI structure in
the HF solution for the etching time; and thereafter selectively
etching the nitride-containing layer with a phosphoric acid
solution without removing the STI structure, whereby the resulting
STI structure has the predetermined target height.
12. The method of claim 11, wherein said forming the STI structure
comprises: etching a trench extending through the
nitride-containing layer, the pad oxide, and into the substrate;
depositing an isolation oxide layer to overfill the trench; and
polishing the overfilled isolation oxide layer to be substantially
coplanar to the nitride-containing layer.
13. The method of claim 11, wherein said selectively etching the
nitride-containing layer with the phosphoric acid solution
comprises: controlling a silicon concentration in the phosphoric
acid solution to be under an aggregate silicon concentration,
whereby the STI structure is not removed.
14. The method of claim 11, wherein said selectively etching the
nitride-containing layer with the phosphoric acid solution
comprises: controlling a silicon concentration in the phosphoric
acid solution within a range of about 57 to 110 parts per million
(ppm).
15. A method of forming a shallow trench isolation structure with a
predetermined target height above a pad oxide layer on each of a
plurality of substrates in a processing lot, the method comprising:
forming a nitride-containing layer on the pad oxide layer on each
substrate, wherein the nitride-containing layer has a thickness;
forming a shallow trench isolation (STI) structure on each
substrate to extend through the nitride-containing layer, the pad
oxide layer and into the substrate, wherein a top surface of the
STI structure and a top surface of the nitride-containing layer on
each substrate are substantially coplanar; measuring the thickness
of the nitride-containing layer on at least one substrate in the
processing lot to determine a height of the STI structure above the
pad oxide on said at least one substrate; calculating an etching
time based on the measured thickness of the nitride-containing
layer to selectively etch a thickness of the STI structure on each
substrate in a first wet solution, wherein the thickness of the STI
structure is a difference between the determined height and a
predetermined target height of the STI structure above the pad
oxide; dipping the processing lot in the first wet solution to
selectively etch the thickness of the STI structure for each
substrate for the etching time; and dipping the processing lot in a
second wet solution to selectively etch the nitride-containing
layer for each substrate without etching the STI structure or the
pad oxide, whereby the resulting STI structure for each substrate
is adjusted to the predetermined target height.
16. The method of claim 15, wherein said forming the STI structure
on each substrate comprises: etching a trench extending through the
nitride-containing layer, the pad oxide, and into the substrate;
depositing an isolation oxide layer to overfill the trench; and
polishing the overfilled isolation oxide layer to be substantially
coplanar with the nitride-containing layer.
17. The method of claim 15, wherein the first wet solution
comprises a HF solution
18. The method of claim 15, wherein the second wet solution
comprises a phosphoric acid solution.
19. The method of claim 18, further comprising: controlling a
silicon concentration in the phosphoric acid solution to be under
an aggregate silicon concentration, whereby the STI structure is
not removed.
20. The method of claim 18, further comprising: maintaining a
silicon concentration in the phosphoric acid solution within a
range of about 57 to 110 parts per million (ppm).
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority of U.S. Provisional
Patent Application Ser. No. 61/226,971, filed on Jul. 20, 2009,
which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
[0002] The disclosure relates generally to integrated circuit
manufacturing processes, and more particularly, to methods for
controlling the dimension of a shallow trench isolation
structure.
BACKGROUND
[0003] Shallow trench isolation (STI) has become a common and
important isolation technology in an IC device. One of the purposes
of STI is to prevent carriers, such as electrons or electron-holes,
from drifting between two adjacent device elements through a
semiconductor substrate to cause a leakage current.
[0004] A conventional STI process flow may include pad oxide layer
and nitride-containing layer deposition on a substrate, active area
masking, nitride-containing/oxide etching, silicon substrate trench
etching, isolation oxide filling, chemical mechanical polishing,
and nitride-containing layer and pad oxide layer removal.
[0005] In the conventional method, the predetermined target height
of isolation oxide above the pad oxide layer cannot be well
controlled. In some products, the electrical performance varies
with the predetermined target height of isolation oxide. This lack
of control also produces several problems, and one problem is divot
formation (i.e. oxide recess) along an STI edge. Divot formation
reduces device yield. The divot at the edge of the STI may be
formed by having the pad oxide layer removed in a wet dip
process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The disclosure will be described with reference to
embodiments thereof as illustrated in the accompanying figures. It
should be understood that the drawings are for illustrative
purposes and therefore not drawn to scale.
[0007] FIG. 1 is a flowchart of a method for fabricating a shallow
trench isolation structure, in accordance with an embodiment of the
present invention.
[0008] FIGS. 2 to 8 show cross-sectional views of a shallow trench
isolation structure at various stages of manufacture according to
FIG. 1.
DETAILED DESCRIPTION
[0009] The making and using of illustrative embodiments are
discussed in detail below. It should be appreciated, however, that
the present invention provides many applicable inventive concepts
that can be embodied in a wide variety of specific contexts. The
specific embodiments discussed are merely illustrative of specific
ways to make and use the invention, and do not limit the scope of
the invention.
[0010] FIG. 1 depicts a flowchart of a method 100 for fabricating a
shallow trench isolation structure according to one embodiment of
the invention. FIGS. 2 to 8 are cross-sectional views of a shallow
trench isolation structure at various stages of manufacture
according to FIG. 1. Referring to FIGS. 1 and 2, in process 101
step, a substrate 201 comprises a pad oxide layer 203 formed on the
substrate 201. The term "substrate" herein, generally refers to a
semiconductor substrate comprising silicon or compound
semiconductor, such as GaAs, InP, Si/Ge, or SiC. The pad oxide
layer 203 has a top surface 202 and may be grown by a conventional
oxidation process over the substrate 201. Alternatively, the pad
oxide layer 203 may be formed by a chemical vapor deposition (CVD)
process or any suitable method. In one embodiment, the pad oxide
layer 203 has a thickness from about 90 Angstroms (.ANG.) to about
140 .ANG..
[0011] Referring to FIGS. 1 and 3, in process step 103, a
nitride-containing layer 205 is formed over the pad oxide layer 203
on the substrate 201. Examples of nitride-containing layer 205 may
include a nitride layer, a SiON layer, or any suitable material. In
one embodiment, the nitride-containing layer 205 has a thickness T
from about 800 .ANG. to about 1600 .ANG.. The nitride-containing
layer 205 can function as a stop layer during a subsequent process,
such as for example planarization. In one embodiment, the
nitride-containing layer 205 has a top surface 206 and is formed by
chemical vapor deposition (CVD). It is understood by those skilled
in the art that nitride-containing layer 205 may be formed by other
deposition process as well.
[0012] Referring to FIGS. 1 and 4-6, in process step 105, a shallow
trench isolation (STI) structure 211 is formed in the substrate
201. The STI structure 211 extends through the nitride-containing
layer 205, the pad oxide layer 203 and into the substrate 201.
[0013] FIG. 4 illustrates a trench 207 that is etched and extends
through the nitride-containing layer 205, the pad oxide layer 203
and into the substrate 201. The trench 207 may be formed by a
plasma etching process or any suitable method.
[0014] FIG. 5 illustrates an isolation oxide layer 209 is deposited
to overfill the trench 207 and the top surface 206 of the
nitride-containing layer 205. In one embodiment, the isolation
oxide layer 209 is a material having a high gap fill
characteristic, such as high-temperature undoped silicate glass
(USG), a high density plasma (HDP) oxide, or a silicon oxide such
as tetraethyl orthosilicate (TEOS).
[0015] FIG. 6 illustrates the isolation oxide layer 209 being
planarized to expose the top surface 206 of the nitride-containing
layer 205. The planarization process removes the portion of the
isolation oxide layer 209 that overfills the trench 207 to expose
the top surface 206 of the nitride-containing layer 205. The
planarization process may be performed using a chemical mechanical
polishing (CMP) process, an etching process, and/or a combination
thereof. After the steps shown in FIGS. 4 to 6, the STI structure
211 is formed and confined within the trench 207.
[0016] The STI structure 211 extends through the nitride-containing
layer 205, the pad oxide layer 203 and into the substrate 201. The
STI structure 211 has a top surface 213 and a height H. The height
H is measured from the top surface 202 of the pad oxide layer 203
to the top surface 213 of the STI structure 211. During the
formation of STI structure 211, a correlation between the thickness
T of the nitride-containing layer 205 and the height H of STI
structure 211 is established in process step 107. In one
embodiment, the process 107 of establishing a correlation comprises
polishing the STI structure 211 to the nitride-containing layer
205. The polishing makes the top surfaces 206, 213 of the
nitride-containing layer 205 and the STI structure 211
substantially coplanar. Thus, the height H of STI structure 211 is
substantially equal to the thickness T of the nitride-containing
layer 205. In another embodiment, the process step 107 of
establishing a correlation also comprises polishing the STI
structure 211 to the nitride-containing layer 205. But if CMP
process has different removing rates for the isolation oxide layer
209 and the nitride-containing layer 205, there is a step height
difference S between the top surfaces 206, 213 of the
nitride-containing layer 205 and the STI structure 211. Therefore,
a measurement step may be needed to measure the step height
difference S.
[0017] Referring back to FIG. 1, the fabricating method continues
with process 109. The thickness T of the nitride-containing layer
205 is measured to calculate the height H of STI structure 211
according to the correlation in process step 107. The thickness T
of the nitride-containing layer 205 is measured by a metrology
tool. The metrology tool may include electrical and optical tools,
such as film thickness measurement tools, or any suitable tool. In
one embodiment, if the top surfaces 206, 213 of the
nitride-containing layer 205 and STI structure 211, respectively
are aligned, the height H of STI structure 211 is substantially
equal to the thickness T of the nitride-containing layer 205. In
another embodiment shown in FIG. 6, if the top surfaces 206, 213 of
the nitride-containing layer 205 and STI structure 211,
respectively are not aligned, the measured height H of STI
structure 211 is the measured thickness T of the nitride-containing
layer 205 plus the step height difference S measured between the
nitride-containing layer 205 and the STI structure 211.
[0018] Referring again to FIG. 1, the fabricating method continues
with process step 111. The process step 111 determines a thickness
D on the top portion STI structure 211 to be selectively removed in
a first solution. As shown in FIG. 7, the thickness D of the top
portion STI structure 211 is a difference between the height H of
STI structure 211 and a predetermined target height t' of the STI
structure 211 above the pad oxide 203. An etching time for removing
the thickness D could be calculated from the thickness D divided by
a removing rate of STI structure 211 in the first solution.
[0019] Referring back to FIG. 1, the fabricating method continues
with process step 113. The process step 113 selectively removes the
thickness D of the top portion STI structure 211 by a first etching
process. In one embodiment, the substrate 201 is dipped in a first
solution for the etching time calculated in process step 111. By
controlling the etching time, the demand of a precisely controlled
predetermined target height t' for STI structure 211 for different
products can be achieved. In one embodiment, the first wet solution
comprises a HF solution, which is diluted at a rate of 50:1. In
another embodiment, the first wet solution comprises any suitable
solution. In some embodiments, the process step 113 comprises
selectively etching the top portion STI structure 211 by a dry
etching process.
[0020] Referring to FIG. 1, the fabricating method continues with
process step 115. The process step 115 selectively removes the
nitride-containing layer 205 without etching the STI structure 211
or the pad oxide 203 by a second etching process. In one
embodiment, the process step 115 comprises dipping the substrate
201 in a second wet solution, which comprises a hot phosphoric acid
solution. The second wet solution can be monitored and controlled
to keep the silicon concentration in the second wet solution at a
constant level, which is under an aggregate silicon concentration.
The silicon concentration directly affects the etch rates of the
nitride-containing and silicon oxide layers. For example, the oxide
layer etch rate becomes dramatically lower as the silicon
concentration in the second wet solution increases. The silicon
concentration should be controlled under the aggregate silicon
concentration to prevent silica precipitates from forming in the
second wet solution. In one exemplary embodiment, the second wet
solution may be maintained at a predetermined temperature within a
range of about 70 to 160 to extend the bath life of the hot
phosphoric bath. The silicon concentration may be maintained at a
predetermined concentration within a range of about 57 to 110 parts
per million (ppm). In another embodiment, the predetermined
temperature is at about 150. It is understood by those skilled in
the art that the process step 115 comprises removing the
nitride-containing layer 205 by a dry etching process as well.
[0021] It is understood by those skilled in the art that the
predetermined target height t' may vary between different products.
In some cases, the electrical performance may vary with the
predetermined target height t' of STI structure 211. The
embodiments of the invention provide a method to form a shallow
trench isolation structure having a precise predetermined target
height control that achieves different demands for different
products with robust electrical performance.
[0022] FIG. 1 depicts a flowchart of the method 100 for fabricating
a shallow trench isolation structure for a single substrate. The
method 100 can also be simultaneously performed on all of the
substrates in a processing lot. In another embodiment, all of the
process steps except for the measuring step 109 are simultaneously
performed on all of the substrates in a processing lot, and the
measuring step 109 is only performed on a subset of the substrates
in the processing lot. For example, all of the substrates in the
lot can be processed together during process steps 101, 103, 105
and 107. Since all of the substrates in the lot are processed
together in those four steps, the correlation between the thickness
of the nitride-containing and the height of the STI should be
similar for each substrate in the lot, so the measurement taken on
one substrate can be used to determine the thickness of STI to be
removed for all of the substrates in the lot. Thus it should not be
necessary to measure the nitride-containing layer thickness on
every wafer in the lot if all of the substrates in the lot are
processed together during the other process steps. However, the
measuring step 109 may be performed on at least one substrate in
the processing lot. After the thickness of STI to be removed is
determined in process step 111, all of the substrates in the lot
can be processed together in process steps 113 and 115.
[0023] Although exemplary embodiments of the present invention and
their advantages have been described in detail, it should be
understood that various changes, substitutions and alterations can
be made herein without departing from the spirit and scope of the
invention as defined by the appended claims. Moreover, the scope of
the present application is not intended to be limited to the
particular embodiments of the process, machine, manufacture, and
composition of matter, means, methods and steps described in the
specification. As one of ordinary skill in the art will readily
appreciate from the disclosure herein, processes, machines,
manufacture, compositions of matter, means, methods, or steps,
presently existing or later to be developed, that perform
substantially the same function or achieve substantially the same
result as the corresponding embodiments described herein may be
utilized according to the present invention. Accordingly, the
appended claims are intended to include within their scope such
processes, machines, manufacture, compositions of matter, means,
methods, or steps.
* * * * *