U.S. patent application number 12/807763 was filed with the patent office on 2011-01-13 for simplified multichip packaging and package design.
This patent application is currently assigned to STMicroelectronics Asia Pacific Pte. Ltd.. Invention is credited to Chek-Lim Kho, Kum-Weng Loo.
Application Number | 20110006411 12/807763 |
Document ID | / |
Family ID | 36061338 |
Filed Date | 2011-01-13 |
United States Patent
Application |
20110006411 |
Kind Code |
A1 |
Loo; Kum-Weng ; et
al. |
January 13, 2011 |
Simplified multichip packaging and package design
Abstract
A multichip integrated circuit apparatus includes first and
second integrated circuit die mounted on opposite sides of a
leadframe die paddle, with at least one of the integrated circuit
die extending further toward the leads than does the die paddle.
With this arrangement, the active circuit areas of both integrated
circuit die can face in the same direction, and can be wire bonded
to the same surfaces of the leads. This avoids wire bonding
complications that are often encountered in multichip integrated
circuit package designs.
Inventors: |
Loo; Kum-Weng; (Singapore,
SG) ; Kho; Chek-Lim; (Singapore, SG) |
Correspondence
Address: |
STMICROELECTRONICS, INC.
MAIL STATION 2346 , 1310 ELECTRONICS DRIVE
CARROLLTON
TX
75006
US
|
Assignee: |
STMicroelectronics Asia Pacific
Pte. Ltd.
Singapore
SG
|
Family ID: |
36061338 |
Appl. No.: |
12/807763 |
Filed: |
September 14, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11000355 |
Nov 30, 2004 |
7816182 |
|
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12807763 |
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Current U.S.
Class: |
257/676 ;
257/E23.037 |
Current CPC
Class: |
H01L 2924/01082
20130101; H01L 2224/49113 20130101; H01L 2224/4826 20130101; H01L
2924/01033 20130101; H01L 2924/01047 20130101; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2224/73265 20130101; H01L
2224/48465 20130101; H01L 2224/73265 20130101; H01L 2224/32145
20130101; H01L 2224/73265 20130101; H01L 2224/48091 20130101; H01L
2224/32245 20130101; H01L 2224/48465 20130101; H01L 2924/181
20130101; H01L 2224/73215 20130101; H01L 2224/32145 20130101; H01L
2224/32245 20130101; H01L 23/49575 20130101; H01L 2224/48247
20130101; H01L 2924/01078 20130101; H01L 24/32 20130101; H01L
2924/181 20130101; H01L 24/49 20130101; H01L 2224/48465 20130101;
H01L 2224/48464 20130101; H01L 2224/48465 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/14 20130101; H01L
2224/4826 20130101; H01L 24/48 20130101; H01L 2224/49113 20130101;
H01L 2224/73215 20130101; H01L 2224/48091 20130101; H01L 2224/45099
20130101; H01L 2224/4826 20130101; H01L 2924/00 20130101; H01L
2224/32245 20130101; H01L 2924/00014 20130101; H01L 2224/48465
20130101; H01L 2224/45015 20130101; H01L 2224/48247 20130101; H01L
2224/4826 20130101; H01L 2924/00 20130101; H01L 2224/48247
20130101; H01L 2924/207 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/48247 20130101; H01L 2224/48465 20130101 |
Class at
Publication: |
257/676 ;
257/E23.037 |
International
Class: |
H01L 23/495 20060101
H01L023/495 |
Claims
1. An integrated circuit apparatus, comprising: a leadframe
including a first set of leads, a second set of leads and a die
paddle disposed between said first and second sets of leads; a
first integrated circuit die mounted on a first side of said die
paddle; a second integrated circuit die mounted on a second side of
said die paddle which faces generally oppositely of said first side
of said die paddle; and one of said first and second integrated
circuit die extending further toward both of said first and second
sets of leads than does said die paddle.
2. The apparatus of claim 1, wherein the other of said first and
second integrated circuit die extends further toward both of said
first and second sets of leads than does said die paddle.
3. The apparatus of claim 1, wherein each of said leads has first
and second generally oppositely facing surfaces, all of said first
surfaces facing generally in a first direction and all of said
second surfaces facing generally in a second direction that is
generally opposite said first direction, and including a first
plurality of electrically conductive wires, each said wire of said
first plurality having one end bonded to said first surface of one
of said leads and having another end bonded to said first
integrated circuit die, and a second plurality of electrically
conductive wires, each said wire of said second plurality having
one end bonded to said first surface of one of said leads and
having another end bonded to said second integrated circuit
die.
4. The apparatus of claim 3, wherein said first integrated circuit
die has an active circuit area which faces said first side of said
die paddle.
5. The apparatus of claim 1, wherein said first integrated circuit
die has an active circuit area which faces said first side of said
die paddle, and including a plurality of electrically conductive
wires, each said wire having one end bonded to one of said leads
and having another end bonded to said first integrated circuit
die.
6. The apparatus of claim 1, wherein said leads are approximately
coplanar with said die paddle.
7. The apparatus of claim 1, wherein said die paddle is a split die
paddle.
8. The apparatus of claim 1, including a third integrated circuit
die mounted on a spacer that is mounted on said first integrated
circuit die and is interposed between said first integrated circuit
die and said third integrated circuit die.
9. The apparatus of claim 8, wherein each of said leads has a first
portion that is approximately coplanar with said first integrated
circuit die, and a second portion that extends from said first
portion at an angle directed toward one of said second and third
integrated circuit die.
10. An integrated circuit apparatus, comprising: a leadframe
including a first set of leads, a second set of leads and a die
paddle disposed between said first and second sets of leads; a
first integrated circuit die mounted on a first side of said die
paddle; a second integrated circuit die mounted on a second side of
said die paddle which faces generally oppositely of said first side
of said die paddle; each of said leads having first and second
generally oppositely facing surfaces, all of said first surfaces
facing generally in a first direction and all of said second
surfaces facing generally in a second direction that is generally
opposite said first direction; a first plurality of electrically
conductive wires, each said wire of said first plurality having one
end bonded to said first surface of one of said leads and having
another end bonded to said first die; and a second plurality of
electrically conductive wires, each said wire of said second
plurality having one end bonded to said first surface of one of
said leads and having another end bonded to said second die.
11. The apparatus of claim 10, wherein said leads are approximately
coplanar with said die paddle.
12. The apparatus of claim 10, wherein said die paddle is a split
die paddle.
13. The apparatus of claim 10, including a third integrated circuit
die mounted on a spacer that is mounted on said first integrated
circuit die and is interposed between said first integrated circuit
die and said third integrated circuit die.
14. The apparatus of claim 13, wherein each of said leads has a
first portion that is approximately coplanar with said first
integrated circuit die, and a second portion that extends from said
first portion at an angle directed toward one of said second and
third integrated circuit die.
15. An integrated circuit apparatus, comprising: a leadframe
including a first set of leads, a second set of leads and a die
paddle disposed between said first and second sets of leads; a
first integrated circuit die mounted on a first side of said die
paddle; a second integrated circuit die mounted on a second side of
said die paddle which faces generally oppositely of said first side
of said die paddle; said first integrated circuit die having an
active circuit area which faces said first side of said die paddle;
and a plurality of electrically conductive wires, each said wire
having one end bonded to one of said leads and having another end
bonded to said first integrated circuit die.
16. The apparatus of claim 15, wherein said leads are approximately
coplanar with said die paddle.
17. The apparatus of claim 15, wherein said die paddle is a split
die paddle.
18. The apparatus of claim 15, including a third integrated circuit
die mounted on a spacer that is mounted on said first integrated
circuit die and is interposed between said first integrated circuit
die and said third integrated circuit die.
19. The apparatus of claim 18, wherein each of said leads has a
first portion that is approximately coplanar with said first
integrated circuit die, and a second portion that extends from said
first portion at an angle directed toward one of said second and
third integrated circuit die.
20.-22. (canceled)
Description
FIELD OF THE INVENTION
[0001] This invention relates generally to integrated circuit
packaging and, more particularly, to multichip packaging.
BACKGROUND OF THE INVENTION
[0002] A continuing goal of the semiconductor industry is to
maximize circuit density. One conventional approach is to provide
more than one semiconductor die (or chip) in a single integrated
circuit package. To this end, in various conventional designs,
first and second integrated circuit die are mounted on opposite
sides of a leadframe die paddle. In some of these designs, the
leadframe must be flipped in order to make all necessary wire
bonding connections, and wires are bonded to both the upper and
lower surfaces of the leads. Bonding to both lead surfaces requires
plating both lead surfaces (e.g. with silver). In some designs, the
die paddle must be specially designed to provide adequate heat
transfer during wire bonding. Some designs require a special
interconnect circuit which wraps around from one side of the die
paddle to the other side of the die paddle. Bond pads of the
integrated circuit die on one side of the die paddle are connected
to the interconnect circuit in order to render that integrated
circuit die electrically accessible from the other side of the die
paddle.
[0003] It can be seen from the foregoing discussion that the
conventional technique of mounting integrated circuit die on
opposite sides of a leadframe die paddle adds complications to the
design and production process.
[0004] FIG. 1 illustrates another conventional technique of
providing more than one integrated circuit die in a single
integrated circuit package. In FIG. 1, a spacer/interposer (such as
a semiconductor substrate) is interposed between first and second
integrated circuit die, one of which is mounted on the die paddle
11. The upper, active circuit areas of both integrated circuit die
are wire bonded to the sets of leads 12 and 13. The existence of
the spacer/interposer causes the arrangement of FIG. 1 to occupy
more space than do the aforementioned arrangements wherein the
integrated circuit die are mounted on opposite sides of the die
paddle. Also, the arrangement of FIG. 1 introduces a mismatch in
the coefficient of thermal expansion (CTE). Accordingly, the
downset of the die paddle 11 with respect to the lead sets 12 and
13 is typically provided to compensate for this CTE mismatch.
[0005] It is desirable in view of the foregoing to provide for
multichip packaging designs which can overcome the aforementioned
disadvantages associated with various conventional approaches.
SUMMARY OF THE INVENTION
[0006] Exemplary embodiments of the invention provide an integrated
circuit apparatus having first and second integrated circuit die
mounted on opposite sides of a leadframe die paddle, with at least
one of the integrated circuit die extending further toward the
leads than does the die paddle. This arrangement permits the active
circuit areas of both integrated circuit die to face in the same
direction, and to be wire bonded to the same surfaces of the leads.
This simplifies the wire bonding process.
[0007] The foregoing has outlined rather broadly the features and
technical advantages of the present invention so that those skilled
in the art may better understand the detailed description of the
invention that follows. Additional features and advantages of the
invention will be described hereinafter that form the subject of
the claims of the invention. Those skilled in the art will
appreciate that they may readily use the conception and the
specific embodiment disclosed as a basis for modifying or designing
other structures for carrying out the same purposes of the present
invention. Those skilled in the art will also realize that such
equivalent constructions do not depart from the spirit and scope of
the invention in its broadest form. (STMI)
[0008] Before undertaking the Detailed Description of the Invention
below, it may be advantageous to set forth definitions of certain
words or phrases used throughout this patent document: the terms
"include" and "comprise," as well as derivatives thereof, mean
inclusion without limitation; the term "or" is inclusive, meaning
and/or; the phrases "associated with" and "associated therewith,"
as well as derivatives thereof, may mean to include, be included
within, interconnect with, contain, be contained within, connect to
or with, couple to or with, be communicable with, cooperate with,
interleave, juxtapose, be proximate to, be bound to or with, have,
have a property of, or the like; and the term "controller" means
any device, system or part thereof that controls at least one
operation, whether such a device is implemented in hardware,
firmware, software or some combination of at least two of the same.
It should be noted that the functionality associated with any
particular controller may be centralized or distributed, whether
locally or remotely. Definitions for certain words and phrases are
provided throughout this patent document, and those of ordinary
skill in the art will understand that such definitions apply in
many, if not most, instances to prior uses, as well as to future
uses, of such defined words and phrases.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] For a more complete understanding of the present invention,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
wherein like numbers designate like objects, and in which:
[0010] FIG. 1 illustrates a conventional multichip package
design;
[0011] FIG. 2 illustrates a multichip package design according to
exemplary embodiments of the invention;
[0012] FIG. 3 is a top view of FIG. 2;
[0013] FIG. 4 illustrates a specific embodiment of the multichip
package design of FIG. 2;
[0014] FIG. 5 illustrates a multichip packaging design according to
exemplary embodiments of the invention, and including a
spacer/interposer;
[0015] FIG. 6 is similar to FIG. 5, but utilizes a split die paddle
according to exemplary embodiments of the invention;
[0016] FIG. 7 is a top view of FIG. 6;
[0017] FIG. 8 illustrates an exemplary process for use in producing
the embodiments of FIGS. 2-7.
DETAILED DESCRIPTION OF THE INVENTION
[0018] The figures and the various embodiments used to describe the
principles of the present invention in this patent document are by
way of illustration only and should not be construed in any way to
limit the scope of the invention.
[0019] Exemplary embodiments of the invention provide for mounting
first and second integrated circuit die on opposite sides of a
leadframe die paddle. At least one of the integrated circuit die
extends further toward both sets of leadframe leads than does the
die paddle, thereby permitting the active circuit areas of both
integrated circuit die to face in the same direction and to be wire
bonded to the same surfaces of the leadframe leads. The wire
bonding process does not require flipping the leadframe, and no
special die paddle design is needed for heat transfer during wire
bonding.
[0020] FIG. 2 illustrates a multichip package design according to
exemplary embodiments of the invention. In the example of FIG. 2,
integrated circuit die 21 and 22 are mounted on opposite sides of a
leadframe die paddle using any suitable die adhesive, for example a
non-conductive glue. The active circuit area of the integrated
circuit die 22 faces the die paddle, and the active circuit area of
the integrated circuit die 21 faces oppositely from the die paddle,
so both active circuit areas are facing in the same direction. The
integrated circuit die 22 extends further toward both sets of leads
23 and 24 than does the die paddle, thereby permitting the
integrated circuit die 22 to be wire bonded to the same surfaces of
the leads 23 and 24 as is the integrated circuit die 21. By wire
bonding to the same side of the leads 23 and 24, only that side of
the leads need be plated (such as silver plating). Also, both
integrated circuit die can be wire bonded to the leads without
requiring any flipping of the lead frame during the wire bonding
process.
[0021] FIG. 3 provides a top view of the multichip package design
of FIG. 2.
[0022] FIG. 4 illustrates a specific example of the multichip
package design of FIG. 2, with exemplary physical dimensions
labeled therein. As shown more clearly in the example of FIG. 4,
because no interposer/spacer is utilized, the embodiments of FIGS.
2-4 do not introduce a CTE mismatch problem, so a downset such as
illustrated in prior art FIG. 1 is not necessary.
[0023] FIG. 5 illustrates a further multichip package design
according to exemplary embodiments of the invention. FIG. 5 is
generally similar to the embodiments of FIGS. 2-4, with two
integrated circuit die 21 and 22 mounted on opposite sides of a
leadframe die paddle 41 and facing in a common direction. An
interposer is mounted on the active surface area of the integrated
circuit die 21, and a third integrated circuit die 51 is mounted on
the interposer, with its active circuit area facing away from the
interposer. The arrangement of FIG. 5 thus implements a stack of
three integrated circuit die whose respective active circuit areas
face in a common direction. The stacking of the interposer and
third integrated circuit die 51 on the integrated circuit die 21
can be accomplished in generally the same conventional fashion as
the interposer and second integrated circuit die are stacked onto
the first integrated circuit die in prior art FIG. 1.
[0024] The leads at 52 and 53 in FIG. 5 are shaped differently than
the leads in the embodiments of FIGS. 2-4, in order to better
accommodate wire bonding to the three integrated circuit die 21, 22
and 51. In particular, the outer portions of the leads at 52 and 53
extend generally inwardly toward the middle integrated circuit die
21 and are approximately coplanar therewith. However, the inner
portions of the leads at 52 and 53 are angled in a direction toward
the integrated circuit die 22, thereby facilitating wire bonding to
the integrated circuit die 22. In the example of FIG. 5, the active
circuit die areas of all three integrated circuit die are wire
bonded to the same side of the leads at 52 and 53. The dimensions
illustrated in FIG. 5 are provided by way of example only, in order
to describe one specific embodiment represented by FIG. 5.
[0025] FIG. 6 illustrates a multichip package design according to
further exemplary embodiments of the invention. The example of FIG.
6 is similar to FIG. 5, but utilizes a two-piece or split die
paddle 61, rather than a one-piece die paddle 41 as shown in FIG.
5. The space between the two pieces of the die paddle 61 is filled
in with the glue that is used to mount the integrated circuit die
21 and 22 on the die paddle 61. As in the examples of FIGS. 2-5,
the integrated circuit die 21 and 22 mounted on the split die
paddle 61 extend further toward both sets of leads 52 and 53 than
does the split die paddle 61, thereby providing space for wire
bonding the integrated circuit die 22 onto the same surface of the
leads 52 and 53 as are the other two integrated circuit die 21 and
51. This also permits the entire wire bonding process to be
completed without flipping the leadframe. The specific dimensions
shown in FIG. 6 are provided by way of example only, in order to
describe one particular embodiment represented by FIG. 6.
[0026] FIG. 7 is a top view of the multichip package design of FIG.
6.
[0027] In all of the embodiments illustrated in FIGS. 2-7, the back
of the integrated circuit die 22 can be used for heat transfer
purposes during the wire bonding process, so there is no need for
the aforementioned special die paddle design that some prior art
approaches use to effectuate heat transfer during the wire bonding
process.
[0028] FIG. 8 illustrates exemplary operations which can be
performed to produce the exemplary multichip package design
described above with respect to FIGS. 2-4. After backgrinding the
wafer at 81, the wafer is mounted (and backside taped) for sawing
at 82, and is then sawed at 83. At 84, the sawed wafer is taped
again, this time on the active surface side of the wafer, and the
backside of the wafer is de-taped. With the tape now on the active
circuit side of the wafer, the wafer has been effectively flipped
for purposes of the packaging process. Therefore, with the
leadframe flipped also, the flipped die can be die-attached (D/A)to
the flipped leadframe at 85, which results in the active circuit
area of the die mounted on and facing what will ultimately be the
bottom of the die paddle (see also die 22 of FIGS. 2-4). At 86, the
leadframe is flipped back over and a plasma cleaning process can be
performed. Thereafter, at 87, the integrated circuit die (for
example 22 in FIGS. 2-4) is wire bonded to the appropriate leads.
Then, at 88, a die from a further, normally sawed wafer, with tape
on its backside, is die attached to the leadframe die paddle (which
was flipped back over at 86). This die corresponds to die 21 of
FIGS. 2-4. After another plasma cleaning operation at 89, the
integrated circuit die that was mounted at 88 (e.g. die 21 of FIGS.
2-4) is wired bonded to the appropriate leads at 90. Thereafter,
the leadframe and integrated circuit die are encapsulated within a
molding compound at 91.
[0029] Referring now to FIG. 8 and FIG. 5, the arrangement of FIG.
5 can be produced by using the operations up through operation 90
of FIG. 8, and thereafter mounting the interposer and third
integrated circuit die 51 onto the integrated circuit die 21 using
generally the same conventional techniques utilized to mount the
interposer and second integrated circuit die of prior art FIG. 1.
Thereafter, the third integrated circuit die 51 of FIG. 5 is wire
bonded to the leads 52 and 53, after which the entire arrangement
is encapsulated in a molding compound.
[0030] The structure of FIG. 6 differs from the structure of FIG. 5
in its use of a split die paddle 61, and it will therefore be
apparent to workers in the art that the arrangement of FIG. 6 can
be readily produced in generally the same fashion as described
above with respect to FIG. 5.
[0031] Although the present invention has been described in detail,
those skilled in the art will understand that various changes,
substitutions, and alterations herein may be made without departing
from the spirit and scope of the invention it its broadest
form.
* * * * *