U.S. patent application number 12/853749 was filed with the patent office on 2010-12-23 for self-aligned cross-point memory fabrication.
This patent application is currently assigned to MOLECULAR IMPRINTS, INC.. Invention is credited to Dwayne L. LaBrake, Christopher Mark Melliar-Smith, Sidlgata V. Sreenivasan.
Application Number | 20100323490 12/853749 |
Document ID | / |
Family ID | 40304679 |
Filed Date | 2010-12-23 |
United States Patent
Application |
20100323490 |
Kind Code |
A1 |
Sreenivasan; Sidlgata V. ;
et al. |
December 23, 2010 |
Self-Aligned Cross-Point Memory Fabrication
Abstract
Fabricating a cross-point memory structure using two lithography
steps with a top conductor and connector or memory element and a
bottom conductor orthogonal to the top connector. A first
lithography step followed by a series of depositions and etching
steps patterns a first channel having a bottom conductor. A second
lithography step followed by a series of depositions and etching
steps patterns a second channel orthogonal to the first channel and
having a memory element connecting the an upper conductor and the
lower conductor at their overlaid intersections.
Inventors: |
Sreenivasan; Sidlgata V.;
(Austin, TX) ; Melliar-Smith; Christopher Mark;
(Austin, TX) ; LaBrake; Dwayne L.; (Cedar Park,
TX) |
Correspondence
Address: |
MOLECULAR IMPRINTS
PO BOX 81536
AUSTIN
TX
78708-1536
US
|
Assignee: |
MOLECULAR IMPRINTS, INC.
Austin
TX
|
Family ID: |
40304679 |
Appl. No.: |
12/853749 |
Filed: |
August 10, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12182905 |
Jul 30, 2008 |
7795132 |
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12853749 |
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60952996 |
Jul 31, 2007 |
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61017242 |
Dec 28, 2007 |
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Current U.S.
Class: |
438/381 ;
257/E21.003 |
Current CPC
Class: |
H01L 27/24 20130101;
H01L 27/101 20130101 |
Class at
Publication: |
438/381 ;
257/E21.003 |
International
Class: |
H01L 21/02 20060101
H01L021/02 |
Claims
1. A method for fabricating a cross-point memory element,
comprising: patterning a multi-layered structure forming a
plurality of first channels and a plurality of first gratings, the
multi-layered structure having a first conducting layer and a
switching material stack layer; depositing a first dielectric
material layer on the multi-layered structure filling the first
channels; providing a crown surface defined by exposed surfaces of
the gratings and surfaces of dielectric material; depositing an
upper conducting layer on the crown surface; patterning the upper
conducting layer forming a plurality of second channels and a
plurality of second gratings, the second channels positioned
substantially orthogonal to the first channels; depositing a second
dielectric material layer filling the second channels; wherein
orthogonal overlapping of the first conducting layer and the upper
conducting layer provide a connection via the switching material
stack layer forming a memory element.
2. The method of claim 1, wherein the multi-layered structure
includes: a substrate layer; the first conducting layer; and, the
switching material stack layer wherein patterning the multi-layered
structure includes etching the first conducting layer and the
switching material stack layer to form the first channels.
3. The method of claim 2, wherein the first conducting layer is
formed of tungsten.
4. The method of claim 2, wherein the first channels are a series
of substantially parallel channels defining gratings.
5. The method of claim 2, wherein the first channels are formed
using a first lithography step followed by an etching step that
stops before the substrate layer.
6. The method of claim 2, wherein the upper conducting layer and
the first conducting layer are formed of tungsten.
7. The method of claim 1, wherein patterning the upper conducting
layer includes a lithography step and an etching step.
8. The method of claim 1, wherein patterning the multi-layered
structure includes an imprint lithography process.
9. The method of claim 1, wherein patterning the upper conducting
layer includes an imprint lithography process.
10. A method for fabricating a cross-point memory element for a
memory array comprising: applying a first lithography step to a
composite multilayer structure that includes a substrate and a
first resist material layer whereby a pattern for a plurality of
first channels is formed in the first resist material layer;
applying a sequence of deposition steps to fill the plurality of
first channels with a first dielectric material layer; depositing a
second resist material layer on the dielectric material; providing
a modified composite multilayer structure; applying a second
lithography step to the modified composite multilayer structure
whereby a pattern for a plurality of second channels, disposed over
and orthogonal to the plurality of first channels, is formed in the
second resist material; and, applying a sequence of deposition
steps to fill the plurality of second channels with a second
dielectric material layer.
11. The method of claim 10, wherein the composite multilayer
structure includes: a substrate; a first conducting layer; and, a
switching material stack layer.
12. The method of claim 10, further comprising planarizing the
first dielectric material layer.
13. The method of claim 10, wherein the modified composite
multilayer structure includes a second conducting layer.
14. The method of claim 10, wherein the first lithography step is
an imprint lithography process.
15. The method of claim 10, wherein the first channels are
substantially orthogonal to the second channels.
16. The method of claim 15, wherein orthogonal overlapping provides
a connection forming a memory element via a switching material
layer in the first resist material layer
17. The method of claim 10, wherein the first resist material layer
and the second resist material layer include tungsten.
18. A method for fabricating a cross-point memory element,
comprising: patterning a multi-layered structure forming a
plurality of first channels; depositing a first dielectric material
layer on the multi-layered structure filling the first channels;
providing a crown surface on the multi-layered structure;
depositing an upper conducting layer on the crown surface;
patterning the upper conducting layer forming a plurality of second
channels, the second channels positioned substantially orthogonal
to the first channels; and, depositing a second dielectric material
layer filling the second channels.
19. The method of claim 18, wherein the multi-layered structure
includes: a substrate layer; a first conducting layer; and, a
switching material layer.
20. The method of claim 19, wherein orthogonal overlapping of the
first conducting layer and the upper conducting layer forms a
memory element via the switching material layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 12/182,905 filed Jul. 30, 2008, which claims the benefit of
priority to U.S. provisional application No. 60/952,996, filed on
Jul. 31, 2007 and U.S. provisional application No. 61/017,242,
filed on Dec. 28, 2007. The aforementioned applications are
incorporated herein by references in their entirety.
TECHNICAL FIELD
[0002] The field of the invention relates generally to
semiconductor fabrication. More particularly, the present invention
is directed to fabricating a cross-point memory array.
BACKGROUND INFORMATION
[0003] Nano-fabrication involves the fabrication of very small
structures, e.g., having features on the order of nanometers or
smaller. One area in which nano-fabrication has had a sizeable
impact is in the processing of integrated circuits. As the
semiconductor processing industry continues to strive for larger
production yields while increasing the circuits per unit area
formed on a substrate, nano-fabrication becomes increasingly
important. Nano-fabrication provides greater process control while
allowing increased reduction of the minimum feature dimension of
the structures formed. Other areas of development in which
nano-fabrication has been employed include biotechnology, optical
technology, mechanical systems and the like.
[0004] An exemplary nano-fabrication technique is commonly referred
to as imprint lithography. Exemplary imprint lithography processes
are described in detail in numerous publications, such as U.S.
patent application publications no. 2004/0065976 and no.
2004/0065252 and U.S. Pat. No. 6,936,194, each of which is
incorporated by reference herein.
[0005] The imprint lithography technique disclosed in each of the
aforementioned U.S. patent application publications and U.S. patent
includes formation of a relief pattern in a polymerizable layer and
transferring a pattern corresponding to the relief pattern into an
underlying substrate. The substrate may be positioned upon a stage
to obtain a desired position to facilitate patterning thereof. A
mold is employed spaced-apart from the substrate with a formable
liquid present between the mold and the substrate. The liquid is
solidified to form a patterned layer that has a pattern recorded
therein that is conforming to a shape of the surface of the mold in
contact with the liquid. The mold is then separated from the
patterned layer such that the mold and the substrate are
spaced-apart. The substrate and the patterned layer are then
subjected to processes to transfer, into the substrate, a relief
image that corresponds to the pattern in the patterned layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a section view of stacked material layers in one
embodiment;
[0007] FIGS. 2-3 are section views after patterning and etching the
layers of FIG. 1;
[0008] FIGS. 4-7 are section views of the structure of FIG. 2 after
deposition of a dielectric layer;
[0009] FIGS. 8-11 are top and section views of a multi-layered
structure according to one embodiment;
[0010] FIGS. 12-16 are top and section views of a multi-layered
structure according to one embodiment;
[0011] FIGS. 17-21 illustrate the top view of a multi-layered
structure according to one embodiment;
[0012] FIG. 22A illustrates a multilayer structure according to
another embodiment;
[0013] FIG. 22B is a top view of the multilayer structure of the
embodiment of FIG. 22A;
[0014] FIG. 23 is a section view of the multilayer structure shown
in FIG. 22B taken along section line M.sub.1-M.sub.1';
[0015] FIGS. 24-25 illustrate a further embodiment for fabricating
lower conductor strips according to one embodiment;
[0016] FIGS. 26-27 illustrate yet another embodiment for forming
lower conductors;
[0017] FIGS. 28-29 illustrate views of further processing of the
structure according to one embodiment;
[0018] FIGS. 30-32 show a top view and section views of a
multi-layered structure according to one embodiment;
[0019] FIGS. 33-35 show various views of a multi-layered structure
according to one embodiment after further processing;
[0020] FIGS. 36-40 show various views of a multi-layered structure
according to one embodiment after further processing;
[0021] FIGS. 41-45 show various views of a multi-layered structure
according to one embodiment after further processing;
[0022] FIGS. 46-50 show various views of a multi-layered structure
according to one embodiment after further processing;
[0023] FIGS. 51-55 show various views of a multi-layered structure
according to one embodiment after further processing;
[0024] FIGS. 56-60 show various views of a multi-layered structure
according to one embodiment after further processing; and
[0025] FIGS. 61-62 are views of a cross-point memory structure that
may be fabricated by embodiments herein.
DETAILED DESCRIPTION
[0026] Cross-point memory structures may be manufactured with three
lithography steps including an intermediate lithography step to
form pillars (connectors) that connect the two conductors. Two of
these lithography steps (connectors and the second conductor)
require sub-resolution overlay. There is also a desire for
cross-point memory devices that utilize self-assembly molecular
switching elements. The present invention discloses fabricating
cross-point devices wherein the three materials (the first and
second conductors and the connecting material) are deposited and
aligned using standard silicon processing techniques.
[0027] In the present invention, an integration scheme where only
two lithography steps are sufficient to create the cross-point
structures is described. To that end, the precise (sub-resolution)
overlay requirement may be absent and the cross-point is naturally
formed at the intersection of the two conductor levels.
[0028] Referring to FIGS. 61 and 62, the present invention is
focused on making cross-point structures using 2 levels of
lithography and a self-aligned process wherein the connector
material 148 forming a memory element between the two conductor
levels 168 and 124 is formed at the intersection of the two
conductors that are typically laid orthogonal to each other. For an
embodiments herein, the lower conductors 124 and the connectors 148
may be made out materials that may be etched using a dry etch
(reactive ion etch (RIE) process and hence may be removed in a
subtractive manner. In one embodiment, they are made out of
silicon. In an exemplary structure, the lower conductors 124 are
aluminum, titanium or other metal conductors and the connectors 148
are polysilicon. The connectors 148 may also be other materials
that act as a reversible switches such as phase change materials,
e.g., GST materials as described in Yang et al., "Patterning of
Ge.sub.2Sb.sub.2Te.sub.5 phase change material using UV
nano-imprint lithography," Microelectronic Engineering, Volume 84,
Issue 1, January 2007, pages 21-24, which is incorporated herein by
reference. The bottom conductor 124 may also be formed by highly
doped silicon instead of being a metal. The top conductor 168 may
be formed from a variety of etchable metals including, but not
limited to, aluminum and copper.
[0029] FIG. 1 is a section view of a multi-layered structure 10
suitable for fabricating a cross-point memory structure.
Multi-layered structure 10 comprises a substrate 12, a first
conducting layer 14, and a connector or switching material stack
layer 16. Substrate 12 may be formed from materials including, but
not limited to, silicon, gallium arsenide, quartz, fused-silica,
sapphire, organic polymers, siloxane polymers, borosilicate glass,
fluorocarbon polymers, or a combination thereof. First conducting
layer 14 may be formed from tungsten. Switching material layer 16
may be formed from a combination of materials including, but not
limited to, polysilicon, chalcogenite, GST, and or material
structures configured as diodes (e.g., PN junctions).
[0030] FIGS. 2 and 3 illustrate top and section views of
multi-layered structure 10. Multi-layered structure 10 has a
pattern formed by etching away channels of first conducting layer
14 and connector or switching layer 16 thereby defining
multi-layered structure 110. FIG. 3 is a section view of structure
110 taken along section line A.sub.1-A.sub.1'. In this view, the
pattern is shown as a series of parallel channels 19 formed by
etching first conducting layer 14 and switching material stack
layer 16 along the direction D.sub.1 thereby defining gratings 18.
The pattern may be formed in multi-layered structure 110 using a
lithography step followed by an etching step that stops on
substrate 12. For the lithography step, any known technique, e.g.,
photolithography (various wavelengths including G line, I line, 248
nm, 193 nm, 157 nm, and 13.2-13.4 nm), contact lithography, e-beam
lithography, x-ray lithography, ion-beam lithography, atomic beam
lithography, and imprint lithography may be employed. Imprint
lithography is described in U.S. Pat. No. 6,932,934, U.S. patent
application publication no. 2004/0124566, U.S. patent application
publication no. 2004/0188381, and U.S. patent application
publication no. 2004/0211754, all of which are incorporated by
reference herein.
[0031] The etching step in FIGS. 2 and 3 employed to etch
conducting layer 14 may use a process described in Oehrlein et al.,
"Surface Modifications of Electronic Materials induced by Plasma
Etching," J. Electrochem. Soc. 136, 2050 (1989); Saia et al.,
"Plasma Etching Methods for the Formation of Planarized Tungsten
Plugs used in Multilevel VLSI Metallizations," in Proc. 6.sup.th
Symp. Plasma Processing, The Electrochemical Society, ECS Proc.
Vol. 87-6, 173 (1987); Balooch et al., "The Kinetics of Tungsten
and Tungsten Silicide Films by Chlorine Atoms," J. Electrochem.
Soc. 135, 2016 (1988); and van Roosmalen, "Dry Etching for VLSI,"
Springer, pp. 121-125 (1991); all of which are incorporated herein
by reference.
[0032] The etching step in FIGS. 2 and 3 employed to etch connector
layer 16 may use a process described in van Arendonk et al.,
European Patent no. 337,562 entitled "Method of Manufacturing a
Semiconductor Device," and van Roosmalen, "Dry Etching for VLSI,"
Springer, pp. 113 (1991); all of which are incorporated herein by
reference.
[0033] FIGS. 4-7 illustrate top and section views of multi-layered
structure 110 after deposition of a dielectric material 20 defining
a multi-layered structure 210. FIG. 4 is a top view showing the
channels 19 filled with dielectric material 20 and the various
section lines. FIG. 5 is the section view taken along section line
A.sub.2-A.sub.2' orthogonal to gratings 18. In this view, the
channels 19 are filled with dielectric material 20 to the surface
24 of gratings 18. FIG. 6 is the section view taken along line
section line B.sub.2-B.sub.2' where only substrate 12 and
dielectric 20 are visible. FIG. 7 is the section view taken along
section line C.sub.2-C.sub.2'. In this view, the lower or first
conductor 14, substrate 12 and connector material 16 are visible.
Dielectric material 20 may be deposited on multi-layered structure
210 by methods including, but not limited to, chemical vapor
deposition (CVD), physical vapor deposition (PVD), sputter
deposition, spin-coating, and dispensing of a liquid. Dielectric
material 20 may comprise silicon oxide or any low-k dielectric
material. Dielectric material 20 may be subjected to a
chemo-mechanical polish (CMP) process that results in multi-layered
structure 210 having crown surface 22. Crown surface 22 is defined
by an exposed surface 24 of each of gratings 18 and upper surfaces
27 of dielectric material 20. Portions of dielectric material 20
may be removed to form crown surface 22 using an etching process as
described in Coburn et al. "Some Chemical Aspects of the
Fluorocarbon Plasma Etching of Silicon and its Compounds," IBM J.
Res. Develop. 23, 33 (1979); Coburn et al., "Some Chemical Aspects
of the Fluorocarbon Plasma Etching of Silicon and it's Compounds,"
Solid State Technol. 22(4), 117, (1979); and van Roosmalen, "Dry
Etching for VLSI," Springer, p. 107 (1991); all of which are
incorporated herein by reference.
[0034] FIGS. 8-11 are top and section views of multi-layered
structure 210 after a second or upper conducting layer 26 has been
deposited over crown surface 22 thereby defining multi-layered
structure 310. FIG. 8 is the top view showing only conducting layer
26 and illustrating various section lines. FIG. 9 is the section
view taken along section line A.sub.3-A.sub.3' showing the material
layers of FIG. 5 along with the layer of conducting material 26.
FIG. 10 is the section view taken along section line
B.sub.3-B.sub.3' through the dielectric layer. In this view, only
conducting layer 26, dielectric layer 20 and substrate 12 are
visible. FIG. 11 is the section view taken along section line
C.sub.3-C.sub.3' through the channel 18 which has the various
material layers. In this view, the second or upper conductor 26,
the connector or switching layer 16, the lower conductor 14 and the
substrate are visible. Second conducting layer 26 may be formed
from various conducting materials (e.g., tungsten). Second
conducting layer 26, depending on composition, may be deposited on
multi-layered structure 210 by processes including, but not limited
to, chemical vapor deposition (CVD), physical vapor deposition
(PVD), sputter deposition, spin-coating, and dispensing of a
liquid.
[0035] FIGS. 12-16 are top and section views of multi-layered
structure 310 after removing portions of upper conductor 26 having
a pattern of strips 28 orthogonal to channels 18 thereby defining
multi-layered structure 410. The removed material defines open
channels 29. FIG. 12 is a top view of structure 310 showing various
section lines, strips 28 of upper conductor 26, and the exposed
sections of lower conductor 14 and dielectric 20. FIG. 13 is the
section view taken along section line A.sub.4-A.sub.4' through one
of the conducting strips 28. In this view, substrate 12, dielectric
strips 20 and the channels 18 filled with connector 16 and lower
conductor 14 are visible. FIG. 14 is the section view taken along
section line D.sub.4-D.sub.4' through exposed portions of channel
18 and dielectric strips 20. Because of the back drop of upper
conductor strip 28, this view shows the same layers as FIG. 13.
FIG. 15 is the section view taken along section line
B.sub.4-B.sub.4' through the dielectric strip 20. In this view,
substrate 12, strips 28 of conducting material 26, and portions of
dielectric material 20 are shown. FIG. 16 is the section view taken
along section line C.sub.4-C.sub.4' through lower conducting
channel 18. In this view, the material stack of upper conductor 26,
connector 16, lower conductor 14 that orthogonally intersect to
form a memory element are visible. The pattern formed in second
conducting layer 26 and switching or connector material stack layer
16 defines the strips or gratings 28. Gratings 28 extend along a
second direction D.sub.2 orthogonal to the first direction D.sub.1
shown in FIG. 2. The pattern formed in multi-layered structure 410
may use a lithography step followed by etching steps which stop at
first conducting layer 16. The lithography step and the etching
steps may be selected from the processes mentioned above with
respect to FIGS. 1-11. The section view taken along section line
A.sub.4-A.sub.4' of multi-layered structure 410 shows the
orthogonal overlapping of first and second conducting layers 14 and
26 are connected via switching or connector material stack layer 16
to form a memory element.
[0036] FIGS. 17-21 illustrate top and section views of
multi-layered structure 410 after deposition of dielectric material
20 to fill the open channels 29 thereby defining multi-layered
structure 510. FIG. 18 is the section view taken along section line
A.sub.5-A.sub.5'. Since the open channel 29 is not visible in this
view, the filling of channel 29 with dielectric material 20 does
not reveal differences from the view in FIG. 13. FIG. 19 is the
section view taken along line D.sub.5-D.sub.5' through the
dielectric 20 fill of channel 29. In this view, only dielectric 20,
lower conductor 14 and substrate 20 are visible. FIG. 20 is the
section view taken along section line B.sub.5-B.sub.5' through the
dielectric layer. The dielectric layer 20 blocks everything except
sections of upper conductor 26 and substrate 12. FIG. 21 is the
section view taken along section line C.sub.5-C.sub.5' through
channel 18 and lower conductor 14. In this view, the orthogonal
overlapping of first and second conducting layers 14 and 26 are
connected via switching material stack layer 16 to form a memory
element is visible wherein the open channels 29 are filled to the
top of upper conductor 26 with dielectric material 20.
Multi-layered structure 510 shows a top surface 30 having lines of
second conducting layer 26 separated by dielectric material 20.
FIG. 21 shows the upper conductors exposed at the surface. In many
applications, it may be necessary to cover the surface with a
dielectric layer before further processing.
[0037] Another embodiment for fabricating a cross-point memory
structure in a self-aligned process with two lithography steps is
described relative to FIGS. 22A-60. FIG. 22A illustrates a
multilayer structure including a substrate 112 (e.g., Si), a first
dielectric layer 114 (e.g., SiO.sub.2 or low k material), an etch
stop layer 116 (e.g., SiN, SiC, or Si(O)N), and a second dielectric
layer 118 (e.g., SiO.sub.2).
[0038] FIG. 22B is a top view of the multilayer structure 100. FIG.
23 is a section view taken along section line M.sub.1-M.sub.1' as
shown in FIG. 22B with the etched channels 122. Substrate 112 may
be formed from substantially the same materials as mentioned above
with respect to substrate 12 and FIG. 1. By appropriate masking and
multiple etching steps, channels may be etched through the layers
atop substrate 112.
[0039] Multi-layered structure 100 is shown after having a pattern
formed using the first lithography step. The patterns are etched
through first dielectric layer 114, etch stop layer 116, and second
dielectric layer 118 and define gratings 120 and trenches 122 along
a first direction V.sub.1 shown in FIG. 22B. The pattern may be
formed in multi-layered structure 100 using the first lithography
step to define the trenches 122 followed by etching steps selected
to stop on substrate 112. The lithography step and the etching
steps may be selected for any of the processes disclosed above with
respect to the embodiment described relative to FIGS. 1-11.
[0040] FIGS. 24 and 25 illustrate a further embodiment for
fabricating lower conductor strips 124. FIG. 25 is a section view
taken along section line M.sub.2-M.sub.2' as shown in FIG. 24. In
the embodiment of FIG. 25, the silicon substrate 112 is first doped
to N+ (124) in the channel 122 area. This is followed by doping the
channel 122 area to a P-type material (126). In this manner, a
diode PN junction is formed in the event it is desirable to have
the cross point memory allow conduction in only one direction when
a connector is conductive.
[0041] FIGS. 26 and 27 illustrate yet another embodiment for
forming lower conductor 124. FIG. 26 is similar to FIG. 24 with a
section view taken along line M.sub.3-M.sub.3'. In this embodiment,
a material such as aluminum or tungsten may be deposited within
trenches 122 and subsequently subjected to an etching process to
form first conducting layer 124 with a height not exceeding the
level of etch mask layer 116. FIG. 27 shows that the etch stop is
removed in the areas of trench 122.
[0042] FIGS. 28 and 29 illustrate views of further processing of
the structure of FIG. 23 wherein multiple layers are deposited to
form a multi-layer structure 1100. FIG. 29 is the top view and FIG.
28 is the section view along line N.sub.1-N.sub.1'. First, a
dielectric material is used to fill the trench 122. More
specifically, a dielectric material 128 is deposited within
trenches 122 to form a continuous dielectric layer with first
dielectric layer 114 and second dielectric layer 118 both shown in
FIG. 23. Dielectric layer 128 may comprise substantially the same
material as first and second dielectric layers 114 and 118
described above with respect to FIG. 23. In the following, this
dielectric layer may be referred to as layers 114 and 118 or simple
as a single layer 128. A resist layer 130 is then deposited on
dielectric layer 128. Layer 130 may comprise an organic material
such as amorphous carbon or a polymeric resist material. A hard
mask layer 132 is then deposited on resist layer 130. Hard mask
layer 132 may comprise materials including but not limited to
spin-on-glass, SiN, and SiC. Another resist layer 134 is then
deposited on hard mask layer 132.
[0043] FIG. 27 shows the structure 100 once lower conductors are
formed as discussed in FIGS. 22B-26. The dielectric material 128 is
deposited into the trenches 122 and over the dielectric stack as
shown in FIG. 29. At this stage, this dielectric 128 is planarized
using a process such as chemical mechanical polishing (CMP). An
organic material 130 such as amorphous carbon or a polymeric resist
material is deposited onto the dielectric stack comprising
dielectric 128 and etch stop 116. Next a hard mask film 132 is
deposited on layer 130. Hard mask 132 may be a spin-on-glass (SOG),
SiN, SiC, and etc. The hard mask may also comprise dual-top hard
mask which includes a thinner hard mask 134 (e.g., SiN) on top of a
thicker hard mask 132 (e.g., SOG). The SiN layer 134 may be made
thin enough to allow easy pattern transfer from a lithography
process such as imprint, photolithography, etc; and the lower SOG
is made thick enough to allow pattern transfer at least through the
deep amorphous carbon layer 130. A high-resolution lithography such
as 193 nm or 193 nm immersion or imprint lithography or EUV may be
used to create a pattern on top of the hard mask (or dual-top hard
mask).
[0044] Organic layer 130, hard mask layer 132, and resist layer 134
may be deposited to form the multi-layered structure 1100 by
methods including, but not limited to, chemical vapor deposition
(CVD), physical vapor deposition (PVD), sputter deposition,
spin-coating and dispensing of a liquid.
[0045] FIGS. 30-32 show a top view and section views of
multi-layered structure 1100 after a channel pattern is formed in
resist layer 134 orthogonal to channels 122 thereby defining
multi-layered structure 1200. FIG. 31 is the view taken along line
N.sub.2' N.sub.2' and FIG. 32 is the section view taken along line
O.sub.2-O.sub.2'. The pattern formed in resist layer 134 defines
gratings defined by lines 136 and trenches 138. The gratings extend
along a direction V.sub.2 orthogonal to the direction V1 shown in
FIG. 22. Trenches 138 may only extend down to hard mask layer 132
after a first etching step. In one embodiment pattern 132 may be
formed with an imprint mold where resist 134 is a formable layer.
Therefore, the first step would entail removing the resist in the
pattern channel 132 and further etching through to hard mask 132.
FIG. 32 shows the section view where all of the layers of structure
1200 are visible. The view in FIG. 32 shows resist 134 removed down
to hard mask 132.
[0046] FIGS. 33-35 show various views of multi-layered structure
1200 with resist 134 removed after the pattern of channels 138 are
formed in mask layer 132 thereby defining multi-layered structure
1300. FIG. 34 is the section view taken along line N.sub.3-N.sub.3'
and FIG. 35 is the section view taken along line O.sub.3-O.sub.3'.
The pattern formed in resist layer 132 defines gratings as lines
140 and trenches 142. Lines 140 extend along direction V.sub.2
orthogonal to the direction V1 of channels 122 shown in FIG. 22.
Trenches 142 may only extend down to organic layer 130 after a
second etching step. FIG. 34 shows the view where all of the layers
of structure 1300 are visible. The view in FIG. 35 shows resist 134
removed down to organic layer 130.
[0047] FIGS. 36-40 show various views of multi-layered structure
1300 with resist 132 removed once the pattern of trenches 142 has
been etched in multi-layered structure 1300. FIG. 36 is the top
view of structure 1300 with resist 130 removed, after etching the
pattern of trenches 142 through dielectric layers 114 and 128 in
areas not blocked by etch stop layer 116 thereby defining
multi-layered structure 1400. FIG. 37 is the section view along
section line N.sub.4-N.sub.4' through organic layer 130. Since this
view is through the total layered structure, all the layers are
visible along with the opening through the layer 116. FIG. 38 is
the section view along section line P.sub.4-P.sub.4' showing the
dielectric 128 removed down to the lower conductor 124. However,
all the layers are visible behind the via 144 down to lower
conductor 124. In this view, via edges differentiate the via 144
itself. FIG. 39 is the section view along line O.sub.4-O.sub.4'
showing lateral trench 146 down to a side view of the lower
conductor 124. Trench 146 provides the channel for an upper
conductor (not shown). In this view, dielectric layer 114 and mask
116 are shown in the background. FIG. 40 the section view along
section line Q.sub.4-Q.sub.4' through portions of layer 116. FIG.
40 provides another view of trench 146 wherein lower conductor 124
is not visible since it is blocked by dielectric 128.
[0048] The multi-layered structure 1400 has channels 146 and vias
144 in condition to receive a switching or connector material with
characteristics suitable for forming a read/write memory element.
The connector material is so called because it provides the
switchable connection between an upper conductor (not shown) and
lower conductor 124. FIG. 41 is a top view of multi-layered
structure 1400 after depositing a connector layer 148 thereby
forming the basis for multi-layered structure 1500. In this view,
connector material 148 is shown filling channel 146 over exposed
portions of layer 116 (see FIG. 36) and through vias 144 down to
the lower conductor 124. FIG. 42 is the section view along section
line N.sub.5-N.sub.5' orthogonal to lower conductor 124. Since this
view is through the total layered structure, all the remaining
layers are visible along with the opening through etch stop 116.
FIG. 43 is the section view taken along section line
P.sub.5-P.sub.5' through channel 146 and the just deposited
connector material 148. The connector material 148 is shown
extending to the surface of the structure and down to lower
conductor 124. FIG. 44 is the section view taken along line
O.sub.5-O.sub.5' axially through a lower conductor 124. In this
view, the connector material 148 is shown extending to the surface
of the structure 1500 and in the via 144 down to lower conductor
124. The section of organic layer 130 and dielectric layer 128 are
also visible on each side of the channels 146 with connector
material 148. FIG. 45 is the section view taken along section line
Q.sub.5-Q.sub.5' through the layers separating the lower conductor
124 lines. In this view, the via 144 down to conductor 124 is
blocked from view by sections of layers 116 and 128. The portion of
connector material 148 in channel 146 and extending to the surface
of structure 1500 is also visible. Connector layer 148 may be
deposited on multi-layered structure 1400 by processes including,
but not limited to, chemical vapor deposition (CVD), physical vapor
deposition (PVD), sputter deposition, spin-coating and dispensing
of a liquid.
[0049] FIG. 46 is a top view of multi-layered structure 1500 after
being subjected to an etching chemistry to remove portions of
connector layer 148 thereby defining multi-layered structure 1600.
In this view, the connector material 148 has been etched away in
all places except in the vias 144 to lower conductor 124. FIG. 47
is the section view along section line N.sub.6-N.sub.6' orthogonal
to lower conductor 124. Since this view is through the total
layered structure, all the remaining layers are visible along with
the opening through the etch stop layer 116 and shows the same
layers as FIG. 42. FIG. 48 is the section view along section line
P.sub.6-P.sub.6' showing the dielectric connector material 148
filling the via 144 down to lower conductor 124. In this view, all
the layers are visible behind the via 144 down to lower conductor
124 and the via edges differentiate the filled via 144 itself FIG.
49 is the view taken along line O.sub.6-O.sub.6'. In this view, the
connector material 148 fills the via to the surface of etch stop
layer 116. The layers of dielectric 128 and layer 130 separating
channels 146 are also visible in this view. FIG. 50 is the section
view taken along section line Q.sub.6-Q.sub.6' through the layers
separating the lower conductor 124 lines. In this view, sections of
layer 116 and 128 block the view of connector material 148 that
fills the via 144 down to lower conductor 124. Portions of
connector layer 148 may be removed such that a crown surface 150 is
formed as shown in FIG. 48. The crown surface 150 in FIG. 48 is
defined by an exposed surface 152 of etch stop layer 116 and upper
surface 154 of connector material 148.
[0050] FIG. 51 is a top view of multi-layered structure 1600 after
a upper conductor 168 is deposited in channel 146 orthogonal to
lower conductor 124 defining multi-layered structure 1700. In this
view, the upper conductor 168 fills channel 146 substantially to
the surface of organic layer 130. FIG. 52 is the section view along
section line N.sub.7-N.sub.7' through the layers separating
channels 146. FIG. 53 is the section view taken along section line
P.sub.7-P.sub.7' through the upper conductor 168. In this view,
upper conductor 168 blocks from view the layers separating channels
146. FIG. 54 is the view taken along line O.sub.7-O.sub.7' through
a lower conductor 124. In this view, the upper conductor is visible
from the connector material 148 to the top of organic layer 130.
FIG. 55 is the section view taken along section line
Q.sub.7-Q.sub.7' through lower the section of layers separating the
lower conductors 124. In this view, the portion of the upper
conductor 168 extending to the top of layer 130 in channels 146 is
visible. Lower conductor 124 and the connector material 148 are
blocked from view. The upper or second conducting layer 168 may
comprise copper and may be deposited on multi-layered structure
1700 by methods including, but not limited to, electroplating.
[0051] FIG. 56 is a top view of multi-layered structure 1700 after
being polished with a CMP process to remove organic layer 130 and
portions of conductor layer 168 thereby defining multi-layered
structure 1800. FIG. 57 is the section view along section line
N.sub.8-N.sub.8' through the layer section separating channels 146.
FIG. 58 is the section view taken along section line
P.sub.8-P.sub.8' through the upper conductor 168. In this view,
upper conductor 168 blocks from view the layers separating channels
146. FIG. 59 is the section view taken along section line
Q.sub.8-Q.sub.8' through a lower conductor 124. In this view, the
upper conductor is visible from the connector material 148 to the
top of organic layer 148. FIG. 60 is the section view taken along
section line Q.sub.8-Q.sub.8' through lower the section of layers
separating the lower conductors 124. In this view, the portion of
the upper conductor extending to the top of layer 128 in channels
146 is visible. Lower conductor 124 and the connector material 148
are blocked from view. Portions of second conducting layer 168 and
organic layer 130 may be removed such that a crown surface 158 may
be defined, as shown in FIGS. 59 and 60. Crown surface 158 is
defined by an exposed surface 160 of dielectric layer 128 and upper
surface 162 of second conducting layer 148.
[0052] The disclosed method essentially creates connectors 148
between the top and the bottom conductors (168 and 124,
respectively) wherever they intersect when overlaid orthogonally.
Therefore, if there are regions of the two conductor levels that
need to be isolated from one another, for e.g. regions where the
conductor levels are connected to other parts of the memory
circuitry, these regions may need to be handled differently. For
example, the lower conductors may not extend beyond the cross-point
area in one directional axis (e.g., X-axis) and the upper
conductors may not extend in another orthogonal axis (e.g.,
Y-axis). In this manner, the two conductor levels may be isolated
for further processing.
[0053] The embodiments of the present invention described above are
exemplary. Many changes and modifications may be made to the
disclosure recited above, while remaining within the scope of the
invention. Therefore, the scope of the invention should not be
limited by the above description, but instead should be determined
with reference to appended claims along with their full scope of
equivalents.
* * * * *