U.S. patent application number 12/806787 was filed with the patent office on 2010-12-23 for integrated circuit device.
This patent application is currently assigned to Tessera Technologies Hungary Kft... Invention is credited to Avner Badehi.
Application Number | 20100323475 12/806787 |
Document ID | / |
Family ID | 11071197 |
Filed Date | 2010-12-23 |
United States Patent
Application |
20100323475 |
Kind Code |
A1 |
Badehi; Avner |
December 23, 2010 |
Integrated circuit device
Abstract
An integrally packaged optronic integrated circuit device (310)
including an integrated circuit die (322) containing at least one
of a radiation emitter and radiation receiver and having top and
bottom surfaces formed of electrically insulative and mechanically
protective material, at least one of the surfaces (317) being
transparent to radiation, and electrically insulative edge surfaces
(314) having pads.
Inventors: |
Badehi; Avner; (Yehuda,
IL) |
Correspondence
Address: |
TESSERA;LERNER DAVID et al.
600 SOUTH AVENUE WEST
WESTFIELD
NJ
07090
US
|
Assignee: |
Tessera Technologies Hungary
Kft..
Budapest
HU
|
Family ID: |
11071197 |
Appl. No.: |
12/806787 |
Filed: |
August 20, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11588439 |
Oct 26, 2006 |
7781240 |
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12806787 |
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10385555 |
Mar 11, 2003 |
7157742 |
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11588439 |
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09601895 |
Sep 22, 2000 |
6646289 |
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PCT/IL99/00071 |
Feb 3, 1999 |
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10385555 |
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Current U.S.
Class: |
438/110 ;
257/E23.011; 438/25 |
Current CPC
Class: |
H01L 31/02327 20130101;
H01L 33/44 20130101; H01L 2924/014 20130101; H01L 27/14632
20130101; H01L 27/14618 20130101; H01L 27/14687 20130101; H01L
2224/24051 20130101; H01L 2224/24225 20130101; H01L 2924/01068
20130101; H01L 31/0203 20130101; H01L 33/486 20130101; H01L
2924/10253 20130101; H01L 2924/01006 20130101; H01L 2924/01014
20130101; H01L 24/24 20130101; H01L 24/97 20130101; H01L 2224/0401
20130101; H01L 31/02164 20130101; H01L 2924/01005 20130101; H01L
21/82 20130101; H01L 24/82 20130101; H01L 2924/01029 20130101; H01L
2221/68327 20130101; H01L 31/02002 20130101; H01L 31/125 20130101;
H01L 23/3114 20130101; H01L 2224/97 20130101; H01L 2924/01027
20130101; H01L 2924/01079 20130101; H01L 24/02 20130101; H01L 33/56
20130101; H01L 2924/01033 20130101; H01L 21/56 20130101; H01L 33/62
20130101; H01L 2924/01078 20130101; H01L 2224/94 20130101; H01L
33/0095 20130101; H01L 31/186 20130101; H01L 2924/01057 20130101;
H01L 33/52 20130101; H01L 2924/01077 20130101; H01L 2924/14
20130101; H01L 33/483 20130101; H01L 25/105 20130101; H01L 27/15
20130101; H01L 2924/01051 20130101; H01L 2924/10253 20130101; H01L
2924/00 20130101; H01L 2224/97 20130101; H01L 2224/82 20130101 |
Class at
Publication: |
438/110 ; 438/25;
257/E23.011 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 6, 1998 |
IL |
123207 |
Claims
1. A method of producing packaged optronic integrated circuit
devices comprising: (a) providing a transparent protective layer
overlying a first surface of a semiconductor wafer including a
plurality of dies; (b) providing an insulating layer overlying a
second surface of the wafer and having an outer surface facing away
from the wafer; (c) forming contacts electrically connected to the
dies, the contacts extending onto the outer surface of the
insulating layer; and (d) separating the dies from one another, the
step of forming the contacts being performed before completion of
the step of separating the dies from one another.
2. A method as claimed in claim 1 wherein the step of separating
the dies from one another includes forming notches extending
through the wafer between the dies before forming the contacts and
severing the transparent protective layer after forming the
contacts.
3. A method as claimed in claim 2 wherein the step of forming
notches exposes pads of the dies in the notches and the step of
forming contacts includes connecting the contacts to the pads in
the notches.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a continuation of U.S. patent
application Ser. No. 11/588,439, filed Oct. 26, 2006, which is a
divisional of U.S. patent application Ser. No. 10/385,555, filed
Mar. 11, 2003, which is a continuation of U.S. patent application
Ser. No. 09/601,895, filed Sep. 22, 2000, which in turn is a 371 of
International Application PCT/IL/99/00071, filed Feb. 3, 1999, the
disclosures of which are hereby incorporated by reference
herein.
FIELD OF THE INVENTION
[0002] The present invention relates to methods and apparatus for
producing integrated circuit devices and to integrated circuit
devices produced thereby and more particularly to an optronic
integrally packaged die.
BACKGROUND OF THE INVENTION
[0003] An essential step in the manufacture of all integrated
circuit devices is known as "packaging" and involves mechanical and
environmental protection of a silicon chip which is at the heart of
the integrated circuit as well as electrical interconnection
between predetermined locations on the silicon chip and external
electrical terminals.
[0004] At present three principal technologies are employed for
packaging semiconductors: wire bonding, tape automatic bonding
(TAB) and flip chip.
[0005] Wire bonding employs heat and ultrasonic energy to weld gold
bonding wires between bond pads on the chip and contacts on the
package.
[0006] Tape automatic bonding (TAB) employs a copper foil tape
instead of bonding wire. The copper foil tape is configured for
each specific die and package combination and includes a pattern of
copper traces suited thereto. The individual leads may be connected
individually or as a group to the various bond pads on the
chip.
[0007] Flip chips are integrated circuit dies which have solder
bumps formed on top of the bonding pads, thus allowing the die to
be "flipped" circuit side down and directly soldered to a
substrate. Wire bonds are not required and considerable savings in
package spacing may be realized.
[0008] The above-described technologies each have certain
limitations. Both wire bonding and TAB bonding are prone to bad
bond formation and subject the die to relatively high temperatures
and mechanical pressures. Both wire bond and TAB technologies are
problematic from a package size viewpoint, producing integrated
circuit devices having a die-to-package area ratio ranging from
about 10% to 60%.
[0009] The flip-chip does not provide packaging but rather only
interconnection. The interconnection encounters problems of
uniformity in the solder bumps as well as in thermal expansion
mismatching, which limits the use of available substrates to
silicon or materials which have thermal expansion characteristics
similar to those of silicon.
[0010] Optronic packages for semiconductors are known. Conventional
optronic packages used for imaging employ a ceramic housing onto
which is sealingly mounted a transparent window. Optronic packages
used for low level imaging, light emission and radiation detection,
including light detection, employ a clear plastic enclosure.
[0011] Described in applicant's published PCT Application WO
95/19645 are methods and apparatus for producing integrated circuit
devices, including, inter alia, integrally packaged dies having a
radiation transparent protective layer.
SUMMARY OF THE INVENTION
[0012] The present invention seeks to provide optronic integrated
circuit devices which are extremely compact as well as apparatus
and techniques for the production thereof.
[0013] There is thus provided in accordance with a preferred
embodiment of the present invention an integrally packaged optronic
integrated circuit device including: [0014] an integrated circuit
die containing at least one of a radiation emitter and radiation
receiver and having top and bottom surfaces formed of electrically
insulative and mechanically protective material, at least one of
the surfaces being transparent to radiation, and electrically
insulative edge surfaces having pads.
[0015] Preferably, the device also includes at least one spectral
filter associated with a radiation transparent protective surface
thereof.
[0016] Additionally in accordance with a preferred embodiment of
the present invention, the device includes a semiconductor
substrate which is sufficiently thin as to enable to device to be
responsive to back illumination.
[0017] Preferably, the device also includes at least one color
filter associated with a radiation transparent protective surface
thereof.
[0018] Further in accordance with a preferred embodiment of the
present invention, lenses may be integrally formed on a transparent
protective surface of the device.
[0019] Additionally in accordance with a preferred embodiment of
the present invention, light coupling bumps may be integrally
formed on a transparent protective surface of the device.
[0020] Further in accordance with a preferred embodiment of the
present invention a waveguide and other optical components
integrally formed on a transparent protective surface of the
device.
[0021] Additionally in accordance with a preferred embodiment of
the present invention, an optical grating may be integrally formed
on a transparent protective surface of the device.
[0022] Further in accordance with a preferred embodiment of the
present invention a polarizer may be formed on a transparent
protective surface of the device.
[0023] There is also provided in accordance with a preferred
embodiment of the present invention an integrally packaged optronic
integrated circuit device including: [0024] an integrated circuit
die containing at least one of a radiation emitter and radiation
receiver and having top and bottom surfaces formed of electrically
insulative and mechanically protective material, at least one of
the surfaces being transparent to radiation, the integrally
packaged optronic integrated circuit device being characterized in
that its longest dimension does not exceed the longest dimension of
the die by more than 20%. Preferably the integrally packaged
optronic integrated circuit device is characterized in that its
longest dimension does not exceed the longest dimension of the die
by more than 10%. More preferably the integrally packaged optronic
integrated circuit device is characterized in that its longest
dimension does not exceed the longest dimension of the die by more
than 5%.
[0025] There is also provided in accordance with a preferred
embodiment of the present invention a method for producing an
integrally packaged optronic integrated circuit device comprising
the steps of: [0026] forming electrical circuits onto a
semiconductor wafer; [0027] forming at least one transparent
mechanical protective layer onto said semiconductor wafer over said
electrical circuits; [0028] forming solderable contacts onto said
semiconductor wafer; and thereafter, dicing said wafer into
individual packaged dies.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The present invention will be understood and appreciated
more fully from the following detailed description, taken in
conjunction with the drawings in which:
[0030] FIGS. 1A and 1B are respective top view and bottom view
simplified pictorial illustrations of an integrally packaged
optronic integrated circuit device constructed and operative in
accordance with a preferred embodiment of the present
invention;
[0031] FIG. 1C is a bottom view simplified pictorial illustration
of an integrally packaged optronic integrated circuit device of the
type shown in FIGS. 1A and 1B, constructed and operative in
accordance with another preferred embodiment of the present
invention;
[0032] FIG. 2 is a simplified pictorial illustration of the
attachment of a transparent protective packaging layer to a wafer
containing a plurality of integrated circuit dies;
[0033] FIG. 3 is a simplified pictorial illustration of showing the
individual dies on the wafer as seen through the transparent
protective packaging layer attached thereto;
[0034] FIGS. 4A, 4B, 4C and 4D are sectional illustrations of
various stages in the manufacture of integrally packaged optronic
integrated circuit devices in accordance with a preferred
embodiment of the present invention;
[0035] FIG. 5 is a partially cut away detailed pictorial
illustration of an integrally packaged optronic integrated circuit
device produced from the wafer of FIG. 4D;
[0036] FIGS. 6, 7A, 7B, 8A and 8B are sectional illustrations of
various stages in the manufacture of the integrally packaged
optronic integrated circuit device shown in FIGS. 1A, 1B, 1C &
5;
[0037] FIGS. 9, 10A and 10B together provide a simplified block
diagram illustration of apparatus for carrying out the method of
the present invention;
[0038] FIGS. 11A, 11B, 11C, 11D and 11E are simplified pictorial
illustrations of five alternative embodiments of an integrated
circuit device constructed and operative in accordance with yet
another preferred embodiment of the present invention and including
spectral filters and/or anti-reflective coatings;
[0039] FIGS. 12A, 12B and 12C are simplified pictorial
illustrations of three alternative embodiments of an integrally
packaged optronic integrated circuit device which is designed for
back illumination;
[0040] FIGS. 13A, 13B and 13C are simplified pictorial
illustrations of three alternative embodiments of an integrally
packaged optronic integrated circuit device constructed and
operative in accordance with still another preferred embodiment of
the present invention wherein color array filters are integrated
with the integrally packaged optronic integrated circuit
device;
[0041] FIGS. 14A, 14B, 14C and 14D are simplified pictorial
illustrations of four alternative embodiments of an integrally
packaged optronic integrated circuit device constructed and
operative in accordance with another preferred embodiment of the
present invention having lenses integrally formed on a transparent
protective surface thereof;
[0042] FIGS. 15A and 15B are simplified pictorial illustrations of
two alternative embodiments of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with another preferred embodiment of the present invention having
light coupling bumps integrally formed on a transparent protective
surface thereof;
[0043] FIGS. 16A and 16B are simplified pictorial illustrations of
two alternative embodiments of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with yet another preferred embodiment of the present invention
having a waveguide and other optical components integrally formed
on a transparent protective surface thereof;
[0044] FIGS. 17A and 17B are simplified pictorial illustrations of
two alternative embodiments of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with still another preferred embodiment of the present invention
wherein a polarizer is integrated with the integrally packaged
optronic integrated circuit device;
[0045] FIGS. 18A and 18B are simplified pictorial illustrations of
two alternative embodiments of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with still another preferred embodiment of the present invention
wherein an optical grating is integrated with the integrally
packaged optronic integrated circuit device.
[0046] FIGS. 19A and 19B are simplified pictorial illustrations of
two alternative embodiments of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with yet another preferred embodiment of the present invention
wherein the package is formed with a desired geometrical
configuration;
[0047] FIGS. 20A and 20B are simplified pictorial illustrations of
two alternative embodiments of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with yet another preferred embodiment of the present invention
wherein edges of the package are coated with an opaque coating;
[0048] FIG. 21 is a simplified pictorial illustration of an
integrally packaged optronic integrated circuit device constructed
and operative in accordance with still another preferred embodiment
of the present invention and having an octagonal configuration;
and
[0049] FIG. 22 is a simplified pictorial illustration of a cutting
pattern employed to produce integrated circuits of the type shown
in FIG. 21.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0050] Reference is now made to FIGS. 1A-22, which illustrate the
production of integrated circuit devices in accordance with a
preferred embodiment of the present invention.
[0051] FIGS. 1A and 1B together illustrate a preferred embodiment
of integrated circuit device constructed and operative in
accordance with a preferred embodiment of the present invention.
The integrated circuit device includes a relatively thin and
compact, environmentally protected and mechanically strengthened
integrated circuit package 10 having a multiplicity of electrical
contacts 12 plated along the edge surfaces 14 thereof.
[0052] In accordance with a preferred embodiment of the invention,
contacts 12 extend over edge surfaces onto the planar surfaces 16
of the, package. This contact arrangement permits both flat surface
mounting and edge mounting of package 10 onto a circuit board. It
is noted that the integrated circuit package 10 may include one or
more of the following elements (not shown): an integrally formed
dichroic filter, color filter, antireflective coating, polarizer,
optical grating, integrated wave guide and optical coupling
bumps.
[0053] FIG. 1C illustrates an alternative embodiment of the present
invention wherein solderable bumps 17 are provided at the ends of
each contact 12. Preferably, the solderable bumps 17 are arranged
in a predetermined array.
[0054] In accordance with a preferred embodiment of the present
invention, and as illustrated in FIG. 2 and FIG. 4A, a complete
silicon wafer 20 having a plurality of finished dies 22 formed
thereon by conventional techniques, is bonded at its active surface
24 to a radiation transparent protective insulating cover plate 26
via a layer 28 of epoxy. The insulating cover plate 26 typically
comprises glass, quartz, sapphire or any other suitable radiation
transparent insulative substrate.
[0055] The cover plate 26 may be colored or tinted in order to
operate as a spectral filter. Alternatively, a dichroic or colored
spectral filter may be formed on at least one surface of the cover
plate 26.
[0056] It is a particular feature of the present invention that
cover plate 26 and epoxy layer 28 are preferably transparent to
radiation in a spectral region useful for optronic
applications.
[0057] It is appreciated that certain steps in the conventional
fabrication of silicon wafer 20 may be eliminated when the wafer is
used in accordance with the present invention. These steps include
the provision of via openings above pads, wafer back grinding and
wafer back metal coating.
[0058] The complete silicon wafer 20 may be formed with an integral
color filter array by conventional lithography techniques at any
suitable location therein. Prior to the bonding step of FIG. 4A, a
filter may be formed and configured by conventional techniques over
the cover plate 26, such that the filter plane lies between cover
plate 26 and the epoxy layer 28.
[0059] Following the bonding step described hereinabove, the
silicon wafer is preferably ground down to a decreased thickness,
typically 100 microns, as shown in FIG. 4B. This reduction in wafer
thickness is enabled by the additional mechanical strength provided
by the bonding thereof of the insulating cover plate 26.
[0060] Following the reduction in thickness of the wafer, which is
optional, the wafer is etched, using a photolithography process,
along its back surface along predetermined dice lines which
separate the individual dies. Etched channels 30 are thus produced,
which extend entirely through the thickness of the silicon
substrate, typically 100 microns. The etched wafer is shown in FIG.
4C.
[0061] The aforementioned etching typically takes place in
conventional silicon etching solution, such as a combination of
2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5%
water, so as to etch the silicon down to the field oxide layer, as
shown in FIG. 4C.
[0062] The result of the silicon etching is a plurality of
separated dies 40, each of which includes silicon of thickness
about 100 microns.
[0063] As seen in FIG. 4D, following the silicon etching, a second
insulating packaging layer 42 is bonded over the dies 40 on the
side thereof opposite to insulating packaging layer 26. A layer 44
of epoxy lies between the dies 40 and the layer 42 and epoxy also
fills the interstices between dies 40. In certain applications,
such as the embodiment of FIGS. 12A-12C, the packaging layer 42 and
the epoxy layer 44 are both transparent.
[0064] The sandwich of the etched wafer 20 and the first and second
insulating packaging layers 26 and 42 is then partially cut along
lines 50, lying along the interstices between adjacent dies 40 to
define notches along the outlines of a plurality of pre-packaged
integrated circuits. It is a particular feature of the invention
that lines 50 are selected such that the edges of the dies along
the notches are distanced from the outer extent of the silicon 40
by at least a distance d, as shown in FIGS. 4D and 5, to which
reference is now additionally made.
[0065] It is a particular feature of the present invention that
partial cutting of the sandwich of FIG. 4D along lines 50 exposes
edges of a multiplicity of pads 34 on the wafer 20, which pad
edges, when so exposed, define contact surfaces 51 on dies 40.
[0066] Referring now particularly to FIG. 5, at least one
insulating layer, including the field oxide layer, is shown at
reference numeral 32 and metal pads are shown at reference numeral
34. An over-metal insulating layer is shown at reference numeral
36. The color filter plane is shown at reference numeral 38.
[0067] Reference is now made to FIGS. 6, 7A, 7B, 8A and 8B, which
illustrate further steps in the manufacture of integrated circuit
devices in accordance with a preferred embodiment of the present
invention.
[0068] FIG. 6 illustrates at reference numeral 54, a preferred
cross sectional configuration of a notch produced by partially
cutting as described hereinabove in connection with FIG. 5.
Vertical lines 56 indicate the intersection of the notch 54 with
the pads 34, defining exposed sectional pad surfaces 51. Vertical
lines 58 indicate the location of a subsequent final cut which
separates the dies into individual integrated circuits at a later
stage.
[0069] FIGS. 7A and 7B illustrate the formation of metal contacts
12 along the inclined edges 14 and part of the top surface 16.
These contacts, which may be formed by any suitable metal
deposition technique, are seen to extend inside notch 54, thus
establishing electrical contact with surfaces 51 of pads 34. FIG.
7A shows a configuration corresponding to that of FIGS. 1A and 1B
without solderable bumps, while FIG. 7B shows the provision of
solderable bumps 17 on contacts 12, as illustrated in FIG. 1C.
[0070] It is a particular feature of the present invention that
metal contacts are formed onto the dies in electrical contact with
surfaces 51 of pads 34 without first separating the dies into
individual chips.
[0071] FIGS. 8A and 8B illustrate subsequent dicing of the
individual dies on the wafer, subsequent to metal contact formation
thereon, into individual pre-packaged integrated circuit devices.
FIG. 8A shows a configuration corresponding to that of FIGS. 1A and
1B without solderable bumps, while FIG. 8B shows the provision of
solderable bumps 17 on contacts 12, as illustrated in FIG. 1C.
[0072] Reference is now made to FIGS. 9, 10A and 108, which
together illustrate apparatus for producing integrated circuit
devices in accordance with a preferred embodiment of the present
invention. A conventional wafer fabrication facility 180 provides
complete wafers 20. Individual wafers 20 are bonded on their active
surfaces to protective layers, such as glass layers 26, using epoxy
28, by bonding apparatus 182, preferably having facilities for
rotation of the wafer 20, the layer 26 and the epoxy 28 so as to
obtain even distribution of the epoxy.
[0073] The bonded wafer (FIG. 3) is thinned at its non-active
surface as by grinding apparatus 184, such as Model 32BTGW using
12.5 A abrasive, which is commercially available from Speedfam
Machines Co. Ltd. of England.
[0074] The wafer is then-etched at its non-active surface,
preferably by photolithography, such as by using conventional
spin-coated photoresist, which is commercially available from
Hoechst, under the brand designation AZ 4562.
[0075] The photoresist is preferably mask exposed by a suitable UV
exposure system 185, such as a Karl Suss Model KSMA6, through a
lithography mask 186 to define etched channels 30.
[0076] The photoresist is then developed in a development bath (not
shown), baked and then etched in a silicon etch solution 190
located in a temperature controlled bath 188. Commercially
available equipment for this purpose include a Chemkleen bath and a
WHRV circulator both of which are manufactured by Wafab Inc. of the
U.S.A. A suitable conventional silicon etching solution is Isoform
Silicon etch, which is commercially available from Micro-Image
Technology Ltd. of England. The wafer is conventionally rinsed
after etching. The resulting etched wafer is shown in FIG. 4C.
[0077] Alternatively, the foregoing wet chemical etching step may
be replaced by dry plasma etching.
[0078] The etched wafer is bonded on the non-active side to another
protective layer 42 by bonding apparatus 192, which may be
essentially the same as apparatus 182, to produce a doubly bonded
wafer sandwich as shown in FIG. 4D.
[0079] Notching apparatus 194 partially cuts the bonded wafer
sandwich of FIG. 4D to a configuration shown in FIG. 5.
[0080] The notched wafer is then subjected to anticorrosion
treatment in a bath 196, containing a chromating solution 198, such
as described in any of the following U.S. Pat. Nos. 2,501,956;
2,851,385; and 2,796,370, the disclosure of which is hereby
incorporated by reference.
[0081] Conductive layer deposition apparatus 200, which operates by
vacuum deposition techniques, such as a Model 903M sputtering
machine manufactured by Material Research corporation of the
U.S.A., is employed to produce a conductive layer on one or more
surfaces of each die of the wafer as shown in FIG. 7.
[0082] Configuration of contact strips, as shown in FIG. 7, is
carried out preferably by using conventional electro-deposited
photoresist, which is commercially available from DuPont under the
brand name Primecoat or from Shipley, under the brand name Eagle.
The photoresist is applied to the wafers in a photoresist bath
assembly 202 which is commercially available from DuPont or
Shipley.
[0083] The photoresist is preferably light configured by a UV
exposure system 204, which may be identical to system 185, using a
mask 205 to define suitable etching patterns. The photoresist is
then developed in a development bath 206, and then etched in a
metal etch solution 208 located in an etching bath 210, thus
providing a conductor configuration such as that shown in FIGS. 1A
and 1B.
[0084] The exposed conductive strips shown in FIG. 7 are then
plated, preferably by electroless plating apparatus 212, which is
commercially available from Okuno of Japan.
[0085] The wafer is then diced into individual prepackaged
integrated circuit devices. Preferably the dicing blade 214 should
be a diamond resinoid blade of thickness 4-12 mils. The resulting
dies appear as illustrated generally in FIGS. 1A and 1B.
[0086] FIG. 10A shows apparatus for producing an integrated circuit
configuration corresponding to that of FIGS. 1A and 1B without
solderable bumps, while FIG. 10B shows apparatus for producing an
integrated circuit configuration corresponding to that of FIG. 1C
having solderable bumps. The embodiment of FIG. 10B is identical to
that of FIG. 10A, apart from the additional provision of bump
forming apparatus 213 downstream of the electroless plating
apparatus 212.
[0087] Reference is now made to FIGS. 11A-11E, which illustrate
five alternative preferred embodiments of integrated circuit device
constructed and operative in accordance with another preferred
embodiment of the present invention and includes a relatively thin
and compact, environmentally protected and mechanically
strengthened integrated circuit package 310 having a multiplicity
of electrical contacts 312 plated along the edge surfaces 314
thereof.
[0088] FIG. 11A shows a dichroic filter and/or antireflective
coating 315 formed on an outer facing surface 316 of a transparent
protective layer 317. FIG. 11B illustrates a coating 318, which may
be identical to coating 315, which is formed on an inner facing
surface 319 of transparent protective layer 317. FIG. 11C shows
both coatings 315 and 318 on respective surfaces 316 and 319 of
transparent protective layer 317. Optronic components are formed on
a surface 320 of a silicon substrate 322 of conventional thickness,
typically 100 microns. Surface 320 faces transparent protective
layer 317.
[0089] FIG. 11D shows an absorption filter 323 formed on outer
facing surface 316 of transparent protective layer 317. FIG. 11E
shows an absorption filter 323, having formed thereon an
anti-reflective coating 324, formed on outer facing surface 316 of
transparent protective layer 317.
[0090] Reference is now made to FIGS. 12A-12C, which illustrate
three alternative preferred embodiments of integrated circuit
device which include a relatively thin and compact, environmentally
protected and mechanically strengthened integrated circuit package
330 having a multiplicity of electrical contacts 332 plated along
the edge surfaces 334 thereof.
[0091] In contrast to the embodiments of FIGS. 11A-11E, the
integrated circuit devices of FIGS. 12A-12C are designed for back
illumination and therefore employ a thinned silicon substrate 336,
typically having a thickness of 12-15 microns.
[0092] Whereas in the embodiment of FIGS. 11A-11E, the optronic
components are formed on a surface 320 which faces a transparent
protective layer 317, in the embodiment of FIGS. 12A-12B, the
components may be formed on a surface 340 of substrate 336, which
surface 340 faces away from the corresponding transparent
protective layer 337. The extreme thickness of the substrate 336 in
the embodiments of FIGS. 12A-12C enables the optronic components on
surface 340 to be exposed to light impinging via transparent
protective layer 337 by back exposure.
[0093] It is appreciated that silicon is transparent to certain
radiation spectra, such as IR radiation. When an IR responsive
device is provided, the embodiment of FIGS. 12A-12C can be
constructed without a thinned silicon substrate.
[0094] FIG. 12A shows a dichroic filter and/or antireflective
coating 345 formed on an outer facing surface 346 of the
transparent protective layer 337. FIG. 12B illustrates a coating
348, which may be identical to coating 345, which is formed on an
inner facing surface 349 of transparent protective layer 337. FIG.
12C shows both coatings 345 and 348 on respective surfaces 346 and
349 of transparent protective layer 337.
[0095] The modifications shown in FIGS. 11D and 11E may also be
embodied in the configuration of FIGS. 12A-12C.
[0096] Reference is now made to FIGS. 13A, 13B and 13C, which
illustrate three alternative preferred embodiments of integrated
circuit device constructed and operative in accordance with another
preferred embodiment of the present invention and includes a
relatively thin and compact, environmentally protected and
mechanically strengthened integrated circuit package 350 having a
multiplicity of electrical contacts 352 plated along the edge
surfaces 354 thereof.
[0097] FIG. 13A shows a color filter, such as an RGB or masking
filter, 355 formed on an outer facing surface 356 of a transparent
protective layer 357. FIG. 13B illustrates a filter 358, which may
be identical to filter 355, which is formed on an outer facing
surface 359 of a silicon substrate 362. FIG. 13C shows both filters
355 and 358 on respective surfaces 356 and 359.
[0098] It is appreciated that filter 356 may alternatively be
located on an inner facing surface of transparent protective layer
357.
[0099] Reference is now made to FIGS. 14A, 14B, 14C and 14D, which
illustrate four alternative embodiments of an integrally packaged
optronic integrated circuit device constructed and operative in
accordance with another preferred embodiment of the present
invention having lenses integrally formed on a transparent
protective surface thereof.
[0100] The embodiment of FIG. 14A may be identical to that of FIG.
11A without the coating and is further distinguished therefrom in
that it has a transparent protective layer 370 which is formed with
an array of microlenses 372 on an outer facing surface 374
thereof.
[0101] The embodiment of FIG. 14B may be identical to that of FIG.
12A without the coating and is further distinguished therefrom in
that it has a transparent protective layer 380 which is formed with
an array of microlenses 382 on an outer facing surface 384
thereof.
[0102] In the illustrated embodiment of FIGS. 14A and 14B, the
microlenses 372 and 382 respectively are formed of the same
material as than of transparent protective layers 370 and 380
respectively. Alternatively, microlenses 372 and 382 may be formed
of a material different from that of respective transparent
protective layers 370 and 380.
[0103] The embodiment of FIG. 14C corresponds to that of FIG. 14A.
However in the embodiment of FIG. 14C, an array of microlenses 385
is formed on an inner facing surface of transparent protective
layer 370. In the illustrated embodiment of FIG. 14C, the
microlenses 385 are formed of a different material than of
transparent protective layer 370. Alternatively, microlenses 385
may be formed of the same material as that of transparent
protective layer 370.
[0104] The embodiment of FIG. 14D corresponds to that of FIG. 14B.
However in the embodiment of FIG. 14D, similarly to the embodiment
of FIG. 14C, an array of microlenses 387 is formed on an inner
facing surface of transparent protective layer 380. In the
illustrated embodiment of FIG. 14D, the microlenses 387 are formed
of a different material than of transparent protective layer 380.
Alternatively, microlenses 387 may be formed of the same material
as that of transparent protective layer 380.
[0105] In the embodiments of FIGS. 14C and 14D, the index of
refraction of the microlenses 385 and 387 respectively must exceed
that of an epoxy layer 388 underlying them.
[0106] Reference is now made to FIGS. 15A and 15B, which are
simplified pictorial illustrations of two alternative embodiments
of an integrally packaged optronic integrated circuit device
constructed and operative in accordance with another preferred
embodiment of the present invention having light coupling bumps
integrally formed on a transparent protective surface thereof.
[0107] The embodiment of FIG. 15A may be identical to that of FIG.
11A without the coating and is further distinguished therefrom in
that it has a light coupling bump 390 formed on a transparent
protective layer 392. A waveguide 394 is shown optically coupled to
the transparent protective layer 392 via bump 390. Preferably the
bump 390 is formed of a transparent organic material which is
somewhat compliant such that mechanical pressure produces a slight
deformation thereof and enables an evanescent light wave to pass
through an interface defined therewith.
[0108] The embodiment of FIG. 15B may be identical to that of FIG.
12A without the coating and is further distinguished therefrom in
that it has a light coupling bump 396 formed on a transparent
protective layer 398. A waveguide 399 is shown optically coupled to
the transparent protective layer 398 via bump 396.
[0109] Reference is now made to FIGS. 16A and 16B which are
simplified pictorial illustrations of two alternative embodiments
of an integrally packaged optronic integrated circuit device
constructed and operative in accordance with yet another preferred
embodiment of the present invention having a waveguide and other
optical components integrally formed on a transparent protective
surface thereof.
[0110] The embodiment of FIG. 16A may be identical to that of FIG.
11A without the coating and is further distinguished therefrom in
that it has a wave guide 400 and possibly other optical elements
(not shown) formed on a transparent protective layer 402, as by
conventional integrated optics techniques. This arrangement enables
optical communication between an optronic component formed on a
silicon substrate 404 via the transparent protective layer 402 and
the wave guide 400.
[0111] The embodiment of FIG. 16B may be identical to that of FIG.
12A without the coating and is further distinguished therefrom in
that it has a wave guide 410 and possibly other optical elements
(not shown) formed on a transparent protective layer 412, as by
conventional integrated optics techniques. This arrangement enables
optical communication between an optronic component formed on a
silicon substrate 414 via the transparent protective layer 412 and
the wave guide 410.
[0112] Reference is now made to FIGS. 17A and 17B, which are
simplified pictorial illustrations of two alternative embodiments
of an integrally packaged optronic integrated circuit device
constructed and operative in accordance with still another
preferred embodiment of the present invention wherein a polarizer
is integrated with the integrally packaged optronic integrated
circuit device.
[0113] The embodiment of FIG. 17A may be identical to that of FIG.
11A without the coating and is further distinguished therefrom in
that it has a polarizer 420 which is on an outer facing surface 422
of a transparent protective layer 424.
[0114] The embodiment of FIG. 17B may be identical to that of FIG.
12A without the coating and is further distinguished therefrom in
that it has a polarizer 430 which is on an outer facing surface 432
of a transparent protective layer 434.
[0115] Reference is now made to FIGS. 18A and 18B, which are
simplified pictorial illustrations of two alternative embodiments
of an integrally packaged optronic integrated circuit device
constructed and operative in accordance with still another
preferred embodiment of the present invention wherein an optical
grating is integrated with the integrally packaged optronic
integrated circuit device.
[0116] The embodiment of FIG. 18A may be identical to that of FIG.
11A without the coating and is further distinguished therefrom in
that it has a transparent protective layer 440 which is formed with
an optical grating 442 on an outer facing surface 444 thereof.
[0117] The embodiment of FIG. 18B may be identical to that of FIG.
12A without the coating and is further distinguished therefrom in
that it has a transparent protective layer 450 which is formed with
an optical grating 452 on an outer facing surface 454 thereof.
[0118] Reference is now made to FIGS. 19A and 19B which may be
generally similar in all relevant respects to respective FIGS. 11A
and 12A respectively. The embodiment of FIGS. 19A and 19B is
characterized in that a transparent protective layer 460 is
provided with a particular edge configuration, preferably to enable
it to be located in an aperture. In FIGS. 19A and 19B, the
transparent protective layer 460 is shown with a peripheral edge
defining a step 462. It is appreciated that any other suitable
configuration may also be provided for the transparent protective
layer 460.
[0119] Reference is now made to FIGS. 20A and 20B, which are
simplified pictorial illustrations of two alternative embodiments
of an integrally packaged optronic integrated circuit device
constructed and operative in accordance with yet another preferred
embodiment of the present invention wherein edges of the package
are coated with an opaque coating.
[0120] The embodiment of FIG. 20A may correspond to that of FIG.
19A wherein the transparent protective layer 460 may be provided
with an opaque coating 464 at its peripheral edge which may cover
step 462 and may also cover the edge of the outer facing surface
adjacent thereto.
[0121] The embodiment of FIG. 20B may correspond generally to that
of FIG. 11A wherein a transparent protective layer 470 may be
provided with an opaque coating 472 at its peripheral edge which
may also cover the edge of the outer facing surface adjacent
thereto.
[0122] Reference is now made to FIG. 21, which is a simplified
pictorial illustration of an integrally packaged optronic
integrated circuit device constructed and operative in accordance
with still another preferred embodiment of the present invention
and having an octagonal configuration. This configuration is
preferred for compact applications, such as endoscopes which a high
density of focal plane sensors and electronics is required.
[0123] FIG. 22 is a simplified pictorial illustration of a cutting
pattern employed to produce integrated circuits of the type shown
in FIG. 21. The cutting pattern of FIG. 22, which is shown overlaid
on a wafer 480, comprises six consecutive cuts for each die.
[0124] It will be appreciated by persons skilled in the art that
the present invention is not limited to what has been particularly
shown and described hereinabove. Rather the scope of the present
invention includes both combinations and subcombinations of the
various features described hereinabove as well as modifications and
variations thereof as would occur to a person of skill in the art
upon reading the foregoing specification and which are not in the
prior art.
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