U.S. patent application number 12/480254 was filed with the patent office on 2010-12-09 for mosfet on silicon-on-insulator with internal body contact.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to JIN CAI, STEVEN J. KOESTER, AMLAN MAJUMDAR.
Application Number | 20100308405 12/480254 |
Document ID | / |
Family ID | 43263957 |
Filed Date | 2010-12-09 |
United States Patent
Application |
20100308405 |
Kind Code |
A1 |
CAI; JIN ; et al. |
December 9, 2010 |
MOSFET ON SILICON-ON-INSULATOR WITH INTERNAL BODY CONTACT
Abstract
A semiconductor device is disclosed that includes a
semiconductor-on-insulator substrate including a buried insulator
layer and an overlying semiconductor layer. Source extension and
drain extension regions are formed in the semiconductor layer. A
deep drain region and a deep source region are formed in the
semiconductor layer. A drain metal-semiconductor alloy contact is
located on the upper portion of the deep drain region and abuts the
drain extension region. A source metal-semiconductor alloy contact
abuts the source extension region. The deep source region is
located below and contacts a first portion of the source alloy
contact. The deep source region is not located below and does not
contact a second portion of the source alloy contact, such that the
second portion of the source alloy contact is an internal body
contact that directly contacts the semiconductor layer.
Inventors: |
CAI; JIN; (Courtlandt Manor,
NY) ; KOESTER; STEVEN J.; (Ossining, NY) ;
MAJUMDAR; AMLAN; (White Plains, NY) |
Correspondence
Address: |
FLEIT GIBBONS GUTMAN BONGINI & BIANCO P.L.
551 NW 77TH STREET, SUITE 111
BOCA RATON
FL
33487
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
43263957 |
Appl. No.: |
12/480254 |
Filed: |
June 8, 2009 |
Current U.S.
Class: |
257/347 ;
257/E21.415; 257/E29.286; 438/151 |
Current CPC
Class: |
H01L 29/0847 20130101;
H01L 29/41733 20130101; H01L 29/78612 20130101; H01L 29/66659
20130101; H01L 29/7835 20130101; H01L 29/78621 20130101 |
Class at
Publication: |
257/347 ;
438/151; 257/E29.286; 257/E21.415 |
International
Class: |
H01L 29/786 20060101
H01L029/786; H01L 21/336 20060101 H01L021/336 |
Claims
1. A semiconductor device comprising: a semiconductor-on-insulator
substrate including a buried insulator layer and an overlying
semiconductor layer, the semiconductor layer being doped with a
dopant of a first conductivity type; a gate located on the
semiconductor layer, the gate including a gate dielectric layer
located on the semiconductor layer and a gate conductor layer
located on the gate dielectric layer; a source extension region and
a drain extension region in the semiconductor layer, the source
extension region and the drain extension region contacting the gate
dielectric layer, the source extension region and the drain
extension region being doped with a dopant of a second conductivity
type, which is opposite the first conductivity type; a deep drain
region in the semiconductor layer, the deep drain region contacting
the drain extension region and abutting the buried insulator layer;
a deep source region in the semiconductor layer, the deep source
region contacting the source extension region and abutting the
buried insulator layer, the deep drain region and the deep source
region being doped with a dopant of the second conductivity type; a
drain metal-semiconductor alloy contact located on the upper
portion of the deep drain region and abutting the drain extension
region; and a source metal-semiconductor alloy contact abutting the
source extension region, wherein the deep source region is located
below and contacts a first portion of the source
metal-semiconductor alloy contact, and the deep source region is
not located below and does not contact a second portion of the
source metal-semiconductor alloy contact, such that the second
portion of the source metal-semiconductor alloy contact is an
internal body contact that directly contacts the semiconductor
layer.
2. The semiconductor device of claim 1, wherein the source and
drain metal-semiconductor alloy contact comprise a metal
silicide.
3. The semiconductor device of claim 1, wherein the semiconductor
layer comprises a shallow trench isolation region surrounding an
active area comprising silicon, and the source and drain extension
regions and the deep source and drain regions are all formed in the
active area.
4. The semiconductor device of claim 1, wherein the second portion
is located at one end of the source metal-semiconductor alloy
contact.
5. The semiconductor device of claim 1, wherein the deep source
region is not located below and does not contact a third portion of
the source metal-semiconductor alloy contact, such that the third
portion of the source metal-semiconductor alloy contact is an
internal body contact that directly contacts the semiconductor
layer, and the first portion separates the second portion from the
third portion.
6. The semiconductor device of claim 5, wherein the deep source
region is located below and contacts a fourth portion of the source
metal-semiconductor alloy contact, and the deep source region is
not located below and does not contact a fifth portion of the
source metal-semiconductor alloy contact, such that the fifth
portion of the source metal-semiconductor alloy contact is an
internal body contact that directly contacts the semiconductor
layer, and the fourth portion separates the first portion from the
fifth portion.
7. An integrated circuit comprising a circuit supporting substrate
including a semiconductor device, the semiconductor device
comprising: a semiconductor-on-insulator substrate including a
buried insulator layer and an overlying semiconductor layer, the
semiconductor layer being doped with a dopant of a first
conductivity type; a gate located on the semiconductor layer, the
gate including a gate dielectric layer located on the semiconductor
layer and a gate conductor layer located on the gate dielectric
layer; a source extension region and a drain extension region in
the semiconductor layer, the source extension region and the drain
extension region contacting the gate dielectric layer, the source
extension region and the drain extension region being doped with a
dopant of a second conductivity type, which is opposite the first
conductivity type; a deep drain region in the semiconductor layer,
the deep drain region contacting the drain extension region and
abutting the buried insulator layer; a deep source region in the
semiconductor layer, the deep source region contacting the source
extension region and abutting the buried insulator layer, the deep
drain region and the deep source region being doped with a dopant
of the second conductivity type; a drain metal-semiconductor alloy
contact located on the upper portion of the deep drain region and
abutting the drain extension region; and a source
metal-semiconductor alloy contact abutting the source extension
region, wherein the deep source region is located below and
contacts a first portion of the source metal-semiconductor alloy
contact, and the deep source region is not located below and does
not contact a second portion of the source metal-semiconductor
alloy contact, such that the second portion of the source
metal-semiconductor alloy contact is an internal body contact that
directly contacts the semiconductor layer.
8. The integrated circuit of claim 7, wherein the source and drain
metal-semiconductor alloy contact comprise a metal silicide.
9. The integrated circuit of claim 7, wherein the semiconductor
layer comprises a shallow trench isolation region surrounding an
active area comprising silicon, and the source and drain extension
regions and the deep source and drain regions are all formed in the
active area.
10. The integrated circuit of claim 7, wherein the second portion
is located at one end of the source metal-semiconductor alloy
contact.
11. The integrated circuit of claim 7, wherein the deep source
region is not located below and does not contact a third portion of
the source metal-semiconductor alloy contact, such that the third
portion of the source metal-semiconductor alloy contact is an
internal body contact that directly contacts the semiconductor
layer, and the first portion separates the second portion from the
third portion.
12. The integrated circuit of claim 11, wherein the deep source
region is located below and contacts a fourth portion of the source
metal-semiconductor alloy contact, and the deep source region is
not located below and does not contact a fifth portion of the
source metal-semiconductor alloy contact, such that the fifth
portion of the source metal-semiconductor alloy contact is an
internal body contact that directly contacts the semiconductor
layer, and the fourth portion separates the first portion from the
fifth portion.
13. A method for fabricating a semiconductor device, the method
comprising: providing a semiconductor-on-insulator substrate
including a buried insulator layer; forming an semiconductor layer
overlying the semiconductor-on-insulator substrate, the
semiconductor layer being doped with a dopant of a first
conductivity type; forming a gate located on the semiconductor
layer, the gate including a gate dielectric layer located on the
semiconductor layer and a gate conductor layer located on the gate
dielectric layer; forming a source extension region and a drain
extension region in the semiconductor layer, the source extension
region and the drain extension region contacting the gate
dielectric layer, the source extension region and the drain
extension region being doped with a dopant of a second conductivity
type, which is opposite the first conductivity type; forming a deep
drain region in the semiconductor layer, the deep drain region
contacting the drain extension region and abutting the buried
insulator layer; forming a deep source region in the semiconductor
layer, the deep source region contacting the source extension
region and abutting the buried insulator layer, the deep drain
region and the deep source region being doped with a dopant of the
second conductivity type; forming a drain metal-semiconductor alloy
contact located on the upper portion of the deep drain region and
abutting the drain extension region; and forming a source
metal-semiconductor alloy contact abutting the source extension
region, wherein the deep source region is formed below and contacts
a first portion of the source metal-semiconductor alloy contact,
and the deep source region is formed such that it is not located
below and does not contact a second portion of the source
metal-semiconductor alloy contact, such that the second portion of
the source metal-semiconductor alloy contact is an internal body
contact that directly contacts the semiconductor layer.
14. The method of claim 13, wherein the source and drain
metal-semiconductor alloy contact comprise a metal silicide.
15. The method of claim 13, wherein the semiconductor layer
comprises a shallow trench isolation region surrounding an active
area comprising silicon, and the source and drain extension regions
and the deep source and drain regions are all formed in the active
area.
16. The method of claim 13, wherein the second portion is located
at one end of the source metal-semiconductor alloy contact.
17. The method of claim 13, wherein the deep source region is
formed such that it is not located below and does not contact a
third portion of the source metal-semiconductor alloy contact, such
that the third portion of the source metal-semiconductor alloy
contact is an internal body contact that directly contacts the
semiconductor layer, and the first portion separates the second
portion from the third portion.
18. The method of claim 17, wherein the deep source region is
located below and contacts a fourth portion of the source
metal-semiconductor alloy contact, and the deep source region is
not located below and does not contact a fifth portion of the
source metal-semiconductor alloy contact, such that the fifth
portion of the source metal-semiconductor alloy contact is an
internal body contact that directly contacts the semiconductor
layer, and the fourth portion separates the first portion from the
fifth portion.
Description
FIELD OF THE INVENTION
[0001] The present invention generally relates to the field of
semiconductors, and more particularly relates to metal oxide
semiconductor field effect transistors ("MOSFETs") with internal
body contacts.
BACKGROUND OF THE INVENTION
[0002] A conventional radio frequency ("RF") MOSFET produced on a
silicon-on-insulator ("SOI") substrate includes a body contact in
order to eliminate the floating body effect. While logic MOSFETs on
an SOI substrate can tolerate the floating body effect, RF MOSFETs
cannot do so, especially MOSFETs that are to be used for analog
applications. This is because such RF MOSFETs need to be modeled
very accurately, and the floating body effect is difficult to model
because it is not a steady-state effect. Furthermore, the floating
body effect often induces a kink in the drain current versus
drain-source voltage (Id-Vds) characteristic. This degrades the
linearity as well as the power gain of the transistor. Therefore, a
body contact is provided for an RF MOSFET on an SOI substrate in
order to give the transistor a body-tied configuration. The
external contact to the body ensures a stable body potential.
However, this external body contact requires extra area, and more
specifically increases the perimeter of the drain-to-body junction.
This increases the capacitance and reducing the achievable cut-off
frequency (fT) and maximum frequency (fmax).
SUMMARY OF THE INVENTION
[0003] A semiconductor device is disclosed. The semiconductor
device includes a semiconductor-on-insulator substrate including a
buried insulator layer and an overlying semiconductor layer. The
semiconductor layer is doped with a dopant of a first conductivity
type. A gate is located on the semiconductor layer and includes a
gate dielectric layer located on the semiconductor layer and a gate
conductor layer located on the gate dielectric layer. A source
extension region and a drain extension region are formed in the
semiconductor layer. The source extension region and the drain
extension region contact the gate dielectric layer. The source
extension region and the drain extension region are doped with a
dopant of a second conductivity type. A deep drain region is formed
in the semiconductor layer. The deep drain region contacts the
drain extension region and abuts the buried insulator layer. A deep
source region is formed in the semiconductor layer. The deep source
region contacts the source extension region and abuts the buried
insulator layer. The deep drain region and the deep source region
are doped with a dopant of the second conductivity type. A drain
metal-semiconductor alloy contact is located on the upper portion
of the deep drain region and abutting the drain extension region. A
source metal-semiconductor alloy contact abuts the source extension
region. The deep source region is located below and contacts a
first portion of the source metal-semiconductor alloy contact. The
deep source region is not located below and does not contact a
second portion of the source metal-semiconductor alloy contact,
such that the second portion of the source metal-semiconductor
alloy contact is an internal body contact that directly contacts
the semiconductor layer.
[0004] In another embodiment, an integrated circuit is disclosed.
The integrated circuit includes a circuit supporting substrate
including a semiconductor device. The semiconductor device
comprises a semiconductor-on-insulator substrate including a buried
insulator layer and an overlying semiconductor layer. The
semiconductor layer is doped with a dopant of a first conductivity
type. A gate is located on the semiconductor layer and includes a
gate dielectric layer located on the semiconductor layer and a gate
conductor layer located on the gate dielectric layer. A source
extension region and a drain extension region are formed in the
semiconductor layer. The source extension region and the drain
extension region contact the gate dielectric layer. The source
extension region and the drain extension region are doped with a
dopant of a second conductivity type. A deep drain region is formed
in the semiconductor layer. The deep drain region contacts the
drain extension region and abuts the buried insulator layer. A deep
source region is formed in the semiconductor layer. The deep source
region contacts the source extension region and abuts the buried
insulator layer. The deep drain region and the deep source region
are doped with a dopant of the second conductivity type. A drain
metal-semiconductor alloy contact is located on the upper portion
of the deep drain region and abutting the drain extension region. A
source metal-semiconductor alloy contact abuts the source extension
region. The deep source region is located below and contacts a
first portion of the source metal-semiconductor alloy contact. The
deep source region is not located below and does not contact a
second portion of the source metal-semiconductor alloy contact,
such that the second portion of the source metal-semiconductor
alloy contact is an internal body contact that directly contacts
the semiconductor layer.
[0005] In yet another embodiment, a method for fabricating a
semiconductor device is disclosed. The method includes forming a
semiconductor-on-insulator substrate including a buried insulator
layer. A semiconductor layer is formed over the
semiconductor-on-insulator substrate. The semiconductor layer is
doped with a dopant of a first conductivity type. A gate is formed
on the semiconductor layer and includes a gate dielectric layer
located on the semiconductor layer and a gate conductor layer
located on the gate dielectric layer. A source extension region and
a drain extension region are formed in the semiconductor layer. The
source extension region and the drain extension region contact the
gate dielectric layer. The source extension region and the drain
extension region are doped with a dopant of a second conductivity
type. A deep drain region is formed in the semiconductor layer. The
deep drain region contacts the drain extension region and abuts the
buried insulator layer. A deep source region is formed in the
semiconductor layer. The deep source region contacts the source
extension region and abuts the buried insulator layer. The deep
drain region and the deep source region are doped with a dopant of
the second conductivity type. A drain metal-semiconductor alloy
contact is located on the upper portion of the deep drain region
and abutting the drain extension region. A source
metal-semiconductor alloy contact abuts the source extension
region. The deep source region is located below and contacts a
first portion of the source metal-semiconductor alloy contact. The
deep source region is not located below and does not contact a
second portion of the source metal-semiconductor alloy contact,
such that the second portion of the source metal-semiconductor
alloy contact is an internal body contact that directly contacts
the semiconductor layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIGS. 1-4 are cross-sectional views showing fabrication of a
MOSFET on an SOI substrate according to one embodiment of the
present invention;
[0007] FIG. 5 illustrates masks for deep source-drain implants
according to one embodiment of the present invention;
[0008] FIG. 6 illustrates conventional masks for deep source-drain
implants;
[0009] FIG. 7 shows a top-down view of a MOSFET on an SOI substrate
according to one embodiment of the present invention;
[0010] FIG. 8 shows a cross-sectional view of the MOSFET of FIG. 7
taken along line A; and
[0011] FIG. 9 shows a cross-sectional view of the MOSFET of FIG. 7
taken along line A'.
DETAILED DESCRIPTION
[0012] Preferred embodiments of the present invention will be
described in detail hereinbelow with reference to the attached
drawings.
[0013] Embodiments of the present invention utilize an internal
body contact that does not require extra area to improve the
performance of a metal oxide semiconductor field effect transistor
("MOSFET") on a silicon-on-insulator ("SOI") substrate. This MOSFET
overcomes the problems discussed above because a body contact is
provided without increasing the junction area of the transistor,
and without increasing the capacitance of the MOSFET. Thus, the
MOSFET can achieve higher speeds, while still suppressing the
floating body effect for good linearity.
[0014] More specifically, compared to a conventional MOSFET on an
SOI substrate with a body contact, the MOSFET of the present
invention eliminates the capacitance penalty for providing the body
contact, so as to increase speed. Further, the area of the MOSFET
of the present invention is reduced compared to the conventional
body-contacted MOSFET. Compared to a conventional floating-body
MOSFET on an SOI substrate, the MOSFET of the present invention
exhibits improved linearity and lower output conductance, which
improves power gain. Additionally, the MOSFET of the present
invention can be fabricated without any more mask layers than a
conventional floating-body MOSFET. The internal body contact of the
MOSFET of the present invention can be made solely through design
changes to the conventional process flow, without the need for any
additional processing steps (such as angled implants or alternate
amorphization species).
[0015] FIGS. 1-4 show fabrication of a MOSFET on an SOI substrate
according to one embodiment of the present invention. As shown in
FIG. 1, an SOI substrate 8 is provided. The SOI substrate 8 is
formed by a handle substrate 10 (e.g., a silicon substrate), an
overlying buried insulator layer 12 (e.g., an oxide layer), and an
overlying semiconductor layer 30. Shallow trench isolation regions
20 of a dielectric material are formed in the semiconductor layer
30. The shallow trench isolation region 20 abuts the buried
insulator layer 12 and laterally surrounds an active region 31 in
the semiconductor layer 30, so as to electrically isolate the
active region 31 from other portions of the semiconductor layer 30
(e.g., other active regions).
[0016] In exemplary embodiments, the active region 31 comprises a
single crystalline semiconductor material, such as silicon,
germanium, a silicon-germanium alloy, a silicon-carbon alloy, a
silicon-germanium-carbon alloy, gallium arsenide, indium arsenide,
indium phosphide, a III-V compound semiconductor material, a II-VI
compound semiconductor material, or an organic semiconductor
material. In this exemplary embodiment, the semiconductor material
comprises silicon. The active region 31 of this embodiment is doped
with a dopant of a first conductivity type, such as a p-type dopant
(e.g., boron, gallium, or indium) or an n-type dopant (e.g.,
phosphorus, arsenic, or antimony). The concentration of the dopant
is from about 1.0.times.10.sup.15 atoms/cm.sup.3 to about
1.0.times.10.sup.19 atoms/cm.sup.3. Non-electrical
stress-generating dopants, such as germanium and carbon may also be
present. The active region 31 may also have a built-in biaxial
stress in the plane of the active region 31 (i.e., in the plane
perpendicular to the direction of the top surface 19 of the active
region 31.
[0017] As shown in FIG. 2, a gate dielectric 50 and a gate
conductor 52 are formed on the active region 31. More specifically,
a stack of a gate dielectric layer and a gate conductor layer are
formed on the active region 31. This stack is then lithographically
patterned and etched to form the gate dielectric 50 and the
overlying gate conductor 52 in a portion of the active region 31 of
the semiconductor layer 30.
[0018] The gate dielectric 50 of this embodiment comprises a
conventional dielectric material (such as silicon oxide, silicon
nitride, silicon oxynitride, or a stack thereof) that is formed by
thermal conversion of a top portion of the active region 31 and/or
by chemical vapor deposition ("CVD"). In alternative embodiments,
the gate dielectric 50 comprises a high-k dielectric material (such
as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide,
titanium dioxide, strontium titanate, lanthanum aluminate, yttrium
oxide, an alloy thereof, or a silicate thererof) that is formed in
a known manner (such as by CVD, atomic layer deposition ("ALD"),
molecular beam epitaxy ("MBE"), pulsed laser deposition ("PLD"),
liquid source misted chemical deposition ("LSMCD"), or physical
vapor deposition ("PVD")). The thickness of the gate dielectric
layer is from about 1 nm to about 3 nm in exemplary embodiment
having a conventional dielectric material, and from about 2 nm to
about 6 nm in exemplary embodiment having a high-k dielectric
material, and may have an effective oxide thickness on the order of
or less than 1 nm.
[0019] The gate conductor 52 comprises a semiconductor (e.g.,
polysilicon) gate layer and/or a metal gate layer. In one
embodiment in which of the gate dielectric 50 comprises a
conventional dielectric material, the gate conductor 52 is a
semiconductor gate layer and has a thickness from about 40 nm to
about 200 nm. In one embodiment in which the gate dielectric
comprises a high-k dielectric material, the gate conductor 52 is a
metal gate layer abutting the gate dielectric 50 and comprising a
conductive refractory metal nitride (such as TaN, TiN, WN, TiAlN,
TaCN, or an alloy thereof). The thickness of the metal gate layer
in this embodiment is from about 2 nm to about 100 nm, and
preferably from about 7 nm to about 50 nm. In another embodiment,
the gate conductor 52 comprises a stack of a metal gate layer and a
semiconductor gate layer.
[0020] The length L of the gate conductor 52 of this embodiment is
determined by lithographic means, and is a lithographic minimum
length (or a "critical dimension"). In some embodiments, a trimming
etch is employed to reduce the length L of the gate conductor 52 to
a length that is less than the lithographic minimum length.
[0021] As shown in FIG. 3, a first gate spacer layer 53 comprising
a dielectric material (such as silicon oxide) is then formed on the
gate conductor 52 and on the semiconductor layer 30. Alternatively,
a reactive-ion etch process can be used to remove the dielectric
material on top of the gate and on the semiconductor layer so as to
form a gate spacer only on the sidewall of the gate conductor 52.
Ion implantations are performed into the semiconductor layer 30
employing the gate conductor 52 as an implantation mask in order to
form a source extension region 134A and a drain extension region
134B that are self-aligned to the gate conductor 52. The source
extension region 134A and the drain extension region 134B are
formed in the semiconductor layer 30 at the same time. This ion
implantation to form the extension regions can be performed before
or after the formation of the first gate spacer layer 53, or
alternatively formation of the first gate spacer layer 53 can be
omitted. If the ion implantation follows formation of the first
gate spacer layer 53, the vertical portions of the first gate
spacer layer 53 on the sidewalls of the gate conductor 52 also
serve as an implantation mask. In complementary MOSFET (CMOS)
technologies which have both n-type MOSFETs and p-type MOSFETs,
block masks are used to define where extension implants occur. In
particular, one mask is used to open n-type MOSFET regions and
block p-type MOSFET regions for ion implantation of n-type dopants
in order to form source and drain extension regions in the n type
MOSFETs. Another mask, complementary to the first mask, is used to
open the p-type MOSFET regions and block n-type MOSFET regions for
ion implantation of p-type dopants in order to form source and
drain extension regions in the p-type-MOSFETs.
[0022] The portion of the active region that is not implanted with
dopant ions during the ion implantation constitutes the body 32 of
the MOSFET and has first conductivity type doping. The source
extension region 134A and the drain extension region 134B has a
first depth d1 (e.g., from about 5 nm to about 50 nm), and outer
edges of these extension regions extend under the gate dielectric
50. Thus, the source extension region 134A and the drain extension
region 134B both abut the gate dielectric 50 and have a second
conductivity type doping, which is the opposite the first
conductivity type doping. The source extension region 134A and the
drain extension region 134B of this exemplary embodiment have a
doping concentration from about 1.0.times.10.sup.19 atoms/cm.sup.3
to about 1.0.times.10.sup.21 atoms/cm.sup.3. In some embodiments,
another ion implantation done at a tilted angle is then performed
to form halo regions under the source and drain extension
regions.
[0023] As shown in FIG. 4, a second gate spacer layer is deposited
on the first gate spacer layer 53, and then these two layers are
etched (e.g., using reactive ion etching) to form a gate spacer 55.
This gate spacer 55 comprises the combination of the first gate
spacer layer portion 54 and the second gate spacer layer portion
56. In exemplary embodiments, the second gate spacer layer portion
56 comprises a dielectric material that is the same as or different
than the dielectric material of the first gate spacer layer portion
54. For example, in this embodiment the first gate spacer layer
portion 54 comprises silicon oxide and the second gate spacer layer
portion 56 comprises silicon nitride. The dielectric materials for
the first and second gate spacer layer portions may include low-k
dielectric materials. The portion of the first gate spacer layer 53
outside the outer sidewalls of the second gate spacer layer portion
56 is removed during the reactive ion etching.
[0024] Thus, the gate spacer 55 laterally abuts the sidewalls of
the gate conductor 52 and the gate dielectric 50, and abuts the
source extension region 134A and the drain extension region 134B.
In this embodiment, the thickness of the gate spacer 55, as
measured laterally at the base of the gate spacer 55 from the
sidewall of the gate conductor 52 abutting the spacer 55 to an
outer edge of the gate spacer 55 adjoining either the source
extension region 134A or the drain extension region 134B, is from
about 10 nm to about 100 nm, and preferably from about 20 nm to
about 80 nm. In alternative embodiments, the gate spacer 55 is
formed by only one or more than two gate spacer layers.
[0025] Next, deep source-drain implants are performed. More
specifically, a mask is first formed to define where the deep
source-drain implants will occur. FIG. 5 shows masks for deep
source-drain implants according to one embodiment of the present
invention. These masks include a first mask 502 for defining the
deep source-drain implants of a p-type MOSFET and a second mask 504
defining the deep source-drain implants of an n-type MOSFET. The
mask layout in FIG. 5 is used for making an n-type MOSFET (NFET)
and a p-type-MOSFET (PFET). This is done for illustration purposes
only and is not meant to limit the present invention. In practice,
designs typically include multiple incidences of NFETs and PFETs,
and can have any layout style.
[0026] The first mask 502 for a p-type MOSFET has a blocking region
506 where the deep source-drain implants are blocked and an open
region 508 where the deep source-drain implants occur. Because the
first mask 502 is for forming p-type MOSFETs, this mask blocks all
of the area over the n-type device NFET along with the area over
the p-type device PFET that is not to be implanted. Additionally,
the blocking region 506 includes two extensions 510 and 512 that
extend into the open region 508. While in this embodiment the
additional block regions 510 and 512 are linked to the bigger
blocking region 506, this is not the case in all embodiments. For
example, in an alternative embodiment, the additional block regions
510 and 512 are `islands` inside the open region 508.
[0027] The second mask 504 for an n-type MOSFET has a blocking
region 518 where the deep source-drain implants are blocked and an
open region 520 where the deep source-drain implants occur. Because
the second mask 504 is for forming n-type MOSFETs, this mask blocks
all of the area over the p-type device PFET. Additionally, the
blocking region 518 includes two additional areas 514 and 516 in
the open region 520 over the n-type device NFET.
[0028] The blocking regions 506 and 518 block the ions being
implanted during the deep source-drain implants, while the open
regions 508 and 520 allow the ions to pass through for deep
source-drain implantation. In this embodiment of the present
invention, the two extensions 510 and 512 of the blocking region
506 of the first mask 502 and the two additional areas 514 and 516
of the blocking region 518 of the second mask 504 are added to the
design of these masks. This can be seen in a comparison with the
conventional masks for deep source-drain implants shown in FIG.
6.
[0029] The first conventional mask 602 for a p-type MOSFET has a
blocking region 606 where the deep source-drain implants are
blocked, and an open region 608 where the deep source-drain
implants occur. Because this mask is for forming p-type MOSFETs,
all of the area over the n-type device NFET is blocked while a
substantially square or rectangular area over the p-type device
PFET is open so that it will be implanted. Similarly, the second
conventional mask 604 for an n-type MOSFET has a blocking region
610 where the deep source-drain implants are blocked, and an open
region 612 where the deep source-drain implants occur. Because this
mask is for forming n-type MOSFETs, a substantially square or
rectangular area over the p-type device PFET is blocked while all
of the area over the n-type device NFET is open.
[0030] In the exemplary embodiment, the two extensions 510 and 512
of the blocking region 506 of the first mask 502 and the two
additional areas 514 and 516 of the blocking region 518 of the
second mask 504 are made to block the deep source-drain implant in
a portion of the source region of the MOSFET. After the deep
source-drain implantation has been performed, the mask is removed
in a conventional manner and a subsequent rapid thermal anneal
("RTA") is performed (alternatively, millisecond laser anneal or
flash anneal can be used) to provide relatively deep diffusions for
the deep source and drain regions.
[0031] As shown in FIGS. 8 and 9, the deep-source drain implants
form a deep source region 806 and a deep drain region 808. Next, a
source silicide contact 802 and a drain silicide contact 804 are
formed by metallization of exposed semiconductor material. In
particular, in this embodiment, a metal layer is deposited directly
on the semiconductor layer 30 (such as by a blanket deposition).
The metal layer comprises a metal capable of forming a
metal-semiconductor alloy with the semiconductor material of the
semiconductor layer 30 (such as tungsten, tantalum, titanium,
cobalt, nickel, platinum, osmium, or an alloy thereof). A preferred
thickness of the metal layer ranges from about 5 nm to about 50 nm,
and more preferably from about 10 nm to about 25 nm. In some
embodiments, a metal nitride capping layer (e.g., containing a
refractory metal nitride such as TaN, TiN, or OsN) is deposited
over the metal layer.
[0032] An anneal is then performed so that the metal layer reacts
with the semiconductor material of the semiconductor layer 30 to
form the source silicide contact 802 directly over the deep source
region 806 and the drain silicide contact 804 directly over the
deep drain region 808.
[0033] The resulting structure is shown in FIGS. 7-9. FIG. 7 shows
a top-down view with two source regions S and two drain regions D
separated by gate conductors G, FIG. 8 shows a cross-sectional view
taken along line A of FIG. 7, and FIG. 9 shows a cross-sectional
view taken along line A' of FIG. 7. As shown in FIGS. 7 and 8, in
one portion of the MOSFET the deep-source drain implants are not
blocked in the source and drain regions. Thus, in this portion of
the device the deep source region 806 underlies the source contact
802 and the deep drain region 808 underlies the drain contact 804.
Further, the deep source region 806 contacts the source extension
134A and the deep drain region 808 contacts the drain extension
134B.
[0034] On the other hand, as shown in FIGS. 7 and 9, in another
portion of the MOSFET the deep-source drain implants are not
blocked in the drain region but are blocked in the source region.
The implants are blocked in this portion of the source region by
the extensions or additional areas of the blocking region of the
masks used for deep source-drain implants. Thus, in this portion of
the device the deep drain region 908 underlies the drain contact
904 but there is no deep source region underlying the source
contact 902. Instead, the source contact 902 directly overlays the
body 32 in this portion of the device. The deep drain region 908
contacts the drain extension 134B while the source contact 902
contacts the source extension 134A.
[0035] Thus, the deep source-drain implant is blocked at the ends
of the source regions, so that at the ends of these regions (as
shown by hatching in FIG. 7) there is no deep source region and the
silicide of the source contact directly contacts the body. In the
remainder of the source regions, the deep source regions underlie
the source contact. Further, in all of each drain region, the deep
drain region underlies the drain contact.
[0036] This structure provides an internal body contact at the ends
of the source regions as shown in FIG. 9, while leaving the
remainder of the source regions unchanged as shown in FIG. 8.
Because the internal body contact also contacts the source
extension region, body contact is made without a capacitance
penalty compared to a floating body device. At the same time, there
is only a small impact on the source resistance because the deep
source implant underlies most of the source contact. Additionally,
because the shallow source extension still directly connects the
silicide contact to the area under the gate in the area where there
is the internal body contact (i.e., where the silicide contact
directly contacts the body), there is no loss of electrical device
width in the body contact area. Thus, there is still current
conduction in this area, so there is no loss of drive current due
to the body contact.
[0037] The present invention is not limited to having the internal
body contact located at only the far end of each source region. For
example, in another embodiment there is additionally an internal
body contact area at the other end of each source region, as shown
by areas 702 in FIG. 7. Thus, in this embodiment a region at each
end of each source region has an internal body contact. In another
embodiment, this is further extended so that the deep source-drain
implant is blocked in multiple regions of each source region to
produce more body contacts. In yet another embodiment, the deep
source-drain implant is blocked in a larger area at the end of each
source region to produce a larger body contacts. In other
embodiments, one or multiple such internal body contacts are
provided at any location along each source region. As the area of
the source region area that is used for internal body contact is
increased, the control of the body potential is improved at the
expense of increased source resistance. Preferably, only the area
needed to maintain good control of the body potential is used for
internal body contact.
[0038] After the contact areas are formed, the device is completed
in a conventional manner and electrically connections are made
between the contact areas and other devices so as to form an
integrated circuit.
[0039] Accordingly, embodiments of the present invention provide a
MOSFET on an SOI substrate with an internal body-tied
configuration. The internal body contact allows the junction area
and capacitance of the MOSFET to remain the same, while suppressing
the floating body effect for better linearity. Thus, the
capacitance penalty for providing a body contact is eliminated,
which increases the speed. At the same time, the area of MOSFET is
reduced compared to conventional body-contacted devices. Further,
the MOSFET can be fabricated without any more mask layers than a
conventional floating-body MOSFET. The internal body contact of the
MOSFET is made solely through design changes to the conventional
process flow, without the need for any additional processing
steps.
[0040] The MOSFET of the present invention is particularly suited
for use as an RF MOSFET. While the resulting MOSFET is asymmetric
(i.e., the source and drain are not reversible), this is usually of
no consequence for RF circuits, because the source and drain
contacts rarely, if ever, need to have their polarity reversed in
such circuits.
[0041] It should be noted that some of the features of the examples
of the present invention may be used to advantage without the
corresponding use of other features. As such, the foregoing
description should be considered as merely illustrative of the
principles, teachings, examples and exemplary embodiments of the
present invention, and not in limitation thereof.
[0042] It should be understood that these embodiments are only
examples of the many advantageous uses of the innovative teachings
herein. In general, statements made in the specification of the
present application do not necessarily limit any of the various
claimed inventions. Moreover, some statements may apply to some
inventive features but not to others. In general, unless otherwise
indicated, singular elements may be in the plural and vice versa
with no loss of generality.
[0043] The circuit as described above is part of the design for an
integrated circuit chip. The chip design is created in a graphical
computer programming language, and stored in a computer storage
medium (such as a disk, tape, physical hard drive, or virtual hard
drive such as in a storage access network). If the designer does
not fabricate chips or the photolithographic masks used to
fabricate chips, the designer transmits the resulting design by
physical means (e.g., by providing a copy of the storage medium
storing the design) or electronically (e.g., through the Internet)
to such entities, directly or indirectly. The stored design is then
converted into the appropriate format (e.g., GDSII) for the
fabrication of photolithographic masks, which typically include
multiple copies of the chip design in question that are to be
formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0044] The method as described above is used in the fabrication of
integrated circuit chips.
[0045] The resulting integrated circuit chips can be distributed by
the fabricator in raw wafer form (that is, as a single wafer that
has multiple unpackaged chips), as a bare chip, or in a packaged
form. In the latter case, the chip is mounted in a single chip
package (such as a plastic carrier, with leads that are affixed to
a motherboard or other higher level carrier) or in a multichip
package (such as a ceramic carrier that has either or both surface
interconnections or buried interconnections). In any case, the chip
is then integrated with other chips, discrete circuit elements,
and/or other signal processing devices as part of either (a) an
intermediate product, such as a motherboard, or (b) an end product.
The end product can be any product that includes integrated circuit
chips, ranging from toys and other low-end applications to advanced
computer products having a display, a keyboard, or other input
device, and a central processor.
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