U.S. patent application number 12/456398 was filed with the patent office on 2010-11-04 for bifacial solar cells with back surface reflector.
This patent application is currently assigned to Calisolar, Inc.. Invention is credited to Alain Blosse, Peter Borden, Martin Kaes, Fritz G. Kirscht, Andreas Kraenzl, Kamel Ounadjela.
Application Number | 20100275995 12/456398 |
Document ID | / |
Family ID | 43029508 |
Filed Date | 2010-11-04 |
United States Patent
Application |
20100275995 |
Kind Code |
A1 |
Kaes; Martin ; et
al. |
November 4, 2010 |
Bifacial solar cells with back surface reflector
Abstract
A simplified manufacturing process and the resultant bifacial
solar cell (BSC) are provided, the simplified manufacturing process
reducing manufacturing costs. The BSC includes a back surface
contact grid and an overlaid blanket metal reflector. A doped
amorphous silicon layer is interposed between the contact grid and
the blanket layer.
Inventors: |
Kaes; Martin; (Berlin,
DE) ; Borden; Peter; (San Mateo, CA) ;
Ounadjela; Kamel; (Belmont, CA) ; Kraenzl;
Andreas; (Radolfzell, DE) ; Blosse; Alain;
(Belmont, CA) ; Kirscht; Fritz G.; (Berlin,
DE) |
Correspondence
Address: |
PATENT LAW OFFICE OF DAVID G. BECK
P. O. BOX 1146
MILL VALLEY
CA
94942
US
|
Assignee: |
Calisolar, Inc.
Sunnyvale
CA
|
Family ID: |
43029508 |
Appl. No.: |
12/456398 |
Filed: |
June 15, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61215199 |
May 1, 2009 |
|
|
|
Current U.S.
Class: |
136/258 ;
257/E21.135; 257/E21.506; 438/72; 438/98 |
Current CPC
Class: |
H01L 31/068 20130101;
Y02P 70/521 20151101; Y02P 70/50 20151101; H01L 31/1804 20130101;
H01L 31/18 20130101; Y02E 10/547 20130101; H01L 31/022425 20130101;
H01L 31/0684 20130101 |
Class at
Publication: |
136/258 ; 438/72;
438/98; 257/E21.135; 257/E21.506 |
International
Class: |
H01L 31/028 20060101
H01L031/028; H01L 21/22 20060101 H01L021/22; H01L 21/60 20060101
H01L021/60 |
Claims
1. A method of fabricating a bifacial solar cell (BSC), the method
comprising the steps of: depositing a dopant of a first
conductivity type onto a back surface of a silicon substrate of
said first conductivity type to form a back surface doped region;
depositing a back surface dielectric over said back surface doped
region; forming an active area of a second conductivity type on a
front surface of said silicon substrate, said forming step
including a thermal diffusing step, wherein said method includes a
single thermal diffusing step; etching said active area; depositing
a front surface passivation and anti-reflection (AR) dielectric
layer onto said active area; applying a back surface contact grid;
applying a front surface contact grid; firing said back surface
contact grid; firing said front surface contact grid; depositing a
layer of amorphous silicon onto said back surface contact grid and
said back surface dielectric, wherein said layer of amorphous
silicon is doped with a second dopant of said first conductivity
type; depositing a layer of metal over said layer of amorphous
silicon; and isolating said active area.
2. The method of claim 1, wherein said step of applying said back
surface contact grid further comprises the step of screen printing
said back surface contact grid, and wherein said step of applying
said front surface contact grid further comprises the step of
screen printing said front surface contact grid.
3. The method of claim 1, further comprising the step of depositing
a conductive interface layer between said layer of amorphous
silicon and said layer of metal, wherein said conductive interface
layer depositing step is performed prior to said metal layer
depositing step.
4. A method of fabricating a bifacial solar cell, the method
comprising the steps of: depositing a boron doped layer on a back
surface of a p-type silicon substrate; depositing a back surface
dielectric onto said boron doped layer; diffusing phosphorous onto
a front surface of said silicon substrate to form an n.sup.+ layer
and a front surface junction; removing a phosphor-silicate glass
(PSG) formed during said phosphorous diffusing step; depositing a
front surface passivation and anti-reflection (AR) dielectric layer
onto said n.sup.+ layer; applying a back surface contact grid;
applying a front surface contact grid; firing said back surface
contact grid; firing said front surface contact grid; depositing a
boron doped layer of amorphous silicon onto said back surface
contact grid and said back surface dielectric; depositing a metal
layer onto said boron doped layer of amorphous silicon; and
isolating said front surface junction.
5. The method of claim 4, wherein said step of applying said back
surface contact grid further comprises the step of screen printing
said back surface contact grid, and wherein said step of applying
said front surface contact grid further comprises the step of
screen printing said front surface contact grid.
6. The method of claim 4, wherein said step of isolating said front
surface junction is performed using a laser scriber.
7. The method of claim 4, further comprising the step of depositing
a conductive interface layer between said boron doped layer of
amorphous silicon and said layer of metal, wherein said conductive
interface layer depositing step is performed prior to said metal
layer depositing step.
8. The method of claim 7, wherein said conductive interface layer
is comprised of a material selected from the group consisting of
indium tin oxide and aluminum-doped zinc oxide.
9. The method of claim 4, wherein said steps of firing said back
and front surface contact grids are performed simultaneously.
10. The method of claim 4, wherein said step of firing said back
surface contact grid is performed prior to said step of applying
said front surface contact grid.
11. The method of claim 4, wherein said boron doped layer
depositing step further comprises the step of depositing a boron
doped silicon dioxide layer using chemical vapor deposition.
12. The method of claim 4, wherein said boron doped layer
depositing step further comprises the step of depositing a boron
doped silicon layer using chemical vapor deposition.
13. The method of claim 4, wherein said boron doped layer
depositing step further comprises the step of depositing a boron
doped amorphous silicon layer using plasma enhanced chemical vapor
deposition.
14. The method of claim 4, wherein said boron doped layer
depositing step further comprises the step of spraying a boric acid
solution onto said back surface of said silicon substrate.
15. The method of claim 4, wherein said boron doped layer
depositing step further comprises the step of spraying a boron
doped spin-on glass onto said back surface of said silicon
substrate.
16. The method of claim 4, wherein said PSG removing step further
comprises the step of etching said front surface with a
hydrofluoric etch.
17. The method of claim 4, further comprising the step of selecting
said back surface dielectric and said front surface passivation and
AR dielectric from the group consisting of silicon nitrides,
silicon dioxides and silicon oxynitrides.
18. The method of claim 4, wherein said phosphorous diffusing step
is performed at a temperature of approximately 850.degree. C. for a
duration of approximately 10 to 20 minutes.
19. The method of claim 4, wherein said back surface dielectric
depositing step is performed after said step of applying said back
surface contact grid.
20. A bifacial solar cell, comprising: a silicon substrate of a
first conductivity type with a front surface and a back surface; a
doped region of said first conductivity type located on said back
surface of said silicon substrate; a dielectric layer deposited on
said doped region; an active region of a second conductivity type
located on said front surface of said silicon substrate; a
passivation and AR dielectric layer deposited on said active
region; a first contact grid applied to said dielectric layer, said
first contact grid comprised of a first metal, wherein after a
firing step said first contact grid is alloyed through said
dielectric layer to said doped region located on said back surface
of said silicon substrate; a second contact grid applied to said
passivation and AR dielectric layer, said second contact grid
comprised of a second metal, wherein after said firing step said
second contact grid is alloyed through said passivation and AR
dielectric layer to said active region; a amorphous silicon layer
doped with a dopant of said first conductivity type, said amorphous
silicon layer deposited on said first contact grid and said
dielectric layer; and a blanket layer deposited on said amorphous
silicon layer, said blanket layer comprised of a third metal.
21. The bifacial solar cell of claim 20, further comprising a
groove on said front surface of said silicon substrate, said groove
isolating a front junction formed by said active region and said
silicon substrate.
22. The bifacial solar cell of claim 20, further comprising a
conductive interface layer interposed between said amorphous
silicon layer and said blanket layer.
23. The bifacial solar cell of claim 22, wherein said conductive
interface layer is selected from the group of materials consisting
of indium tin oxide and aluminum doped zinc oxide.
24. The bifacial solar cell of claim 20, wherein said silicon
substrate is comprised of a p-type silicon, said active region is
comprised of n.sup.+ material resulting from a phosphorous
diffusion step, and said doped region and said amorphous silicon
layer further comprise a boron dopant.
25. The bifacial solar cell of claim 24, wherein said dielectric
layer and wherein said passivation and AR dielectric layer are each
comprised of a material selected from the group consisting of
silicon nitrides, silicon dioxides and silicon oxynitrides.
26. The bifacial solar cell of claim 20, wherein said silicon
substrate is comprised of an n-type silicon, said active region is
comprised of p.sup.+ material resulting from a boron diffusion
step, and said doped region and said amorphous silicon layer
further comprise a phosphorous dopant.
27. A method of fabricating a bifacial solar cell (BSC), the method
comprising the steps of: forming an active area of a second
conductivity type on a front surface of a silicon substrate of a
first conductivity type, said forming step including a thermal
diffusing step; etching said front surface of said silicon
substrate; depositing a front surface passivation and
anti-reflection (AR) dielectric layer onto said active area and a
back surface dielectric layer onto said back surface of said
silicon substrate; applying a back surface contact grid; applying a
front surface contact grid; firing said back surface contact grid;
firing said front surface contact grid; depositing a layer of
amorphous silicon onto said back surface contact grid and said back
surface dielectric layer, wherein said layer of amorphous silicon
is doped with a dopant of said first conductivity type; and
depositing a layer of metal over said layer of amorphous
silicon.
28. The method of claim 27, wherein said step of applying said back
surface contact grid further comprises the step of screen printing
said back surface contact grid, and wherein said step of applying
said front surface contact grid further comprises the step of
screen printing said front surface contact grid.
29. The method of claim 27, further comprising the step of
depositing a conductive interface layer between said layer of
amorphous silicon and said layer of metal, wherein said conductive
interface layer depositing step is performed prior to said metal
layer depositing step.
30. The method of claim 27, further comprising the step of removing
a back surface junction formed on a back surface of said silicon
substrate during said active area forming step.
31. A method of fabricating a bifacial solar cell, the method
comprising the steps of: diffusing phosphorous onto a front surface
of a silicon substrate to form an n.sup.+ layer and a front surface
junction and onto a back surface of said silicon to form a back
surface junction; removing a phosphor-silicate glass (PSG) formed
during said phosphorous diffusing step; depositing a front surface
passivation and anti-reflection (AR) dielectric layer onto said
n.sup.+ layer and a back surface dielectric layer onto said back
surface of said silicon substrate; applying a back surface contact
grid; applying a front surface contact grid; firing said back
surface contact grid; firing said front surface contact grid; and
depositing a metal layer onto said back surface contact grid and
said back surface dielectric.
32. The method of claim 31, wherein said step of applying said back
surface contact grid further comprises the step of screen printing
said back surface contact grid, and wherein said step of applying
said front surface contact grid further comprises the step of
screen printing said front surface contact grid.
33. The method of claim 31, wherein said steps of firing said back
and front surface contact grids are performed simultaneously.
34. The method of claim 31, wherein said step of firing said back
surface contact grid is performed prior to said step of applying
said front surface contact grid.
35. The method of claim 31, further comprising the steps of
removing said back surface junction and isolating said front
surface junction.
36. The method of claim 35, wherein said back surface junction
removing step further comprises the step of etching said back
surface.
37. The method of claim 35, wherein said step of applying said back
surface contact grid is performed after said back surface junction
removing step and before said back surface dielectric layer
depositing step.
38. The method of claim 35, further comprising the step of applying
a back surface metal grid onto said back surface of said silicon
substrate, wherein said back surface metal grid applying step is
performed after said back surface junction removing step and before
said back surface dielectric layer depositing step, and wherein the
method of claim 31 further comprises the step of aligning said back
surface contact grid with said back surface metal grid.
39. The method of claim 38, wherein said back surface metal grid
applying step further comprises the steps of applying a shadow mask
to said back surface of said silicon substrate and depositing said
back surface metal grid onto said back surface of said silicon
substrate.
40. The method of claim 38, wherein said back surface metal grid
applying step further comprises the step of screen printing said
back surface metal grid onto said back surface of said silicon
substrate.
41. The method of claim 38, wherein said step of firing said back
surface contact grid is performed prior to said step of applying
said front surface contact grid.
42. The method of claim 31, wherein said PSG removing step further
comprises the step of etching said front surface with a
hydrofluoric etch.
43. A method of fabricating a bifacial solar cell (BSC), the method
comprising the steps of: depositing a back surface dielectric layer
onto a back surface of a silicon substrate of a first conductivity
type; forming an active area of a second conductivity type on a
front surface of said silicon substrate, said forming step
including a thermal diffusing step; etching said front surface of
said silicon substrate; depositing a front surface passivation and
anti-reflection (AR) dielectric layer onto said active area;
applying a back surface contact grid; applying a front surface
contact grid; firing said back surface contact grid; firing said
front surface contact grid; depositing a layer of amorphous silicon
onto said back surface contact grid and said back surface
dielectric layer, wherein said layer of amorphous silicon is doped
with a dopant of said first conductivity type; and depositing a
layer of metal over said layer of amorphous silicon; and isolating
said front surface junction.
44. The method of claim 43, wherein said step of applying said back
surface contact grid further comprises the step of screen printing
said back surface contact grid, and wherein said step of applying
said front surface contact grid further comprises the step of
screen printing said front surface contact grid.
45. The method of claim 43, wherein said step of isolating said
front surface junction is performed using a laser scriber.
46. The method of claim 43, further comprising the step of
depositing a conductive interface layer between said layer of
amorphous silicon and said layer of metal, wherein said conductive
interface layer depositing step is performed prior to said metal
layer depositing step.
47. A method of fabricating a bifacial solar cell, the method
comprising the steps of: depositing a dielectric layer onto a back
surface of a silicon substrate; diffusing phosphorous onto a front
surface of said silicon substrate to form an n.sup.+ layer and a
front surface junction; removing a phosphor-silicate glass (PSG)
formed during said phosphorous diffusing step; depositing a front
surface passivation and anti-reflection (AR) dielectric layer onto
said n.sup.+ layer; applying a back surface contact grid; applying
a front surface contact grid; firing said back surface contact
grid; firing said front surface contact grid; depositing a boron
doped layer of amorphous silicon onto said back surface contact
grid and said back surface dielectric; and depositing a metal layer
onto said boron doped layer of amorphous silicon; and isolating
said front surface junction.
48. The method of claim 47, wherein said step of applying said back
surface contact grid further comprises the step of screen printing
said back surface contact grid, and wherein said step of applying
said front surface contact grid further comprises the step of
screen printing said front surface contact grid.
49. The method of claim 47, wherein said step of isolating said
front surface junction is performed using a laser scriber.
50. The method of claim 47, further comprising the step of
depositing a conductive interface layer between said boron doped
layer of amorphous silicon and said layer of metal, wherein said
conductive interface layer depositing step is performed prior to
said metal layer depositing step.
51. The method of claim 50, wherein said conductive interface layer
is comprised of a material selected from the group consisting of
indium tin oxide and aluminum-doped zinc oxide.
52. The method of claim 47, wherein said steps of firing said back
and front surface contact grids are performed simultaneously.
53. The method of claim 47, wherein said step of firing said back
surface contact grid is performed prior to said step of applying
said front surface contact grid.
54. The method of claim 47, wherein said PSG removing step further
comprises the step of etching said front surface with a
hydrofluoric etch.
55. A bifacial solar cell, comprising: a silicon substrate of a
first conductivity type with a front surface and a back surface; a
first dielectric layer deposited on said back surface of said
silicon substrate; an active region of a second conductivity type
located on at least a portion of said front surface of said silicon
substrate; a second dielectric layer deposited on said active
region; a first contact grid applied to said first dielectric
layer, said first contact grid comprised of a first metal, wherein
after a firing step said first contact grid is alloyed through said
first dielectric layer to said back surface of said silicon
substrate; a amorphous silicon layer doped with a dopant of said
first conductivity type, said amorphous silicon layer deposited on
said first contact grid and said first dielectric layer; and a
blanket layer deposited on said amorphous silicon layer, said
blanket layer comprised of a third metal.
56. The bifacial solar cell of claim 55, further comprising a
conductive interface layer interposed between said amorphous
silicon layer and said blanket layer.
57. The bifacial solar cell of claim 56, wherein said conductive
interface layer is selected from the group of materials consisting
of indium tin oxide and aluminum doped zinc oxide.
58. The bifacial solar cell of claim 55, wherein said silicon
substrate is comprised of a p-type silicon, said active region is
comprised of n.sup.+ material resulting from a phosphorous
diffusion step, and said amorphous silicon layer further comprises
a boron dopant.
59. The bifacial solar cell of claim 55, further comprising a grid
pattern of a third metal deposited directly on said back surface of
said silicon substrate and interposed between said back surface of
said silicon substrate and said first dielectric layer, wherein
said first contact grid is registered to said grid pattern, and
wherein after said firing step said first contact grid is alloyed
through said first dielectric layer to said grid pattern of said
third metal.
60. The bifacial solar cell of claim 55, wherein said first contact
grid is applied directly to said back surface of said silicon
substrate and prior to said first dielectric layer.
61. The bifacial solar cell of claim 55, further comprising a
groove on said front surface of said silicon substrate, said groove
isolating a front junction formed by said active region and said
silicon substrate.
62. The bifacial solar cell of claim 55, wherein said silicon
substrate is comprised of an n-type silicon, said active region is
comprised of p.sup.+ material resulting from a boron diffusion
step, and said amorphous silicon layer further comprises a
phosphorous dopant.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of the filing date of
U.S. Provisional Patent Application Ser. No. 61/215,199, filed May
1, 2009, the disclosure of which is incorporated herein by
reference for any and all purposes.
FIELD OF THE INVENTION
[0002] The present invention relates generally to solar cells and,
in particular, to an improved structure and manufacturing process
for a bifacial solar cell.
BACKGROUND OF THE INVENTION
[0003] Bifacial solar cells (BSC) may use any of a variety of
different designs to achieve higher efficiencies than those
typically obtained by a conventional, monofacial solar cell. One
such design is shown in U.S. Pat. No. 5,665,175 which discloses a
BSC configuration with first and second active regions formed on
the front and back surfaces of the BSC, respectively, the two
regions separated by a distance .lamda.. The distance .lamda.
allows a leakage current to flow between the first and second
active regions, thus allowing a solar cell panel utilizing such
bifacial cells to continue to operate even if one or more
individual solar cells become shaded or defective.
[0004] U.S. Pat. No. 7,495,167 discloses an n.sup.+pp.sup.+
structure and a method of producing the same. In the disclosed
structure, the p.sup.+ layer, formed by boron diffusion, exhibits a
lifetime close to that of the initial level of the substrate. In
order to achieve this lifetime, the '167 patent teaches that after
phosphorous gettering, the cell must be annealed at a temperature
of 600.degree. C. or less for one hour or more. In order to retain
the lifetime recovered by the phosphorous and low-temperature born
gettering steps, the cell then undergoes a final heat treatment
step in which the cell is fired at a temperature of around
700.degree. C. or less for one minute or less.
[0005] U.S. Patent Application Publication No. 2005/0056312
discloses an alternative technique for achieving two or more p-n
junctions in a single solar cell, the disclosed technique using
transparent substrates (e.g., glass or quartz substrates). In one
disclosed embodiment, the BSC includes two thin-film
polycrystalline or amorphous cells formed on opposing sides of a
transparent substrate. Due to the design of the cell, the high
temperature deposition of the absorber layers can be completed
before the low temperature deposition of the window layers, thus
avoiding degradation or destruction of the p-n junctions.
[0006] Although there are a variety of BSC designs and techniques
for fabricating the same, these designs and techniques tend to be
relatively complex, and thus expensive. Accordingly, what is needed
is a solar cell design that achieves the benefits associated with
bifacial solar cells while retaining the manufacturing simplicity
of a monofacial solar cell. The present invention provides such a
design.
SUMMARY OF THE INVENTION
[0007] The present invention provides a simplified manufacturing
process and the resultant bifacial solar cell (BSC), the simplified
manufacturing process reducing manufacturing costs. In accordance
with the invention, the BSC utilizes a combination of a back
surface contact grid and an overlaid blanket metal reflector.
Additionally, a doped amorphous silicon layer is interposed between
the contact grid and the blanket layer.
[0008] In one embodiment of the invention, the manufacturing method
is comprised of the steps of depositing a dopant of a first
conductivity type onto the back surface of a silicon substrate to
form a back surface doped region where the silicon substrate is of
the same conductivity type as the dopant, depositing a back surface
dielectric layer over the back surface doped region, forming an
active area of a second conductivity type on the front surface of
the silicon substrate, etching the active area, depositing a front
surface passivation and AR dielectric layer onto the active area,
applying and firing front and back surface contact grids,
depositing a layer of doped amorphous silicon onto the back surface
contact grid and the back surface dielectric, depositing a layer of
metal over the doped amorphous silicon layer, and isolating the
front active area. The method may further comprise the step of
depositing a conductive interface layer between the doped amorphous
silicon layer and the metal layer.
[0009] In at least one embodiment of the invention, a manufacturing
method is provided that is comprised of the steps of depositing a
boron doped layer onto the back surface of a p-type silicon
substrate, depositing a back surface dielectric over the boron
doped layer, diffusing phosphorous onto the front surface of the
silicon substrate to form an n.sup.+ layer and a front surface
junction, removing the phosphor-silicate glass formed during the
diffusion step (e.g., by etching with HF), depositing a front
surface passivation and AR dielectric layer onto the n.sup.+ layer,
applying front and back surface contact grids, firing the front and
back surface contact grids, depositing a boron doped layer of
amorphous silicon onto the back surface grid and the back surface
dielectric, depositing a metal layer onto the boron doped amorphous
silicon layer, and isolating the front surface junction using, for
example, a laser scriber. The method may further comprise the step
of depositing a conductive interface layer, for example comprised
of ITO or ZnO:Al, between the boron doped amorphous silicon layer
and the metal layer. The front and back surface contact grid firing
steps may be performed simultaneously. Alternately, the back
surface contact grid applying and firing steps may be performed
prior to, or after, the front surface contact grid applying and
firing steps. The boron doped layer depositing step can be formed
by depositing a boron doped silicon dioxide layer using CVD,
depositing a boron doped polysilicon layer using CVD, depositing a
boron doped amorphous silicon layer using PE-CVD, spray coating a
boric acid solution onto the back surface of the substrate, or
spray/wipe coating a boron-doped spin-on glass onto the back
surface of the substrate. The phosphorous diffusing step may be
performed at a temperature of approximately 850.degree. C. for a
duration of approximately 10 to 20 minutes. The back surface
dielectric depositing step may be performed after the step of
applying the back surface contact grid.
[0010] In at least one embodiment of the invention, a bifacial
solar cell (BSC) is provided that is comprised of a silicon
substrate of a first conductivity type with a front surface active
region of a second conductivity type and a back surface doped
region of the first conductivity type, dielectric layers deposited
on the front surface active region and on the back surface doped
region, a front surface contact grid applied to the front surface
dielectric layer which alloys through the front surface dielectric
to the active region during firing, a back surface contact grid
applied to the back surface dielectric layer which alloys through
the back surface dielectric to the back surface doped region during
firing, an amorphous silicon layer doped with a dopant of a first
conductivity type deposited on the back surface contact grid and
back surface dielectric, and a blanket metal layer deposited on the
doped amorphous silicon layer. The BSC may further comprise a
groove on the front surface of the silicon substrate, the groove
isolating the front surface junction. The BSC may further comprise
a conductive interface layer, for example comprised of ITO or
ZnO:Al, interposed between the doped amorphous silicon layer and
the metal layer. The silicon substrate may be comprised of p-type
silicon, the active region may be comprised of n.sup.+ material
resulting from a phosphorous diffusion step, and the doped region
and the amorphous silicon layer may further comprise a boron
dopant. The silicon substrate may be comprised of n-type silicon,
the active region may be comprised of p.sup.+ material resulting
from a boron diffusion step, and the doped region and the amorphous
silicon layer may further comprise a phosphorous dopant.
[0011] In at least one embodiment of the invention, the
manufacturing method is comprised of the steps of forming an active
area of a second conductivity type on the front surface of a
silicon substrate of a first conductivity type, etching the front
surface of the silicon substrate, depositing a front surface
passivation and AR dielectric layer onto the active area,
depositing a back surface dielectric layer over the back surface of
the silicon substrate, applying and firing front and back surface
contact grids, depositing a layer of doped amorphous silicon onto
the back surface contact grid and the back surface dielectric, and
depositing a layer of metal over the doped amorphous silicon layer.
The method may further comprise the step of removing a back surface
junction formed during the active area forming step. The method may
further comprise the step of depositing a conductive interface
layer between the doped amorphous silicon layer and the metal
layer.
[0012] In at least one embodiment of the invention, the
manufacturing method is comprised of the steps of diffusing
phosphorous onto the front surface of a silicon substrate to form
an n.sup.+ layer and a front surface junction and onto the back
surface to form a back surface junction, removing the
phosphor-silicate glass formed during the diffusion step (e.g., by
etching with HF), depositing a passivation and AR dielectric layer
on the front surface and a back surface dielectric onto the back
surface, applying and firing front and back surface contact grids,
and depositing a metal layer onto the back surface contact grid and
back surface dielectric. The front and back surface contact grid
firing steps may be performed simultaneously. Alternately, the back
surface contact grid applying and firing steps may be performed
prior to, or after, the front surface contact grid applying and
firing steps. The method may further comprise the step of removing
the back surface junction and isolating the front surface junction.
A back surface metal grid may be applied, for example by screen
printing or deposition using a shadow mask, after removing the back
surface junction and prior to depositing the dielectric layer on
the back surface. The back surface grid applying step may be
performed after removing the back surface junction and prior to
depositing the dielectric layer on the back surface.
[0013] In at least one embodiment of the invention, the
manufacturing method is comprised of the steps of depositing a back
surface dielectric onto the back surface of a silicon substrate of
a first conductivity type, forming an active area of a second
conductivity type on the front surface of the silicon substrate,
etching the front surface of the silicon substrate, depositing a
front surface passivation and AR dielectric layer onto the active
area, applying and firing front and back surface contact grids,
depositing a layer of doped amorphous silicon onto the back surface
contact grid and the back surface dielectric, depositing a layer of
metal over the doped amorphous silicon layer, and isolating the
front surface junction, for example using a laser scriber. The
method may further comprise the step of depositing a conductive
interface layer between the doped amorphous silicon layer and the
metal layer.
[0014] In at least one embodiment of the invention, the
manufacturing method is comprised of the steps of depositing a
dielectric layer on the back surface of a silicon substrate,
diffusing phosphorous onto the front surface of the substrate to
form an n.sup.+ layer and a front surface junction, removing the
phosphor-silicate glass formed during the diffusion step (e.g., by
etching with HF), depositing a front surface passivation and AR
dielectric layer, applying and firing front and back surface
contact grids, depositing a boron doped layer of amorphous silicon
onto the back surface contact grid and back surface dielectric,
depositing a metal layer onto the boron doped amorphous silicon
layer, and isolating the front surface junction, for example using
a laser scriber. The method may further comprise the step of
depositing a conductive interface layer, for example comprised of
ITO or ZnO:Al, between the boron doped amorphous silicon layer and
the metal layer. The front and back surface contact grid firing
steps may be performed simultaneously. Alternately, the back
surface contact grid applying and firing steps may be performed
prior to, or after, the front surface contact grid applying and
firing steps.
[0015] In at least one embodiment of the invention, a bifacial
solar cell (BSC) is provided that is comprised of a silicon
substrate with a front surface active region of a first
conductivity type, dielectric layers deposited on the front surface
active region and on the back surface of the silicon substrate, a
back surface contact grid applied to the back surface dielectric
which alloys through the back surface dielectric to the back
surface of the silicon substrate during firing, an amorphous
silicon layer doped with a dopant of the first conductivity type
deposited on the back surface contact grid and back surface
dielectric, and a blanket metal layer deposited on the doped
amorphous silicon layer. The BSC may further comprise a conductive
interface layer, for example comprised of ITO or ZnO:Al, interposed
between the doped amorphous silicon layer and the metal layer. The
silicon substrate may be comprised of p-type silicon, the active
region may be comprised of n.sup.+ material resulting from a
phosphorous diffusion step, and the amorphous silicon layer may
further comprise a boron dopant. The silicon substrate may be
comprised of n-type silicon, the active region may be comprised of
p.sup.+ material resulting from a boron diffusion step, and the
amorphous silicon layer may further comprise a phosphorous dopant.
The BSC may further comprise a metal grid pattern deposited
directly onto the back surface of the silicon substrate and
interposed between the silicon substrate and the back surface
dielectric layer. The BSC may further comprise a groove on the
front surface of the silicon substrate, the groove isolating the
front surface junction.
[0016] A further understanding of the nature and advantages of the
present invention may be realized by reference to the remaining
portions of the specification and the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 illustrates a preferred embodiment of a BSC in
accordance with the invention;
[0018] FIG. 2 illustrates the process flow for the BSC of FIG.
1;
[0019] FIG. 3 illustrates an alternate embodiment of the BSC of
FIG. 1;
[0020] FIG. 4 illustrates the process flow for the BSC of FIG.
3;
[0021] FIG. 5 illustrates an alternate fabrication process for the
BSC of FIG. 1;
[0022] FIG. 6 illustrates an alternate preferred embodiment of a
BSC in accordance with the invention;
[0023] FIG. 7 illustrates the process flow for the BSC of FIG.
6;
[0024] FIG. 8 illustrates an alternate preferred embodiment of a
BSC in accordance with the invention;
[0025] FIG. 9 illustrates the process flow for the BSC of FIG.
8;
[0026] FIG. 10 illustrates an alternate fabrication process for the
BSC of FIG. 6;
[0027] FIG. 11 illustrates an alternate embodiment of the BSC of
FIG. 8; and
[0028] FIG. 12 illustrates the process flow for the BSC of FIG.
11.
DESCRIPTION OF THE SPECIFIC EMBODIMENTS
[0029] A conventional mono-facial solar cell includes a grid-shaped
electrode on the front surface and a solid electrode covering the
entire back surface. In contrast, in a conventional bifacial solar
cell (BSC), the electrode structure is designed to allow light to
enter not only from the front surface, but also from the back
surface. As such, the solid electrode covering the back surface in
the mono-facial cell is replaced by a grid electrode in the BSC. In
such a cell, the grid-shaped back surface electrode allows light,
e.g., indirect light, to enter from the rear. Additionally, such a
design provides improved efficiency due to the decreased contact
area of the grid-shaped back surface electrode. In accordance with
the present invention, bifacial solar cells are provided that
combine a non-continuous, e.g., grid-shaped, back surface electrode
with a back surface reflector, thereby obtaining the advantage of
improved efficiency.
[0030] FIG. 1 illustrates a cross-sectional view of a preferred BSC
structure fabricated in accordance with the procedure described in
FIG. 2. Silicon substrate 101 may be of either p- or n-type. In the
exemplary device and process illustrated in FIGS. 1 and 2, a p-type
substrate is used.
[0031] Initially, substrate 101 is prepared using any of a variety
of well-known substrate preparatory processes (step 201). In
general, during step 201 saw and handling induced damage is removed
via an etching process, for example using a nitric and hydrofluoric
(HF) acid mixture. After substrate preparation, the bottom surface
of substrate 101 is doped, thereby forming a back surface doped
region 103 (step 203). Preferably region 103 is doped with the same
doping type as substrate 101. Increasing the doping level of region
103, compared to substrate 101, lowers the contact resistance.
Additionally, doped region 103 reduces back surface recombination,
a problem that is exacerbated by the inclusion of a back surface
reflector. In at least one embodiment of the invention, region 103
is doped with a different doping type than that of substrate
101.
[0032] Region 103 can be formed using any of a variety of
techniques. Exemplary techniques include, but are not limited to,
chemical vapor deposition (CVD), plasma enhanced CVD (PE-CVD),
spray coating, and spin coating. Accordingly, and assuming a p-type
substrate and a p-type region 103, this region can be formed by
depositing a boron doped polysilicon layer using CVD; depositing a
boron doped silicon dioxide or amorphous silicon layer using
PE-CVD; spray/spin coating a boric acid solution or doped spin-on
glass onto the back surface of substrate 101; or by other
means.
[0033] After formation of region 103, a dielectric layer 105 is
deposited on the back surface of substrate 101, specifically on top
of doped region 103 as shown (step 205). Preferably layer 105 is
comprised of silicon nitride or silicon dioxide or a silicon
dioxide/silicon nitride stack, preferably deposited using PE-CVD
techniques at a temperature of 300.degree. C. to 400.degree. C.,
and has a thickness of approximately 76 nanometers for silicon
nitride or 100 nanometers for silicon oxide. Next, an active region
of a conductivity type different from that of the substrate is
formed on the front surface of substrate 101. For example, assuming
a p-type substrate, during step 207 phosphorous is diffused onto
the front surface of substrate 101, creating n.sup.+ layer 107 and
a p-n junction at the interface of substrate 101 and n.sup.+ layer
107. Preferably n.sup.+ layer 107 is formed using phosphoryl
chloride (POCl.sub.3), where the diffusion is performed at a
diffusion temperature in the range of 825.degree. C. to 890.degree.
C., preferably at a temperature of approximately 850.degree. C.,
for 10 to 20 minutes in a nitrogen atmosphere (step 207). It will
be appreciated that during the phosphorous diffusion step 207,
boron from region 103 is diffused into the back surface of
substrate 101 to form a back surface field (BSF). The
phosphor-silicate glass (PSG) formed during diffusion step 207 is
then etched away, for example using a hydrofluoric (HF) etch at or
near room temperature for 1 to 5 minutes (step 209). In the
preferred embodiment, the front side junction has a depth of 0.3 to
0.6 microns and a surface doping concentration of about
8.times.10.sup.21/cm.sup.3.
[0034] In step 211, a front surface passivation and anti-reflection
(AR) dielectric layer 109 is deposited, preferably comprised of
silicon nitride or silicon oxynitride or a stack of materials of
the silicon oxide/silicon nitride system. In one embodiment, layer
109 is comprised of an approximately 76 nanometer thick layer of
silicon nitride. In another embodiment, layer 109 is comprised of
approximately 10 nanometers of SiO.sub.2 under 70 nanometers of
Si.sub.3N.sub.4. Preferably, layer 109 is deposited at a
temperature of 300.degree. C. to 400.degree. C.
[0035] After deposition of the dielectric layer 109, contact grids
are applied to the front and back surfaces of BSC 100 (step 213),
for example using a screen printing process. In the exemplary
embodiment, front contact grid 111 is comprised of silver while
back contact grid 113 is comprised of an aluminum-silver mixture.
In the preferred embodiment, both the front and back contact grids
are aligned and use the same contact size and spacing, with
electrodes being approximately 100 microns wide, 15 microns thick
and spaced approximately 2.5 millimeters apart. In at least one
alternate embodiment, the back contact grid uses a finer spacing in
order to lessen resistance losses from lateral current flow in the
substrate. Next, a contact firing step 215 is performed, preferably
at a peak temperature of 750.degree. C. for 3 seconds in air. As a
result of this process, contacts 111 alloy through passivation and
AR dielectric coating 109 to n.sup.+ layer 107. Similarly, contacts
113 alloy through dielectric coating 105 to layer 103. It should be
understood that either a single firing step can be performed as
shown, or the front surface and back surface contact grids can be
applied and fired separately, thereby allowing different firing
conditions to be used for each grid.
[0036] Although the back reflector may be deposited directly over
back surface dielectric layer 105 and contacts 113, preferably a
layer 115 of amorphous silicon is applied first to the back surface
(step 217). Layer 115 is preferably thin to minimize infrared
absorption and series resistance, on the order of 5 to 40
nanometers thick, and deposited using a technique such as PE-CVD.
Layer 115 is heavily doped, preferably at a level of
10.sup.19/cm.sup.3 or greater, with the same dopant type as
substrate 101, i.e., p-type dopant in exemplary structure which
uses a p-type substrate. For the exemplary embodiment, boron is
used as the dopant. Lastly, the blanket metal layer 117 is
deposited on the back surface of the structure (step 219), metal
layer 117 providing both a back surface reflector and means for
making an electrical connection with contacts 113. Typically layer
117 is 1 to 10 microns thick, with a thinner layer preferred to
minimize wafer bowing. Given the bandgap of amorphous silicon,
i.e., 1.75 eV, layer 115 is transparent to the long wavelength
photons that reach the reflective layer 117. Lastly, the front
junction is isolated, for example using a laser scriber to form a
groove on the front cell surface around the periphery of the cell
(step 221).
[0037] Blanket metal layer 117 is preferably deposited using either
physical vapor deposition (PVD) or screen printing, although it
will be appreciated that other techniques can be used. Preferably,
layer 117 has a high red reflectance, thus extending the photon
path length in region 101 and increasing the absorption of photons
with a wavelength near the bandgap. Additionally, low cost metals
are preferred, such as aluminum. Although not shown, silver bus
bars, a nickel vanadium coating or other materials can be added to
the back surface of layer 117 to further enable soldering of back
contacts.
[0038] FIGS. 3 and 4 illustrate an alternate embodiment utilizing a
minor modification of the previously described device structure and
process. In structure 300, a thin conductive interface layer 301 is
added between silicon layer 115 and back surface reflector layer
117 (step 401). Layer 301 prevents the metal of layer 117, e.g.,
aluminum, mixing with the silicon of layer 115, thereby helping to
maintain the high reflectivity of layer 117. Exemplary materials
for layer 301 include indium tin oxide (ITO) and aluminum-doped
zinc oxide (ZnO:Al). Optimally, the thickness of layer 301 is
chosen to provide an optical match between the back surface and the
metal layer 117 in the near infrared when taken in combination with
the thickness of back surface dielectric layer 105. Thus, for
example, if layer 105 is 50 nanometers thick, then the thickness of
a ZnO:Al layer 301 should be approximately 35 nanometers thick.
[0039] FIG. 5 illustrates an alternate process for fabricating cell
100. In this process, after the formation of region 103 (step 203),
the phosphorous is diffused into the front surface of substrate 101
(step 207) to create the n.sup.+ layer 107 and the p-n junction,
thereby skipping back surface dielectric deposition step 205. Next,
the PSG is etched away (step 209) and front surface dielectric 109
is deposited (step 211). The front surface contacts 111 and the
back surface contacts are then applied (step 213), followed by the
deposition of back surface dielectric layer 105 (step 501). As
previously noted, back surface dielectric layer 105 is preferably
comprised of silicon nitride or silicon dioxide or a silicon
dioxide/silicon nitride stack. If desired, the order of steps 211,
213 and 501 can be altered, for example applying the back contact
grid 113 first, followed by deposition of back surface dielectric
layer 105, followed by the application of the front contact grid
111, and then followed by the deposition of the front surface
dielectric layer 109.
[0040] After firing the front and back surface contact grids (step
215), amorphous silicon layer 115 is deposited (step 217), followed
by the deposition of blanket reflective layer 117 (step 219), all
as previously described. Although not shown, if desired conductive
interface layer 301 may be added between silicon layer 115 and back
surface reflector layer 117.
[0041] FIGS. 6 and 7 illustrate an alternate embodiment that
eliminates doped region 103. In this embodiment, after substrate
preparation step 201, front and back surface junctions are formed.
Assuming the p-type substrate of the exemplary embodiments,
phosphorous is diffused onto the front surface of substrate 101 as
previously described, creating n.sup.+ layer 107 and a p-n junction
at the interface of substrate 101 and n.sup.+ layer 107 (step 701).
During step 701, phosphorous is also diffused onto the back surface
of substrate 101, creating n.sup.+ layer 601 and a floating
junction. Preferably step 701 is performed using phosphoryl
chloride (POCl.sub.3) with a diffusion temperature in the range of
825.degree. C. to 890.degree. C., preferably at a temperature of
approximately 850.degree. C., for 10 to 20 minutes in a nitrogen
atmosphere. Active region diffusing step 701 is followed by a PSG
(assuming phosphorous) etching step 209, preferably using an HF
etch at or near room temperature for 1 to 5 minutes.
[0042] In step 703, a front surface passivation and anti-reflection
(AR) dielectric layer 603 is deposited as well as a back surface
passivation and AR dielectric layer 605. In an exemplary
embodiment, layers 603 and 605 are comprised of silicon nitride
with an index of refraction of 2.07 and a layer thickness of
approximately 76 nanometers. In an alternate embodiment, layers 603
and 605 are comprised of silicon oxynitride. In another alternate
embodiment, layers 603 and 605 are comprised of a stack of two
layers of different composition, for example 10 nanometers of
silicon dioxide and 70 nanometers of silicon nitride. Layers 603
and 605 are preferably deposited at a temperature of 300.degree. C.
to 400.degree. C.
[0043] Next, the front and back surface contact grids are applied
(step 213) and fired (step 215), followed by deposition of blanket
reflective layer 117 (step 219), all as previously described. In
this embodiment, preferably front contact grid 111 is comprised of
silver while back contact grid 113 is comprised of aluminum.
Contact firing step 215 is preferably performed at a peak
temperature of 750.degree. C. for 3 seconds in air. As a result of
this process, contacts 111 alloy through passivation and AR
dielectric coating 603 to n.sup.+ layer 107. Contacts 113 alloy
through passivation and AR dielectric coating 605 and back diffused
layer 601 to form contact to substrate 101. As aluminum is a p-type
dopant, a diode forms between back diffused layer 601 and contact
113 so that current does not flow from the back diffused layer into
the contact and the back diffusion is floating. This isolates the
back surface from the bulk 101 since there is zero current into a
floating junction. Although not shown in FIGS. 6 and 7, if desired
conductive interface layer 301 may be added between silicon layer
115 and back surface reflector layer 117. This embodiment can also
separate the contact grid deposition process and firing of the
front and back surface contact grids as previously described.
[0044] FIGS. 8 and 9 illustrate an alternate embodiment in which
the floating junction on the back surface of the substrate is
removed. In structure 800, after formation of the front junction
and PSG etching, the back surface of substrate 101 is etched (step
901), thereby removing the back surface junction and providing
isolation for the front junction. In a preferred embodiment, step
901 uses an isotropic wet silicon etch such as a mixture of nitric
acid and HF acid. After removal of the back surface floating
junction, the process continues as previously described relative to
FIGS. 6 and 7. Preferably in this embodiment the back surface
contact grid is comprised of an aluminum-silver mixture.
[0045] FIG. 10 illustrates an alternate process for fabricating
cell 600. In this process, after preparation of substrate 101 (step
201), dielectric layer 605 is applied to the back surface of
substrate 101 (step 1001). As previously described, preferably
dielectric layer 603 is comprised of silicon nitride or silicon
oxynitride. Applying dielectric layer 605 prior to diffusing the
front surface n.sup.+ layer 107 (step 701) prevents the formation
of a back surface junction. After the front surface diffusion (step
701) and the PSG etch (step 209), front surface passivation and AR
dielectric layer 603 is deposited (step 1003), followed by applying
(step 213) and firing (step 215) of the contact grids, deposition
of amorphous silicon layer 115 (step 217), and deposition of back
surface reflector 117 (step 219). Lastly, the front junction is
isolated, for example using a laser scriber to form a groove on the
front cell surface around the periphery of the cell (step 1005).
This embodiment may also include conductive interface layer 301
between silicon layer 115 and back surface reflector layer 117 and,
additionally, may separate the contact grid deposition and firing
of the front and back surface contact grids as previously
described.
[0046] FIGS. 11 and 12 illustrate a variation of BFC 800. As shown
in the BFC cross-sectional view of BFC 1100, a metal grid 1101 is
applied directly onto the back surface of cell 101 (step 1201),
thereby reducing contact resistance. Step 1201 is preferably
performed after the back surface of substrate 101 has been etched
to remove the back surface junction and isolate the front junction
(step 901). Step 1201 is performed using either a deposition
process with a shadow mask, or using a screen printing process.
Preferably, metal grid 1101 is comprised of aluminum. After
depositing dielectric layers 603 and 605 (step 703), contact grids
111 and 113 are applied and fired, either together or separately as
previously described. Back surface contact grid 113 is registered
to metal grid 1101. During the firing step, contact grid 113 alloys
to metal grid 1101. Next, amorphous silicon layer 115 is deposited
(step 217), followed by the deposition of blanket reflective layer
117 (step 219), all as previously described. Although not shown, if
desired conductive interface layer 301 may be added between silicon
layer 115 and back surface reflector layer 117.
[0047] In an alternate embodiment of that described above relative
to FIGS. 11 and 12, the process eliminates the steps of applying
and firing the back surface contact grid 113. In this embodiment,
metal grid 1101 fires through the overlaid dielectric layer,
thereby allowing metal layer 117 to connect to metal grid 1101.
[0048] As previously noted, an n-type substrate may also be used
with the invention. In such an embodiment, an n-type dopant, such
as phosphorous, is used in those regions which were previously
described as using a p-type dopant such as boron. Similarly, in
those regions which previously used a p-type dopant (e.g., boron),
an n-type dopant (e.g., phosphorous) is used. Lastly, it should be
understood that identical element symbols used on multiple figures
refer to the same component/processing step, or
components/processing steps of equal functionality.
[0049] As will be understood by those familiar with the art, the
present invention may be embodied in other specific forms without
departing from the spirit or essential characteristics thereof.
Accordingly, the disclosures and descriptions herein are intended
to be illustrative, but not limiting, of the scope of the
invention.
* * * * *