U.S. patent application number 12/429728 was filed with the patent office on 2010-10-28 for liquid electrical interconnect and devices using same.
This patent application is currently assigned to Aptina Imaging Corporation. Invention is credited to Ulrich Boettiger, Jacques Duparre, Shashikant Hegde, Rick Lake.
Application Number | 20100270458 12/429728 |
Document ID | / |
Family ID | 42991291 |
Filed Date | 2010-10-28 |
United States Patent
Application |
20100270458 |
Kind Code |
A1 |
Lake; Rick ; et al. |
October 28, 2010 |
LIQUID ELECTRICAL INTERCONNECT AND DEVICES USING SAME
Abstract
Various embodiments include interconnects for semiconductor
structures that can include a first conductive structure, a second
conductive structure and a non-hardening liquid conductive material
in contact with the first and second structure. Other embodiments
include semiconductor components and imager devices using the
interconnects. Further embodiments include methods of forming a
semiconductor structure and focusing methods for an imager
device.
Inventors: |
Lake; Rick; (US) ;
Boettiger; Ulrich; (US) ; Hegde; Shashikant;
(US) ; Duparre; Jacques; (US) |
Correspondence
Address: |
DICKSTEIN SHAPIRO LLP
1825 EYE STREET, NW
WASHINGTON
DC
20006
US
|
Assignee: |
Aptina Imaging Corporation
|
Family ID: |
42991291 |
Appl. No.: |
12/429728 |
Filed: |
April 24, 2009 |
Current U.S.
Class: |
250/208.1 ;
257/432; 257/741; 257/E21.499; 257/E23.01; 257/E31.127; 438/65 |
Current CPC
Class: |
H01L 2924/014 20130101;
H01L 2924/1433 20130101; H01L 2224/83191 20130101; H01L 2924/01079
20130101; H05K 3/4007 20130101; H01L 2224/81191 20130101; H05K 3/32
20130101; H01L 2924/01033 20130101; H01L 24/16 20130101; H01L
2924/00014 20130101; H01L 2924/01047 20130101; H01L 2224/13099
20130101; H01L 2924/00011 20130101; H01L 2924/01046 20130101; H01L
2924/00014 20130101; H01L 2924/14 20130101; H01L 2924/351 20130101;
H01L 2224/16237 20130101; H01L 21/76898 20130101; H01L 2924/01029
20130101; H01L 2924/00011 20130101; H01L 2924/1461 20130101; H01L
2924/00 20130101; H01L 2224/0401 20130101; H01L 2224/0401 20130101;
H01L 23/481 20130101; H01L 24/81 20130101; H01L 2924/01013
20130101; H05K 2201/09045 20130101; H01L 2224/81141 20130101; H01L
2924/01006 20130101; H01L 2924/1461 20130101 |
Class at
Publication: |
250/208.1 ;
257/741; 438/65; 257/432; 257/E23.01; 257/E21.499; 257/E31.127 |
International
Class: |
H01L 27/00 20060101
H01L027/00; H01L 23/48 20060101 H01L023/48; H01L 21/50 20060101
H01L021/50; H01L 31/0232 20060101 H01L031/0232 |
Claims
1. An interconnect for a semiconductor structure, the interconnect
comprising: a first conductive structure; a second conductive
structure; and a liquid conductive material in contact with the
first and second structure, the liquid conductive material
remaining a liquid during manufacture of the semiconductor
device.
2. The interconnect of claim 1, wherein the liquid conductive
material is an epoxy comprising a conductive filler.
3. The interconnect of claim 2, wherein the epoxy further comprises
an electrolyte.
4. The interconnect of claim 2, wherein the epoxy further comprises
a thinner.
5. The interconnect of claim 1, wherein the liquid conductive
material is an electrolyte.
6. The interconnect of claim 5, wherein the electrolyte comprises a
polymer.
7. The interconnect of claim 5, wherein the electrolyte comprises
polypropylene glycol and lithium based salts.
8. The interconnect of claim 5, wherein the electrolyte comprises
polyethylene oxide and salts.
9. The interconnect of claim 8, wherein the electrolyte further
comprises propylene glycol.
10. The interconnect of claim 1, wherein the liquid conductive
material has a viscosity of less than about 100,000 cps.
11. A semiconductor structure comprising: a first substrate
comprising: at least one opening, and a first conductive contact
within the at least one opening; a second substrate comprising: at
least one projection, at least one second conductive contact
integrated with the at least one projection; wherein the at least
one opening is in mating physical alignment with the at least one
projection; and a liquid conductive material within the at least
one opening, the liquid conductive material remaining a liquid
during manufacture of the semiconductor structure and providing an
electrical connection between the first conductive contact and the
at least one second conductive contact.
12. The semiconductor component of claim 11, wherein at least one
of the first substrate and second substrate comprise active
semiconductor devices.
13. The semiconductor component of claim 12, wherein the active
semiconductor devices comprise an imager device comprising a pixel
array.
14. The semiconductor component of claim 13, further comprising a
third substrate, the third substrate being at least partially
transparent and comprising at least one lens for focusing an image
on the pixel array.
15. The semiconductor component of claim 14, wherein at least one
of the first substrate and second substrate are moveable with
respect to the third substrate during operation of the device.
16. The semiconductor component of claim 11, wherein the first
conductive contact and the at least one second conductive contact
form a through interconnect.
17. The semiconductor component of claim 11, wherein the at least
one projection is a vertical pin.
18. The semiconductor component of claim 11, wherein the first
substrate and second substrate are part of an electronic device and
wherein the first substrate and second substrate are moveable with
respect to one another during operation of the device.
19. The semiconductor component of claim 11, further comprising a
device for moving at least one of the first substrate and second
substrate.
20. The semiconductor component of claim 19, wherein the device
comprises a MEMS device.
21. A method of forming a semiconductor component, the method
comprising: providing a first substrate, the first substrate
comprising: at least one opening, and a first conductive contact
within the at least one opening; at least partially filling the at
least one opening with a liquid conductive material, the liquid
conductive material remaining a liquid during the formation of the
semiconductor component; and engaging the first substrate with a
second substrate, the second substrate comprising: at least one
projection extending into the opening of the first substrate, and,
at least one second conductive contact provided on the at least one
projection engaging with the liquid conductive material.
22. The method of claim 21, further comprising: aligning the first
substrate and second substrate such that the at least one opening
is aligned with the at least one projection; and placing the at
least one opening is in mating physical engagement with the at
least one projection such that the liquid conductive material is in
contact with the first conductive contact and the at least one
second conductive contact.
23. The method of claim 21, further comprising subsequent to the
act of placing, moving at least one of the first substrate and
second substrate with respect to the other.
24. The method of claim 23, wherein the act of moving comprises
moving the first substrate away from or toward the second
substrate.
25. The method of claim 23, wherein the act of moving comprises
operating a movement device to move at least one of the first
substrate and second substrate with respect to the other.
26. The method of claim 23, further comprising providing at least
one lens, wherein the first substrate further comprises a pixel
array and wherein the act of moving comprises moving the first
substrate with respect to the at least one lens.
27. An imager device comprising: a semiconductor structure
comprising: a first substrate comprising a pixel array, a second
substrate electrically connected to the first substrate by a liquid
conductive material; at least one lens for focusing an image on the
pixel array.
28. The imager device of claim 27, wherein the device for moving at
least the first substrate is located on one of the first substrate
and second substrate.
29. The imager device of claim 27, further comprising a third
substrate, wherein the at least one lens is located on the third
substrate.
30. The imager device of claim 27, wherein the first substrate
further comprises: at least one opening, and a first conductive
contact within the at least one opening;
31. The imager device of claim 30, wherein the non-hardening liquid
conductive material is within the at least one opening.
32. The imager device of claim 31, wherein the second substrate
comprises: at least one projection extending into the opening of
the first substrate, and, at least one second conductive contact
provided on the at least one projection and engaging with the
non-hardening liquid conductive material.
33. A method of focusing an image on a pixel array of an imager
device, the method comprising: providing a semiconductor structure
comprising: first substrate comprising a pixel array, a second
substrate electrically connected to the first substrate by a liquid
conductive material to allow relative movement between the first
substrate and second substrate; arranging at least one lens to
focus an image on the pixel array; and operating a device to move
the first substrate relative to the at least one lens.
34. The method of claim 33, wherein the moving the at least one
first substrate comprises moving the first substrate during
operation of the imager device.
Description
FIELD OF THE INVENTION
[0001] This invention pertains to liquid interconnect systems, and
methods of forming conductive liquid interconnections between
electrical nodes.
BACKGROUND OF THE INVENTION
[0002] In semiconductor manufacture, packaging is the final
operation that transforms a semiconductor substrate into a
functional semiconductor component. Typically, the semiconductor
substrate is in the form of a semiconductor die. Packaging provides
protection for the semiconductor substrate, a signal transmission
system for the integrated circuits on the semiconductor substrate,
and external connection points for the component. In response to
the demand for smaller, lighter and thinner consumer products, new
semiconductor components and new packaging methods are being
developed.
[0003] In fabricating a semiconductor component, it is sometimes
necessary to provide interconnects which allow transmission of
signals from a circuit side of a semiconductor substrate to the
backside of the semiconductor substrate. Interconnects or through
wafer interconnects which extend through the semiconductor
substrate from the circuit side to the backside are sometimes
referred to as through interconnects. Typically, through
interconnects comprise metal filled vias formed in the
semiconductor substrate, which are configured to electrically
connect the integrated circuits on the circuit side to elements on
the backside of the semiconductor substrate.
[0004] In the manufacture of a semiconductor component, the
semiconductor substrate may be mounted and bonded to a second
substrate. Typically, when the two substrates are bonded, they are
securely bonded and no movement of the substrates relative to one
another is permitted. Further, with a fixed electrical connection
between the substrates, such as a solder connection, the electrical
connection can fatigue degrading the connection between the
substrates. Further, a fixed electrical connection can not
accommodate large differences in the coefficients of thermal
expansion (CTE) between the substrates.
[0005] A through interconnect that can overcome one or more of
these issues and a method of providing the same are desirable.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a diagram of a semiconductor component in
accordance with an embodiment of the invention.
[0007] FIG. 2A is a cross sectional view of the semiconductor
component of FIG. 1 along the line 2-2' at a stage of
processing.
[0008] FIG. 2B is a cross sectional view of the semiconductor
component of FIG. 1 along the line 2-2' at another stage of
processing.
[0009] FIG. 3 is a flowchart showing a method of fabricating the
semiconductor component of FIG. 1.
[0010] FIG. 4 depicts a plurality of semiconductor components at a
stage of processing.
[0011] FIGS. 5A-5C depict imager devices including the
semiconductor component of FIG. 1.
[0012] FIG. 6 is a block diagram of a processor system including
any one of the imager devices of FIGS. 5A-5C.
DETAILED DESCRIPTION OF THE INVENTION
[0013] In the following detailed description, reference is made to
the accompanying drawings which form a part hereof, and in which
are shown by way of illustration specific embodiments that may be
practiced. It should be understood that like reference numbers
represent like elements throughout the drawings. These example
embodiments are described in sufficient detail to enable those
skilled in the art to practice them. It is to be understood that
other embodiments may be utilized, and that structural, material,
and electrical changes may be made, only some of which are
discussed in detail below.
[0014] Referring to FIG. 1, a semiconductor structure 100 is
illustrated. The semiconductor structure 100 includes a first
substrate 13 (FIGS. 2A-2B); and second substrate 12 (FIGS. 2A-2B).
The first substrate 13 is, for example, a semiconductor substrate.
The second substrate 12 can be, for example, an interposer or
mounting substrate or another semiconductor substrate. In the
semiconductor structure 100, both the first substrate 13 and the
second substrate 12 can comprise silicon, or another semiconductor
material such as germanium or gallium arsenide. The second
substrate can also comprise a semiconductor material or other
suitable materials such as glasses or polymers.
[0015] The first substrate 13 includes integrated circuits. In the
illustrated example, the first substrate 13 comprises an imager die
110, having an imager device 400, including a pixel array 118.
[0016] The first substrate also includes a plurality of substrate
contacts 20 in electrical communication with the integrated
circuits. The substrate contacts 20 can comprise device bond pads,
or alternately redistribution contacts (i.e., contacts formed in
conjunction with an electrical redistribution layer (RDL)). In
addition, the substrate contacts 20 can comprise a
highly-conductive material, such as aluminum or copper. The
substrate contacts 20 can also comprise stacks of different
materials, such as aluminum-nickel-gold, aluminum-nickel-solder,
copper-palladium, and aluminum on copper.
[0017] For simplicity, the first substrate 13 is illustrated with
only eight substrate contacts 20 arranged in an edge array along
the opposite peripheral edges of the first substrate 13. However,
in actual practice the first substrate 13 can include more or fewer
substrate contacts 20 arranged in a desired configuration, such as
a center array, an edge array or an area array. Also, as shown in
FIG. 1, the substrate contacts 20 have a generally square
peripheral outline. However, the substrate contacts 20 can be
formed in a pattern having any shape including square, rectangular,
circular, triangular and oval. In addition, a size of the substrate
contacts 20 can be selected as required. Further, each substrate
contact 20 can comprise a generally planar pad as shown, or can
have other shapes such as a projection, a bump or a volcano
shape.
[0018] Referring to FIGS. 2A-2B, which shows the substrates 13 and
12 separated and then connected as well as the connection between
substrates 13 and 12, for one semiconductor structure 100 the first
substrate 13 has a circuit side or first side 41, and a back side
or second side 42. The substrate contacts 20 can be in electrical
communication with internal conductors (not shown) located within
the first substrate 13. In addition, the internal conductors can be
in electrical communication with the circuitry fabricated on the
first substrate 13. Further, the first substrate 13 includes an
electrical insulation layer 30 on the circuit side 41. The
insulation layer 30 isolates the contacts 20 from one another and
can comprise an electrically insulating material, such as BPSG
(borophosphosilicate glass), a polymer (e.g., polyimide,
polydimethylsiloxane (PDMS)) or an oxide (SiO.sub.2).
[0019] For some applications, at least some of the substrate
contacts 20 can comprise special purpose contacts. For example, the
substrate contacts 20 can comprise electrically isolated contacts
that are not in electrical communication with the integrated
circuits on the first substrate 13.
[0020] As shown in FIGS. 2A-2B, the semiconductor structure 100
also includes a plurality of through interconnects 29, each of
which connects with a respective contact 20 on substrate 13 with a
contact 22 on substrate 12 placing the contacts 20, 22 in
electrical communication with the through interconnects 29. Each
through interconnect 29 includes a sidewall insulated substrate
opening 36, such as a via, in the first substrate 13 aligned with
an associated substrate contact 20.
[0021] The openings 36 are partially filled with a liquid
conductive material 10. The amount of liquid conductive material 10
should be sufficient to provide an electrical connection between
contact 20 and contact 22 (described below), but should not
significantly overflow from opening 36 when the first and second
substrates 13, 12 are connected (as described in more detail
below). In the example illustrated in FIGS. 2A-2B, the liquid
conductive material 10 has a viscosity such that it remains within
opening 36 independent of the orientation of the second substrate
13.
[0022] The liquid conductive material 10 can be any non-solid,
non-hardening conductive material, for example, a high viscosity
putty, caulk, paste or a low viscosity liquid. In the illustrated
example, the liquid conductive material 10 is a non-hardening
material, meaning that the liquid conductive material 10 will
remain a liquid under the standard processing and operational
conditions of the structure 100. The liquid conductive material 10
should be a material that does not evaporate over its lifetime,
such as a material with a low vapor pressure, e.g., less than 1
mmHg at 20.degree. C. Other characteristics for the liquid
conductive material 10, such as viscosity, melting, freezing and
boiling points can be chosen based on the particular application of
the structure 100.
[0023] Examples of materials suitable for the liquid conductive
material 10 include a non-hardening epoxy or similar material that
includes a conductive filler, such as nano scale particles, such
that the epoxy is conductive in a liquid state.
[0024] In one example, the liquid conductive material 10 is an
uncured epoxy that is substantially conductive in the
low-viscosity, uncured form. In one example, the conductive epoxy
has sufficient conductivity that a 15 mil length sample of the
liquid conductive epoxy having cross-sectional dimensions of 50 mil
by 2 mil would have a resistance of less than about 1000 ohms along
its length while having a viscosity of less than about 1,000,000
cps.
[0025] A suitable epoxy is a silver-containing epoxy sold under the
product name 116-37A by Creative Materials, Inc. of Tyngsboro,
Mass. If desired, the silver containing epoxy can be mixed with one
or more other liquids. In one example the silver-containing epoxy
is mixed with a second liquid, which comprises an ionic salt.
Preferably, the ionic salt is soluble in at least one of the first
and second liquids. The ionic salt can comprise organic salts
and/or inorganic salts. The ionic salt can comprise, for example, a
lithium salt, such as a lithium imide salt. Suitable lithium salts
are, for example, LiAsF.sub.6 and LiN(CF.sub.3 SO.sub.2).sub.2.
[0026] The mixing of the second liquid with the epoxy can occur
prior to, or after, placement of the epoxy into opening 36. In one
example, the final concentration of ionic salt within the epoxy
mixture is from about 0.4% (by weight) to about 2% (by weight).
[0027] Suitable liquids for mixing with the silver-containing epoxy
include a thinner, which lowers the viscosity of the epoxy. The
thinner can be, for example, aliphatic glycidyl ethers and aromatic
glycidyl ethers, such as Heloxy 61 and Heloxy 7 by Shell Chemical
Company of Houston, Tex.
[0028] The liquid conductive material 10 can also be an
electrolyte. For example, polypropylene glycol mixed with lithium
based salts, such as those used in lithium and lithium ion
batteries. Other examples of electrolyte materials suitable for the
liquid conductive material 10 include polymer electrolytes that use
polyethylene oxide (PEO) with salts. The melting point of PEO is
38.degree. C., which can be lowered by the salts or other
additives. Further, the viscosity of PEO can be modified by
including propylene glycol, if desired.
[0029] In another example, an electrolyte can be used in the epoxy
described above to provide conductivity in place of the silver or
to enhance conductivity in conjunction with the silver.
[0030] Each through interconnect 29 also includes a projection 38
on a front side 50 of the second substrate 12 supporting a contact
22. The projection 38 and associated contact 22 is in mating
physical engagement with an associated substrate opening 36. The
projections 38 can be vertical pins, such as wirebonded stud bumps,
or any other projection. The substrate openings 36 in the first
substrate 13 for the through interconnects 29, and the projections
38 on the second substrate 12 for the through interconnects 29, can
be formed with mating sizes and shapes using anisotropic etching
processes.
[0031] Each projection 38 includes a contact 22 configured for
physical and electrical contact with the liquid conductive material
10, which, in turn is in contact with an associated substrate 13
contact 20. The contacts 22 can comprise pads or bumps formed on
the top surfaces of the projections 38, or alternately can comprise
the upper planar surfaces of the conductive connection 23
(described below). In addition, the contacts 22 can comprise metal,
solder, or a conductive polymer that provides an electrical
connection with the liquid interconnect material 10.
[0032] As shown in FIGS. 2A-2B, there are conductive connections 23
from contact 22 of projection 38 to additional circuitry 54
provided on the second substrate 12. Each projection 38 can have
one or more conductive connections 23. The conductive connection 23
can comprise an electrically conductive metal, or a conductive
polymer, deposited in an electrically insulated via of a selected
diameter, or any other conductive structures or interconnects.
[0033] The first substrate 13 can also include an electrical
insulation layer 31 on the back side 42 thereof extending into the
substrate openings 36 of the through interconnects 29, but not to
cover access to contacts 20. The electrical insulation layer 31 can
comprise a single layer of material or the substrate openings 36
can include one or more different insulation layers from that
provided on the second side 42 of the substrate 13. In addition,
the second substrate 12 includes an electrical insulation layer 32
on a front side 50 thereof, which do not cover contacts 22 or 54,
and an electrical insulation layer 33 on a backside 52 thereof. As
with the insulation layer 30, the electrical insulation layers 31,
32 and 33 can comprise an electrically insulating material, such as
a glass (e.g., borophosphosilicate glass), a polymer (e.g.,
polyimide, polydimethylsiloxane (PDMS)), or an oxide (e.g.,
SiO.sub.2) and can serve to isolate electrical circuitry 54. For
some applications, one or more of the electrical insulation layers
30, 31, 32 and 33 can be omitted.
[0034] While use of the liquid conductive material 10 as an
interconnect is described in connection with a through interconnect
29, the liquid conductive material 10 can be used with other
interconnects and to provide other electrical connections between
structures or devices. Use of the liquid conductive material 10 is
particularly suitable to accommodate large differences in the
coefficients of thermal expansion (CTE) between structures
connected by the liquid conductive material 10 or where it is
desirable to maintain movement between the structures connected by
the liquid conductive material 10, e.g., between substrates 13 and
12, such as to buffer one or the other of the structures from
vibration or to enable adjustments in the alignment between the
structures.
[0035] If desired, additional substrates, such as a third substrate
414 (FIG. 5C) can be included. Such multi-substrate semiconductor
structures 100 can be used in the fabrication of imager modules in
which case the third substrate 414 can be transparent or partially
transparent substrate and include one or more lenses 16 (FIG. 5C).
A transparent substrate can comprise glass, silicon or a composite
material (silicon on glass). In addition, for uses in imager
modules, the first substrate 13 can comprise a full thickness
semiconductor substrate or a thinned semiconductor substrate.
[0036] If the semiconductor structure 100 is used for an imager
apparatus 440 (FIGS. 5A-5C), the first substrate 13 (FIGS. 2A-2B)
can comprises an imager die 110 (FIG. 1), having an imager device
400, including a pixel array 118. The second substrate 12 can
comprise a passive element having no active semiconductor devices.
In an alternate example, the second substrate 12 can include active
semiconductor devices. The semiconductor structure 100 may also be
designed for other applications besides an imager apparatus. Thus,
the first substrate 13 can comprise another type of semiconductor
die having integrated circuits constructed in a desired electrical
configuration using active semiconductor devices. For example, the
first substrate 13 can comprise a high speed digital logic device,
such as a dynamic random access memory (DRAM), a static random
access memory (SRAM), a flash memory, a microprocessor, a digital
signal processor (DSP), an application specific integrated circuit
(ASIC), a MEMS type device (e.g., accelerometer, microphone,
speaker, electro mechanical device), a solar cell or any other
electrical component or system.
[0037] Referring to FIG. 3, a method of forming a semiconductor
structure 100 is described. While the steps 301-306 shown in FIG. 3
are shown in an exemplary order, it should be understood that the
order of the steps 301-306 can be changed and additional steps not
described can be conducted before, during and after the steps
301-306 shown in FIG. 3.
[0038] In step 301, the first and second substrates 13, 12 are
fabricated and provided for assembly. The first and second
substrates 13, 12 and the devices and electrical structures
thereon, can be formed by known methods. As shown in step 302, the
openings 36 formed in substrate 13 are partially filled with the
liquid conductive material 10. If an additional substrate is to be
included in semiconductor structure 100, such a substrate would
also be fabricated and provided in step 301.
[0039] Following fabrication of the first substrate 13 and second
substrate 12, an aligning step 303 is performed. As shown in FIG.
2A, during the aligning step 303 the first and second substrates
13, 12 are aligned, such that the projections 38 on the second
substrate 12 are aligned with the liquid conductive material 10
filled openings 36 on the first substrate 13.
[0040] In connection step 304 (FIG. 2B), the first and second
substrates 13, 12 are moved together such that the contacts 22 on
the projections 38 are placed in physical contact with the liquid
conductive material 10.
[0041] If an additional substrate is to be included in
semiconductor structure 100, such a substrate could be aligned and
connected according to known methods either before or after the
aligning and connecting steps 303, 304.
[0042] If desired, a plurality of first substrates 13 can be
aligned with a common second substrate 12 and the second substrate
12 is cut around the first substrates 13 in a singulation step 305.
The singulating step 305 can be performed using a dicing saw or
other singulation method, such as cutting with a laser or a water
jet, or by etching with a suitable wet or dry etchant. FIG. 4
depicts in top view a plurality of semiconductor components 100 in
which a plurality of first substrates 13 are connected with a
common second substrate 12, prior to a singulation step 305. As
shown in FIG. 4, the semiconductor structure 100 when singulated
around substrate 13 can have a generally rectangular chip scale
outline. Alternately, the semiconductor structure 100 and the first
substrate 13 can have any shape, such as square or triangular, and
can also have a circular or oval shape.
[0043] Although FIG. 4 shows a plurality of separate first
substrates 13 connected to a common substrate 12, it should be
understood that the plurality of first substrates 13 can also be
part of a common substrate that is connected with second substrate
12. Substrates 13 and 12 can be formed on respective semiconductor
wafers. In this case, semiconductor structures 100 are formed by
singulation through both substrates 13, 12.
[0044] Optionally, an adjusting step 306 can be performed to move
one or both of the first and second substrates 13, 12 with respect
to one another or with respect to another structure, such as lens
structure 16 (described below). As the first and second substrates
13, 12 are not fixedly bonded and are connected by the liquid
conductive material 10, the first and second substrates are
moveable to some extent with respect to one another as depicted by
arrows 202 in FIG. 2B before and after the singulation step 305.
According, the adjusting step 306 can be conducted at any time,
including during operation of an electronic device or system
including the semiconductor structure 100, e.g., an imager device
400 (FIGS. 5A-5C). Movement of the first and second substrates 13,
12 can be accomplished by a device 505 as described below in
connection with FIGS. 5A-5C.
[0045] In one example, where the semiconductor structure 100
includes an imager device 400 having a pixel array 118 on substrate
13, this movement can be used to focus an image on a pixel of the
imager device 400 by enabling movement of the first and/or second
substrates 13, 12 toward and away from one another. Thus, the
adjusting step 306 can also be a focusing step. Such movement can
also accommodate extreme differences in the coefficients of thermal
expansion (CTE) between the first and second substrates 13, 12.
Further, the liquid conductive material 10 allows one substrate 13,
12 to float with respect to the other substrate 13, 12, buffering
it from vibration.
[0046] FIGS. 5A-5C depict imager apparatuses 440 constructed using
the semiconductor structure 100 where an imager device 400 (FIG. 1)
is formed on substrate 13. In the FIG. 5A example, a lens structure
16, which may include one or more lenses for focusing an image on
pixel array 118, is located adjacent the first substrate 13. A
spacer 416 may be provided between lens structure 16 and substrate
13. Alternatively, the lens structure 16 could be located adjacent
the second substrate 12, as shown in FIG. 5B for backside imaging
of the pixel array 118. A spacer 416 may be provided lens structure
16 and substrate 12. As another alternative shown in FIG. 5C, the
semiconductor structure 100 can also include a third substrate 414
having lens structure 16, which is directly coupled to substrate
12.
[0047] During the adjusting step 306 (FIG. 3), one of the first and
second substrates 13, 12 is moved with respect to the other and
with respect to lens structure 16 as shown by arrows 202. If
desired, one substrate 13, 12 can be maintained in a fixed
alignment with lens structure 16, e.g., by spacer 416. In such a
case, only one substrate 13, 12 is moved, for example, the
substrate 13, 12 that is not in a fixed alignment with lens
structure 16. Moving one or more of the first and second substrates
13, 12 can require less power than moving the more massive lens
structure 16.
[0048] The movement can be made by a device 505 that is located
internally (FIG. 5A) or externally (FIG. 5B) to the apparatus 440.
As another alternative shown in FIG. 5C, the device 505 can be
located on the first or second substrates 13, 12. In the FIG. 5C
example, the device 505 is located on the first substrate 13, which
includes the imager device 400 (FIG. 1). The device 505 can also be
included on the second substrate 12. Where the device 505 is
located on the first or second substrate 13, 12, the device 505 can
be a micro-electromechanical system (MEMS) device.
[0049] FIG. 6 illustrates a processor system as part of a digital
still or video camera system 500 employing an imager apparatus 440
as illustrated in any of FIGS. 5A-5C, which include a semiconductor
structure 100. The processing system includes a processor 555
(shown as a CPU) which implements system, e.g. camera 500,
functions. The processor 555 is coupled with other elements of the
system, including random access memory 520, removable memory 525
such as a flash or disc memory, one or more input/output devices
510 for entering data or displaying data and/or images and imager
device 400 through bus 515 which may be one or more busses or
bridges linking the processor system components. A camera lens 535
allows an image or images of an object being viewed to pass to the
pixel array 118 (FIG. 1) of imager apparatus 440 when a "shutter
release"/"record" button 540 is depressed.
[0050] The camera system 500 is only one example of a processing
system having digital circuits that could include image sensor
devices. Without being limiting, such a system could also include a
computer system, cell phone system, scanner, machine vision system,
vehicle navigation system, video phone, surveillance system, auto
focus system, star tracker system, motion detection system, image
stabilization system, and other image processing systems.
[0051] While disclosed embodiments have been described in detail,
it should be readily understood that the invention is not limited
to the disclosed embodiments. Rather the disclosed embodiments can
be modified to incorporate any number of variations, alterations,
substitutions or equivalent arrangements not heretofore
described.
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