U.S. patent application number 12/398942 was filed with the patent office on 2010-09-09 for microfabricated inductors with through-wafer vias.
This patent application is currently assigned to TELEDYNE SCIENTIFIC & IMAGING, LLC. Invention is credited to Robert L. Borwick, III, Jeffrey F. DeNatale, Alexandros Papavasiliou, Philip A. Stupar.
Application Number | 20100225436 12/398942 |
Document ID | / |
Family ID | 42677731 |
Filed Date | 2010-09-09 |
United States Patent
Application |
20100225436 |
Kind Code |
A1 |
Papavasiliou; Alexandros ;
et al. |
September 9, 2010 |
MICROFABRICATED INDUCTORS WITH THROUGH-WAFER VIAS
Abstract
The present invention relates to microfabricated inductors with
through-wafer vias. In one embodiment, the present invention is an
inductor including a first wafer, a first plurality of metal
fillings located within the first wafer, and a first plurality of
metal conductors connecting the first plurality of metal fillings
together to form a first spiral with a first plurality of windings.
In another embodiment, the present invention is a method for
producing an inductor including the steps of forming a first
plurality of vias in a first substrate, filling the first plurality
of vias in the first substrate with a first plurality of metal
fillings, forming a first plurality of metal conductors, and
connecting pairs of the first plurality of metal fillings together
using the first plurality of metal conductors to form a spiral.
Inventors: |
Papavasiliou; Alexandros;
(Thousand Oaks, CA) ; DeNatale; Jeffrey F.;
(Thousand Oaks, CA) ; Stupar; Philip A.; (Oxnard,
CA) ; Borwick, III; Robert L.; (Thousand Oaks,
CA) |
Correspondence
Address: |
Snell & Wilmer L.L.P. (TELEDYNE)
600 ANTON BOULEVARD, SUITE 1400
COSTA MESA
CA
92626
US
|
Assignee: |
TELEDYNE SCIENTIFIC & IMAGING,
LLC
Thousand Oaks
CA
|
Family ID: |
42677731 |
Appl. No.: |
12/398942 |
Filed: |
March 5, 2009 |
Current U.S.
Class: |
336/200 ;
29/602.1 |
Current CPC
Class: |
H01F 2017/0086 20130101;
H01F 17/0013 20130101; Y10T 29/49165 20150115; Y10T 29/49073
20150115; Y10T 29/4902 20150115; H01F 17/03 20130101 |
Class at
Publication: |
336/200 ;
29/602.1 |
International
Class: |
H01F 5/00 20060101
H01F005/00; H01F 7/06 20060101 H01F007/06 |
Claims
1. An inductor comprising: a first wafer; a first plurality of
metal fillings located within the first wafer; and a first
plurality of metal conductors connecting the first plurality of
metal fillings together to form a first spiral with a first
plurality of windings.
2. The inductor of claim 1 wherein the first wafer includes a first
plurality of vias coated with an insulation material, the first
plurality of vias containing the first plurality of metal
fillings.
3. The inductor of claim 1 wherein the first wafer includes a first
plurality of trenches coated with an insulation material, the first
plurality of trenches containing the first plurality of metal
conductors.
4. The inductor of claim 3 wherein each of the first plurality of
trenches have a depth to spacing aspect ratio equal to or greater
than 2:1.
5. The inductor of claim 1 wherein the first plurality of metal
fillings is rectangular shaped in cross section.
6. The inductor of claim 1 wherein the first plurality of metal
fillings is oval shaped in cross section.
7. The inductor of claim 1 further comprising: a second plurality
of metal fillings located within the first wafer, each of the
second plurality of metal fillings connected to one of the first
plurality of metal fillings to form a metal fillings group
conducting in parallel.
8. The inductor of claim 1 further comprising: a second plurality
of metal fillings located within the first wafer; and a second
plurality of metal conductors connecting the second plurality of
metal fillings together to form a second spiral including a second
plurality of windings, the first spiral connected to the second
spiral to form a spiral group conducting in parallel.
9. An inductor comprising: a first wafer; a first plurality of
metal fillings located within the first wafer; a first plurality of
metal conductors connecting pairs of the first plurality of metal
fillings together to form a first portion of a first spiral; a
second wafer; a second plurality of metal fillings located within
the second wafer; and a second plurality of metal conductors
connecting pairs of the second plurality of metal fillings together
to form a second portion of the first spiral, the first portion of
the first spiral and the second portion of the first spiral bonded
together to form the first spiral.
10. The inductor of claim 9 wherein the first plurality of metal
fillings are substantially aligned with the second plurality of
metal fillings.
11. The inductor of claim 10 wherein the first plurality of metal
filings and the second plurality of metal fillings are bonded
through a ductile metal bump.
12. The inductor of claim 11 wherein the ductile metal bump is a
gold bump.
13. The inductor of claim 9 wherein the first wafer includes a
first plurality of vias coated with an insulation material, the
first plurality of vias containing the first plurality of metal
fillings, and the second wafer includes a second plurality of vias
coated with the insulation material, the second plurality of vias
containing the second plurality of metal fillings.
14. The inductor of claim 9 wherein the first wafer includes a
first plurality of trenches coated with an insulation material, the
first plurality of trenches containing the first plurality of metal
conductors, and the second wafer includes a second plurality of
trenches coated with the insulation material, the second plurality
of trenches containing the second plurality of metal
conductors.
15. The inductor of claim 14 wherein the first plurality of
trenches and the second plurality of trenches each have a depth to
spacing aspect ratio equal to or greater than 2:1.
16. The inductor of claim 9 wherein the first plurality of metal
fillings is rectangular shaped in cross section.
17. The inductor of claim 9 wherein the first plurality of metal
fillings is oval shaped in cross section.
18. The inductor of claim 9 further comprising: a third plurality
of metal fillings located within the first wafer, each of the third
plurality of metal fillings connected to one of the first plurality
of metal fillings to form a first metal fillings group conducting
in parallel; and a fourth plurality of metal fillings located
within the second wafer, each of the fourth plurality of metal
fillings connected to one of the second plurality of metal fillings
to form a second metal fillings group conducting in parallel.
19. The inductor of claim 9 further comprising: a third plurality
of metal fillings located within the first wafer; a third plurality
of metal conductors connecting pairs of the third plurality of
metal fillings together to form a first portion of a second spiral;
a fourth plurality of metal fillings located within the second
wafer; and a fourth plurality of metal conductors connecting pairs
of the fourth plurality of metal fillings together, to form a
second portion of the second spiral, the first portion of the first
spiral and the second portion of the second spiral bonded to form
the second spiral, wherein the first spiral and the second spiral
are connected to form a spiral group conducting in parallel.
20. A method for producing an inductor comprising the steps of:
forming a first plurality of vias in a first substrate; filling the
first plurality of vias in the first substrate with a first
plurality of metal fillings; forming a first plurality of metal
conductors; and connecting pairs of the first plurality of metal
fillings together using the first plurality of metal conductors to
form a spiral.
21. The method of claim 20 further comprising the step of: forming
an insulating layer within the first plurality of vias.
22. The method of claim 20 further comprising the steps of: forming
a first plurality of trenches within the first substrate; forming a
first insulating layer within the first plurality of trenches; and
forming the first plurality of metal conductors on top of the first
insulating layer within the first plurality of trenches.
23. The method of claim 22 further comprising the step of:
increasing a winding density of the spiral by forming each of the
first plurality of trenches with a depth to spacing aspect ratio
equal to or greater than 2:1.
24. The method of claim 23 further comprising the step of forming
the first plurality of trenches with deep reactive ion etching
using a time sequenced etch and passivation process.
25. The method of claim 20 further comprising the step of plating
metal into photoresist molds to form the first plurality of metal
conductors.
26. The method of claim 20 wherein the first plurality of metal
fillings are formed in a rectangular cross section shape to reduce
resistance within the first plurality of metal fillings.
27. The method of claim 20 wherein the first plurality of metal
fillings are formed in an oval cross section shape to reduce
resistance within the first plurality of metal fillings.
28. The method of claim 20 further comprising the steps of: forming
a second plurality of vias in a second substrate; filling the
second plurality of vias in the second substrate with a second
plurality of metal fillings; forming a second plurality of metal
conductors; connecting pairs of the second plurality of metal
fillings together using the second plurality of metal conductors;
and connecting the first plurality of metal fillings to the second
plurality of metal fillings to form the spiral.
29. The method of claim 28 further comprising the step of bonding
the first plurality of metal fillings to the second plurality of
metal fillings using gold thermocompression bonding.
30. The method of claim 28 further comprising the step of plating
metal into photoresist molds to form the first plurality of metal
conductors and the second plurality of metal conductors.
31. The method of claim 28 further comprising the steps of: forming
a first plurality of trenches within the first substrate; forming a
first insulating layer within the first plurality of trenches;
forming the first plurality of metal conductors on top of the first
insulating layer within the first plurality of trenches; forming a
second plurality of trenches within the second substrate; forming a
second insulating layer within the second plurality of trenches;
and forming the second plurality of metal conductors on top of the
second insulating layer within the second plurality of
trenches.
32. The method of claim 31 further comprising the step of
increasing a winding density of the spiral by forming each of the
first plurality of trenches and each of the second plurality of
trenches with a depth to spacing aspect ratio equal to or greater
than 2:1.
33. The method of claim 32 further comprising the step of forming
the first plurality of trenches and the second plurality of
trenches with deep reactive ion etching using a time sequenced etch
and passivation process.
34. The method of claim 28 wherein the first plurality of metal
fillings and the second plurality of metal fillings are formed in a
rectangular cross section shape to reduce resistance within the
first plurality of metal fillings and the second plurality of metal
fillings.
35. The method of claim 28 wherein the first plurality of metal
fillings and the second plurality of metal fillings are formed in
an oval cross section shape to reduce resistance within the first
plurality of metal fillings and the second plurality of metal
fillings.
Description
BACKGROUND
[0001] 1. Field
[0002] The present invention relates to microfabricated inductors
with through-wafer vias.
[0003] 2. Related Art
[0004] RF systems often use inductors. However, conventional
inductors with an air center require a large amount of physical
space and may also have a relatively low Q factor. This can place a
limit or hamper the ability of reducing the size of RF systems.
Furthermore, the relatively low Q factor can reduce the performance
of RF systems at high frequencies.
[0005] Thus, there is a need for inductors which occupy a reduced
amount of space and possess an improved Q factor.
SUMMARY
[0006] In one embodiment, the present invention is an inductor
including a first wafer, a first plurality of metal fillings
located within the first wafer, and a first plurality of metal
conductors connecting the first plurality of metal fillings
together to form a first spiral with a first plurality of
windings.
[0007] In another embodiment, the present invention is an inductor
including a first wafer, a first plurality of metal fillings
located within the first wafer, a first plurality of metal
conductors connecting pairs of the first plurality of metal
fillings together to form a first portion of a first spiral. The
present invention also includes a second wafer, a second plurality
of metal fillings located within the second wafer, and a second
plurality of metal conductors connecting pairs of the second
plurality of metal fillings together to form a second portion of
the first spiral. The first portion of the first spiral and the
second portion of the first spiral can be bonded together to form
the first spiral.
[0008] In yet another embodiment, the present invention is a method
for producing an inductor including the steps of forming a first
plurality of vias in a first substrate, filling the first plurality
of vias in the first substrate with a first plurality of metal
fillings, forming a first plurality of metal conductors, and
connecting pairs of the first plurality of metal fillings together
using the first plurality of metal conductors to form a spiral.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The features, objects, and advantages of the present
invention will become more apparent from the detailed description
set forth below when taken in conjunction with the drawings,
wherein:
[0010] FIG. 1 is a perspective view of an embodiment of the present
invention;
[0011] FIG. 2 is a top view of an embodiment of the present
invention;
[0012] FIG. 3 is a graph of Q factors;
[0013] FIG. 4 is a side view of a production of an embodiment of
the present invention;
[0014] FIG. 5 is a side view of a production of an embodiment of
the present invention;
[0015] FIG. 6 is a side view of a production of an embodiment of
the present invention;
[0016] FIG. 7 is a side view of a production of an embodiment of
the present invention;
[0017] FIG. 8 is a side view of a production of an embodiment of
the present invention;
[0018] FIG. 9 is a side view of a production of an embodiment of
the present invention;
[0019] FIG. 10 is a side view of a production of an embodiment of
the present invention;
[0020] FIG. 11 is a side view of a production of an embodiment of
the present invention;
[0021] FIG. 12 is a side view of a production of an embodiment of
the present invention;
[0022] FIG. 13 is a side view of a production of an embodiment of
the present invention;
[0023] FIG. 14 is a side view of a production of an embodiment of
the present invention;
[0024] FIG. 15 is a side view of a production of an embodiment of
the present invention;
[0025] FIG. 16 is a side view of a production of an embodiment of
the present invention;
[0026] FIG. 17 is a side view of a production of an embodiment of
the present invention;
[0027] FIG. 18 is a side view of a production of an embodiment of
the present invention;
[0028] FIG. 19 is a side view of a production of an embodiment of
the present invention;
[0029] FIG. 20 is a side view of a production of an alternate
embodiment of the present invention;
[0030] FIG. 21 is a side view of a production of an alternate
embodiment of the present invention;
[0031] FIG. 22 a side view of a production of an alternate
embodiment of the present invention;
[0032] FIG. 23 a side view of a production of an alternate
embodiment of the present invention;
[0033] FIG. 24 a side view of a production of an alternate
embodiment of the present invention;
[0034] FIG. 25 a side view of a production of an alternate
embodiment of the present invention;
[0035] FIG. 26 a side view of a production of an alternate
embodiment of the present invention;
[0036] FIG. 27 a side view of a production of an alternate
embodiment of the present invention;
[0037] FIG. 28 a side view of a production of an alternate
embodiment of the present invention;
[0038] FIG. 29 a side view of a production of an alternate
embodiment of the present invention;
[0039] FIG. 30 a side view of a production of an alternate
embodiment of the present invention;
[0040] FIG. 31 a side view of a production of an alternate
embodiment of the present invention;
[0041] FIG. 32 a side view of a production of an alternate
embodiment of the present invention;
[0042] FIG. 33 a side view of a production of an alternate
embodiment of the present invention;
[0043] FIG. 34 a side view of a production of an alternate
embodiment of the present invention;
[0044] FIG. 35 is a side view of an alternate embodiment of the
present invention;
[0045] FIG. 36 is a top view of an alternate embodiment of the
present invention; and
[0046] FIG. 37 is a top view of an alternate embodiment of the
present invention.
DETAILED DESCRIPTION
[0047] Methods and systems that implement the embodiments of the
various features of the present invention will now be described
with reference to the drawings. The drawings and the associated
descriptions are provided to illustrate embodiments of the present
invention and not to limit the scope of the present invention.
Reference in the specification to "one embodiment" or "an
embodiment" is intended to indicate that a particular feature,
structure, or characteristic described in connection with the
embodiment is included in at least an embodiment of the present
invention. The appearances of the phrase "in one embodiment" or "an
embodiment" in various places in the specification are not
necessarily all referring to the same embodiment. Throughout the
drawings, reference numbers are re-used to indicate correspondence
between referenced elements.
[0048] FIG. 1 is a perspective view of an embodiment of the present
invention while FIG. 2 is a top view of an embodiment of the
present invention depicted in FIG. 1. As shown in FIG. 1 and FIG.
2, an inductor 2 is formed within a substrate 4. Substrate 4 can be
formed, for example, from silicon (Si), insulators, a combination
of silicon and insulators, and/or any other type of material
suitable to form a core for an inductor. Substrate 4 can be a
silicon wafer, or a silicon on insulator (SOI) wafer. Substrate 4
can, for example, be between approximately 100 .mu.m to
approximately 1000 .mu.m thick. In one embodiment, substrate 4 is
approximately 400 .mu.m thick.
[0049] Inductor 2 includes a plurality of vias 6 which can be
filled with metal fillings 8. The metal fillings 8 can be connected
by conductors 10. Metal fillings 8 and conductors 10 can form
windings and/or loops within substrate 4. The metal fillings 8 can
be, for example, copper (Cu), copper alloys, silver (Ag), silver
alloys, or any other types of conductive metal. Conductor 10 can
also be copper (Cu), copper alloys, silver (Ag), silver alloys, or
any other types of conductive metal. In one embodiment, metal
fillings 8 and conductor 10 are formed from the same type of
conductive metal. In another embodiment, metal fillings 8 and
conductor 10 are formed from different types of conductive metal.
The conductors 10 can be formed on a surface of the substrate
4.
[0050] A current can flow, for example, into metal filling 8a, from
metal filling 8a to conductor 10a, from conductor 10a to metal
filling 8b, from metal filling 8b to conductor 10b, from conductor
10b to metal filling 8c, and so on such that the metal current
traverses the loops formed by metal fillings 8 and conductors 10
within substrate 4.
[0051] Since inductor 2 is formed within substrate 4, inductor 2
can utilize less space. Inductor 2 can be 10 times smaller in each
of three dimensions, thickness, width, and length when compared
with a conventional inductor with an air center. Thus, inductor 2
can be approximately 1,000 times smaller than conventional
inductors formed with wires, such as conventional inductors with
air centers.
[0052] FIG. 3 is a graph of Q factors. The Q factor for inductors
is governed by the equation
Q = .omega. L R ##EQU00001##
where R is the inductor's internal electrical resistance and
.omega.L is the inductor's capacitive or inductive reactance at
resonance.
[0053] As seen in FIG. 3, although the Q of a silicon-core inductor
may not be as high as that of an air-core inductor at high
frequencies, the Q of the inductor of the present invention is
comparable to the Q of an air-core inductor at frequencies less
than approximately 500 MHz. The present invention may be
particularly valuable for applications below 500 MHz where the
present invention can be used without compromising the Q. As seen
in FIG. 3 at 0.1 GHz, the Q factor of the inductors with air
centers can have a Q of approximately 10. In contrast, in one
embodiment of the present invention, the Q factor of inductor 2 is
60 at 0.1 GHz as indicated by point 42. In another embodiment of
the present invention, the Q factor of inductor 2 is 180 at 0.1 GHz
as indicated by point 44.
[0054] FIG. 19 is a side view of an embodiment of the present
invention. FIGS. 4 to 18 are side views of a production of an
embodiment of the present invention disclosed in FIG. 19. As shown
in FIG. 4, vias 6 are etched in substrate 4. Substrate 4 can have a
first side and a second side. In FIG. 4, the first side is a top
side of substrate 4 while the second side is a bottom side of
substrate 4. In FIG. 5, substrate 4 is coated with an insulation
layer 12. Insulation layer 12 can be, for example, Parylene,
silicon oxide (SiO.sub.2), or any other type of suitable insulation
material. To coat insulation layer 12 on substrate 4, substrate 4
can be thermally oxidized or insulation layer 12 can be coated by
performing deep reactive ion etching using a time sequenced etch
and passivation process, such as the Bosch process, on substrate
4.
[0055] In FIG. 6, gold layer 14 is evaporated on the second side of
substrate 4. In FIG. 7, gold layer 14 is deposited on insulation
layer 12 of a dummy wafer 16. Gold layer 14 can be deposited on
insulation layer 12 of dummy wafer 16 through evaporation. Dummy
wafer 16 can be formed, for example, from silicon 4. In FIG. 8,
dummy wafer 16 is bonded to substrate 4 through gold layer 14 for
both substrate 4 and dummy wafer 16. In FIG. 9, a metal 26 is used
to fill vias 6. Metal 26 can be, for example, copper, silver,
nickel or any other metal with a relatively high conductivity such
as the metal used for metal fillings 8. Furthermore, metal 26 can
be filled in vias 6 by electroplating metal 26 through vias 6.
[0056] In FIG. 10, photoresist 18 is placed over the first side of
substrate 4 encompassing metal 26 and insulation layer 12.
Photoresist 18 provides protection for substrate 4 and the layers
of materials between substrate 4 and photoresist 18 such as metal
26 and/or insulation layer 12. In FIG. 11, dummy wafer 16 is
removed along with photoresist 18. The removal of photoresist 18
exposes metal 26 and insulation layer 12 on the first side of
substrate 4. Dummy wafer 16 can be removed by grinding and etching
dummy wafer 16. After dummy wafer 16 is removed, insulation layer
12 which was located on the second side of substrate 4 between
dummy wafer 16 and gold layer 14 is also removed through
etching.
[0057] In FIG. 12, metal 26 that juts above substrate 4 and
insulation layer 12 on the first side of substrate 4 is removed
through polishing. In FIG. 13, both gold layers 14 are removed.
Also, metal 26 that juts above substrate 4 and insulation layer 12
on the second side of substrate 4 is also removed. In FIG. 14, seed
layer 20 is deposited on both sides of substrate 4. Seed layer 20
can be, for example, copper, gold (Au), or any other suitable
material to form conductors 10. In one embodiment, seed layer 20
can be between approximately 200 .ANG. to approximately 3000 .ANG..
In another embodiment, seed layer 20 is approximately 1000
.ANG..
[0058] In FIG. 15, photoresist 22 is layered on both sides of
substrate 4. The layer of photoresist 22 on a first side of
substrate 4 is patterned with holes where conductors 10 are formed.
In FIG. 16, metal 26 is deposited in the holes, created during the
patterning of photoresist 22, on the first side of substrate 4.
Metal 26 can be deposited in the holes created during the
patterning of photoresist 22, for example, through electroplating.
In FIG. 17, the layer of photoresist 22 that was patterned in FIG.
15 is overlayed with photoresist covering up the holes. The layer
of photoresist 22 on the second side of substrate 4 is now
patterned with holes where conductors 10 will be formed. In FIG.
18, metal 26 is filled in the holes of the layer of photoresist 22
on the second side of substrate 4. In FIG. 19, the layers of
photoresist 22 and seed layer 20 on both sides of substrate 4 are
removed to form inductor 2 with substrate 4, metal fillings 8 and
conductors 10. With the embodiment depicted in FIG. 19, inductor 2
can have a Q of approximately 60.
[0059] FIG. 35 is a side view of an alternate embodiment of the
present invention. FIGS. 20 to 34 are side views of a production of
an embodiment of the present invention disclosed in FIG. 35. In
FIG. 20, a first substrate 4 is coated with insulation layer 12. In
FIG. 35, the first substrate 4 is an SOI substrate with a first
side and a second side. In FIG. 21, insulation layer 12 is
patterned on one side of substrate 4 including forming holes on
insulation layer 12 on the first side of the first substrate 4. In
FIG. 22, the patterned insulation layer 12 on the first side is
coated with photoresist 22. A pattern is created on photoresist 22
including holes above locations on the first substrate 4 where vias
6 should be created on the first substrate 4.
[0060] In FIG. 23, holes are etched in substrate 4 where vias 6
should be formed. In addition, a layer of photoresist 22 is
deposited on the second side of the first substrate 4. The layer of
photoresist 22 on the second side of the first substrate 4 is
patterned and holes are created in the layer of photoresist 22
corresponding to the location of vias 6. In FIG. 24, holes are
etched completely through the first substrate 4 to form vias 6. In
FIG. 25, photoresist 22 is removed on both the first side and the
second side of the first substrate 4 exposing the patterned
insulation layer 12 on both the first side and the second side of
substrate 4.
[0061] In FIG. 26, trenches 24 are formed in the first substrate 4
by etching the first substrate 4 at locations corresponding to the
holes of the patterned insulation layer 12. The trenches 24 can be
formed using deep reactive ion etching according to a time
sequenced etch and passivation chemistry such as the Bosch process.
By forming the trenches through deep reactive ion etching, rather
than for example, using molds formed by photoresist, a closer
packing of the trenches may be achieved. An aspect ratio of a depth
of the trenches 24 to spacing between trenches 24 can be increased,
for example, the aspect ratio can be equal to or greater than 2:1,
such as 10:1. The larger aspect ratio increases an amount of metal
fillings and metal conductors per area thus increasing the winding
density, or the amount of windings per area, of the inductor 2.
With a higher winding density, an inductance of the inductor 2 can
be improved. The closer packing of the trenches 24 can thus improve
the performance of inductor 2.
[0062] In FIG. 27, insulation layer 24 is placed inside trenches
24. Insulation layer 24 can be placed, for example, inside trenches
24 through oxidizing the first substrate 4. In FIG. 28, seed layer
20 is sputtered on the first side of the first substrate 4. In FIG.
29, metal 26 is plated on the first side of the first substrate
4.
[0063] In FIG. 30, dummy wafer 18 is resist bonded onto metal 26
using photoresist 26 on the first side of the first substrate 4. In
FIG. 31, metal 26 is used to fill vias 6. Metal 26 can fill vias 6,
for example, through electroplating. In FIG. 32, dummy wafer 18 is
removed along with photoresist 22. In FIG. 33, excess metal 26 is
removed from both the first side and the second side of the first
substrate 4. Furthermore, both the first side and the second side
of the first substrate 4 can be polished. In FIG. 34, gold layer 14
is deposited on an end of metal 26 in via 6 on the second side of
the first substrate 4. In FIG. 35, the process depicted in FIGS. 20
to 34 is repeated for a second substrate 4. The second substrate 4,
which has gone through the process depicted in FIGS. 20 to 34, is
bonded with the first substrate 4 using a gold thermocompression
bond at gold layers 14 to form inductor 2. Gold layers 14 can be,
for example, gold bumps. With the embodiment depicted in FIG. 35,
simulations have shown that inductor 2 can have a Q as high as 180.
Although gold is used, other ductile metals can be used and the
first substrate and the second substrate can be bonded with ductile
metal bumps.
[0064] In both the embodiment depicted in FIG. 35 and the
embodiment depicted in FIG. 19, metal fillings 8 and/or conductors
10 can be advantageously formed in a rectangular or elliptical
shape in cross section. By having metal fillings 8 and/or
conductors 10 formed in a rectangular or elliptical structure, they
can be packed closer while taking up the same area thus increasing
a winding density of the inductor 2 over conventional inductors.
Conversely, with the same winding density, that is, the same amount
of metal fillings 8 and/or conductors 10 per area, there is more
current passing through the metal fillings 8 and/or conductors 10
due to the skin-effect. That is, the skin-effect drives the current
to an outside edge of conductive materials. Rectangles and/or ovals
beneficially have larger outside edges per unit area which thus
reduces an amount of resistance in metal fillings 8 and/or
conductors 10 and increases the amount of current passing through
metal fillings 8 and/or conductors 10.
[0065] FIG. 36 is a top view of an alternate embodiment of the
present invention. In FIG. 36, metal fillings 30 have a larger
width than metal fillings 8 disclosed in FIG. 1. In FIG. 36, metal
fillings 30 have a rectangular shape in cross section, but metal
fillings 30 can have any shape such as circular, oval, triangular,
etc. By increasing the width of the metal fillings, the resistance
of inductor 2 is decreased. Since the Q factor is governed by the
equation
Q = .omega. L R ##EQU00002##
where R is the inductor's internal electrical resistance and
.omega.L is the inductor's capacitive or inductive reactance at
resonance, any decrease in the amount of resistance results in an
overall increase in the Q factor.
[0066] FIG. 37 is a top view of an alternate embodiment of the
present invention. FIG. 37 includes metal fillings 34 and metal
contacts 38 which are connected in parallel to metal fillings 8 and
metal contacts 10. By doing so, two inductors can be sandwiched
into an area for a single inductor. However, since the two
inductors are connected in parallel, simulations have shown that
while the inductance may be decreased, the resistance will be
decreased at a greater amount than the decrease in inductance. For
example, the resistance can, for example, be decreased to
approximately 50% of its original value. Therefore, the inductance
would be decreased by less than 50% of its original value. Since
the corresponding decrease in resistance is greater than the
corresponding decrease in inductance, the overall Q value would be
increased.
[0067] Furthermore, as shown in FIG. 37, metal fillings 32 are
connected in parallel with metal fillings 8, while metal fillings
36 are connected in parallel with metal fillings 34. Since the
metal fillings 32 are connected in parallel, the overall resistance
of the metal fillings in inductor 2 is reduced. Since the
resistance in inductor 2 is reduced, the Q factor is increased
through metal fillings 32 being connected in parallel with metal
fillings 8 and metal fillings 36 being connected in parallel with
metal fillings 34.
* * * * *