U.S. patent application number 12/588087 was filed with the patent office on 2010-03-04 for semiconductor device and method of manufacturing same.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Osamu Arisumi, Katsuhiko Hieda, Masahiro Kiyotoshi, Yoshitaka Tsunashima.
Application Number | 20100055869 12/588087 |
Document ID | / |
Family ID | 37463992 |
Filed Date | 2010-03-04 |
United States Patent
Application |
20100055869 |
Kind Code |
A1 |
Arisumi; Osamu ; et
al. |
March 4, 2010 |
Semiconductor device and method of manufacturing same
Abstract
A method of manufacturing a semiconductor device comprises
forming a trench in a semiconductor substrate, forming a first
insulating film having a first recessed portion in the trench,
forming a coating film so as to fill the first recessed portion
therewith, transforming the coating film into a second insulating
film, planarizing the second insulating film to expose the first
insulating film and the second insulating film, removing at least
the second insulating film from the first recessed portion to
moderate an aspect ratio for the first recessed portion formed in
the trench, thereby forming a second recessed portion therein, and
forming a third insulating film on a surface of the semiconductor
substrate so as to fill the second recessed portion therewith.
Inventors: |
Arisumi; Osamu;
(Yokohama-shi, JP) ; Kiyotoshi; Masahiro;
(Sagamihara-shi, JP) ; Hieda; Katsuhiko;
(Yokohama-shi, JP) ; Tsunashima; Yoshitaka;
(Yokohama-shi, JP) |
Correspondence
Address: |
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER;LLP
901 NEW YORK AVENUE, NW
WASHINGTON
DC
20001-4413
US
|
Assignee: |
Kabushiki Kaisha Toshiba
Tokyo
JP
|
Family ID: |
37463992 |
Appl. No.: |
12/588087 |
Filed: |
October 2, 2009 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11227252 |
Sep 16, 2005 |
7618876 |
|
|
12588087 |
|
|
|
|
Current U.S.
Class: |
438/435 ;
257/E21.546 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 27/11524 20130101 |
Class at
Publication: |
438/435 ;
257/E21.546 |
International
Class: |
H01L 21/762 20060101
H01L021/762 |
Foreign Application Data
Date |
Code |
Application Number |
May 27, 2005 |
JP |
2005-155806 |
Claims
1.-8. (canceled)
9. A method of manufacturing a semiconductor device comprising:
forming a trench in a semiconductor substrate; forming a first
insulating film having a recessed portion in the trench;
planarizing an upper side of the first insulating film by a CMP
method using a slurry; removing at least the slurry remaining in
the recessed portion of the first insulating film by a chemical
solution to moderate an aspect ratio for the recessed portion
formed in the first insulating film; and forming a second
insulating film on a surface of the semiconductor substrate so as
to fill the recessed portion therewith.
10. The method according to claim 9, wherein the slurry is
comprised of a single particle containing hydrated silica as a main
component.
11. The method according to claim 9, wherein the first insulating
film is comprised of an HDP film.
12. The method according to claim 9, wherein the second insulating
film is constituted by an HDP film.
13. The method according to claim 9, wherein an annealing process
is carried out after the second insulating film is formed.
14.-17. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2005-155806,
filed May 27, 2005, the entire contents of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
a method of manufacturing the same and, in particularly, to an STI
structure having a preferable surface shape and a method of
manufacturing the same.
[0004] 2. Description of the Related Art
[0005] An element isolation technique is known as one of the
important techniques to achieve a high integration density of an
LSI. In the isolation technique, a shallow trench isolation (STI)
structure is mainly used. However, although, at the present, a
ratio of a trench width to a trench depth (aspect ratio) increases,
STI filling cannot be easily performed without forming a void or a
seam in a TEOS/O.sub.3 film obtained by a conventional
normal-pressure CVD method, an HDP-TEOS film obtained by a plasma
CVD method, or the like. Especially, in the STI filling of an NAND
flash memory, a silicon oxide film must be filled in the form of a
high aspect and taperless STI shape as compared to a logic device.
For this reason, it is difficult from 90-70-nm-width generation
that a high density plasma (HDP) single-layer oxide film, which
does not pose any problem in 130-nm-width generation, is once
filled in the STI structure.
[0006] As a countermeasure against the above problem, an STI
filling technique using a coating film has been developed. For
example, after an HDP film is formed in a trench having a depth of
350 to 450 nm from a floating gate surface to an STI bottom, a
coating film of a perhydro-silazane polymer (Polysilazane to be
referred as PSZ hereinafter) solution is formed and etched back by
devising wet etching, so that a level of STI filling may be
controlled.
[0007] However, in a trench having a narrow STI width, a wet
etching rate of the PSZ film is considerably higher than that of
the HDP film. In particular, when an etching solution containing
hydrogen fluoride is used for the STI structure having a width of
about 90 nm, a large etching rate difference of 2.5 times or more
is generated. Therefore, the PSZ film is mainly etched, and the HDP
film filled in the STI trench of the semiconductor substrate is
thinly left on a side surface of a floating gate (FG) formed
through a tunnel insulating film, or the HDP film is partially left
in the shape of a taper on the side surface of the floating
gate.
[0008] Depression of the STI filling material surface is caused by
the etching rate difference because the PSZ film is not
sufficiently transformed into SiO.sub.2. In order to decrease the
etching rate of the PSZ film in the step of densifying the
SiO.sub.2 film, a method of planarizing and then densifying the
SiO.sub.2 film is proposed. However, even in this method, when the
STI trench width is about 100 nm or less, oxygen (O.sub.2) required
to sufficiently transform the PSZ film into the SiO.sub.2 film is
not deeply supplied to the STI trench, and the situation of wet
etching controllability is still difficult.
[0009] In order to secure the drivability of the control gate on
the floating gate side surface, an improved shape (tapered shape
having a thin HDP film) is very difficult to be formed in a wafer
plane or between wafer planes with good controllability. For this
reason, even though a control gate (CG) is formed on the floating
gate and the filled HDP film through an ONO film and an interlayer
insulating film is formed on the control gate, a ratio (coupling
ratio) of a coupling capacitance C2 between the floating gate (FG)
and the control gate (CG) and a coupling capacitance C1 between the
floating gate (FG) and the substrate may fluctuate to cause a
decrease in yield.
[0010] Furthermore, when a fine device structure advances, the STI
filled surface depressed in a concave shape is close to the level
of a tunnel oxide film to cause deterioration of a breakdown
voltage between the substrate and the control gate. In this manner,
at the present, an STI technique of 90-70-nm-width generation or
later is not established, and a technique which can easily control
an STI filling level and the planarity is demanded.
[0011] As a technique that fills the trench with the HDP film, the
following technique is disclosed in Jap. Pat. Appln. KOKAI
Publication No. 2002-208629. That is, the HDP oxide film is coated
on the substrate surface until a trench opening is sealed, and an
oxide film near the opening is removed. Thereafter, an HDP oxide
film is coated again to fill the trench with the HDP oxide
film.
BRIEF SUMMARY OF THE INVENTION
[0012] According to a first aspect of the invention, a method of
manufacturing a semiconductor device comprises: forming a trench in
a semiconductor substrate; forming a first insulating film having a
first recessed portion in the trench; forming a coating film so as
to fill the first recessed portion therewith; transforming the
coating film into a second insulating film; planarizing the second
insulating film to expose the first insulating film and the second
insulating film; removing at least the second insulating film from
the first recessed portion to moderate an aspect ratio for the
first recessed portion formed in the trench, thereby forming a
second recessed portion therein; and forming a third insulating
film on a surface of the semiconductor substrate so as to fill the
second recessed portion therewith.
[0013] According to a second aspect of the invention, a method of
manufacturing a semiconductor device comprises: forming a trench in
a semiconductor substrate; forming a first insulating film having a
recessed portion in the trench; planarizing an upper side of the
first insulating film by a CMP method using a slurry; removing at
least the slurry remaining in the recessed portion of the first
insulating film by a chemical solution to moderate an aspect ratio
for the recessed portion formed in the first insulating film; and
forming a second insulating film on a surface of the semiconductor
substrate so as to fill the recessed portion therewith.
[0014] According to a third aspect of the invention, a
semiconductor device includes active regions each being isolated by
a trench and having a tunnel insulating film for providing each
memory cell and a floating gate provided on the tunnel insulating
film, the semiconductor device comprises; a first CVD oxide film
filled in the trench to at least a level of the floating gate and a
second CVD oxide film provided on the first CVD oxide film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a plan view typically showing an ordinary flash
memory cell structure;
[0016] FIG. 2 is a II-II sectional view of FIG. 1;
[0017] FIG. 3 is a III-III sectional view of FIG. 1;
[0018] FIGS. 4A to 4O are sectional views schematically showing
some of the steps in manufacturing an STI structure according to a
first embodiment;
[0019] FIGS. 5A to 5D are sectional views schematically showing
some of the steps in manufacturing an STI structure according to a
second embodiment;
[0020] FIGS. 6A to 6C are sectional views schematically showing
some of the steps in manufacturing an STI structure according to a
third embodiment; and
[0021] FIGS. 7A to 7D are sectional views schematically showing
some of the steps in manufacturing an STI structure according to a
fourth embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0022] A method of manufacturing a semiconductor device according
to a first embodiment will be described with reference to FIGS. 4A
to 4O. FIG. 1 is a plan view of a NAND flash memory cell structure
using an STI structure known by persons skilled in the art, and
FIGS. 2 and 3 are a II-II sectional view and a III-III sectional
view of FIG. 1, respectively.
[0023] More specifically, commonly, memory cells such as M1 to M8,
each having a source/a drain are arranged between select lines S1
and S2 in a matrix of rows and columns, and a word line WL and a
bit line BL (omitted) are provided. As shown in FIG. 2, each memory
cell includes a tunnel oxide film 11 composed of a silicon oxide
film, a floating gate (FG) constituted by two polysilicon films 12
and 13, a control gate (CG) 23 formed through an ONO film 22, and
an interlayer insulating film 24, which are formed on a
semiconductor substrate 10. The memory cells are electrically
isolated from each other by HDP films 18 buried in trenches. As
shown in FIG. 3, a source of a select transistor is connected to a
wiring layer 29 through a plug 28.
[0024] It is difficult that the STI structure is practically formed
by a CVD method using the HDP film or the like when filling in the
STI having a width of about 90 nm or less is realized at low cost.
The STI structure obtained by the filling technique using the
coating solution which is attempted in a development stage at the
present and the STI structure obtained by the filling technique
using the coating method shown in the embodiment are different from
each other in the following points.
[0025] More specifically, (a) in an STI structure having a width of
90 nm or less, an STI filling material surface is flat and is
uniform to a pattern width. (b) A step coverage generated in
formation of the filling material is caused to be generated outside
and above the STI to perform a planarizing process, and etching
back is performed by an etching process until an FG side wall
portion in the STI is exposed. (c) At this time, a filling material
in at least a region to be etched back has an uniform etching rate
in the entire region.
[0026] A method of forming an STI structure using such a coating
film will be described below. FIGS. 4A to 4L are sectional views of
manufacturing steps corresponding to FIG. 1. In particular, the
sectional views correspond to a region having a narrow STI width
(.ltoreq.90 nm) corresponding to a dotted-line portion in FIG. 2.
In this case, the explanation narrows down to the step of forming
an STI structure. However, before this process is performed,
formation of a sacrificial oxide film, channel ion implantation,
removal of the sacrificial oxide film, formation of a gate oxide
film, formation of a gate electrode, and formation of a
source/drain layers are performed. After the process is carried
out, formation of interlayer insulating films, formation of
contacts, and formation of wiring layers are performed in the same
manner as described above.
[0027] A process for manufacturing an STI structure of 90-nm
generation will be described below. More specifically, as shown in
FIG. 4A, an SiO.sub.2 film 11 is formed on a silicon (100)
substrate 10 to a thickness of, e.g., about 10 nm, and
polycrystalline silicon films 12 and 13 are formed on the resultant
structure by an LP-CVD method to a thickness of 150 nm.
[0028] As shown in FIGS. 4B and 4C, an Si.sub.3N.sub.4 film 14 is
formed to a thickness of about 100 nm. The Si.sub.3N.sub.4 film 14,
the polysilicon films 13 and 12, the SiO.sub.2 film 11, and the
silicon substrate 10 are processed through a mask layer 15 to form
a trench 17 for isolation STI to a depth of, e.g., about 450
nm.
[0029] In FIG. 4C, although not shown, the side surfaces of the
trench 17 are oxidized by using an ordinary thermal oxidation
method to form a thermal oxide film having a thickness of about 3
nm. This is formed to protect an exposed portion at a tunnel oxide
film end. A uniform high-quality oxide film may also be formed on
the silicon side wall of STI by using radical oxidation or the like
independently of the wafer orientation. At this time, the side
surface of the Si.sub.3N.sub.4 film 14 may be slightly
oxidized.
[0030] As shown in FIG. 4D, an HDP film 18 of a CVD oxide film is
deposited for all the trenches 17 in the wafer by an HDP-CVD method
such that a height from the silicon interface under the floating
gate to the bottom of the filled HDP is, e.g., 80 nm or more. At
this time, in the HDP film 18, the STI opening may be filled to
form a void in the trench before the STI trench is completely
filled. For this reason, the deposition process must be controlled.
Therefore, a first recessed portion 181 which is left in the HDP
film 18 without completely filling the trench is formed. As shown
in FIG. 4D, the surface of the bottom of the first recessed portion
181 is not always flat, and it may be corrugated or discontinuous.
The side surfaces of the first recessed portion 181 are not always
vertical in shape. That is, the side surfaces may have step-like
shapes or may be overhang.
[0031] As shown in FIG. 4E, a coating type solution 19 is deposited
on the substrate surface by a coating method to completely fill the
structure. For example, the coating film is formed under such a
coating condition that the coating film has a thickness of about
600 nm. In this case, for example, the PSZ is deposited by a spin
coating method, and a baking step is performed at 150.degree. C.
for about 3 minutes in a coating apparatus to vaporize the
solvent.
[0032] As shown in FIG. 4F, for example, the PSZ film on the
Si.sub.3N.sub.4 film 14 is selectively removed by a CMP method.
However, when the baked PSZ film is soft and beside the PSZ film
contains a large amount of nitride, an etching selectivity between
the PSZ film and the Si.sub.3N.sub.4 film cannot be easily
obtained. Therefore, the PSZ film must be cured to some extent. In
order to transform the PSZ film 19 into a SiO.sub.2 (silica) film
191, a high-temperature heat treatment (curing) is then performed
in a water vapor atmosphere before the CMP process. This process
can be explained by the following chemical formula:
(SiH.sub.2NH).sub.n-+2nO.fwdarw.nSiO.sub.2+nNH.sub.3
More specifically, the PSZ film reacts with oxygen (O) generated by
decomposition of water vapor (H.sub.2O+O.sub.2) to produce
SiO.sub.2 and NH.sub.3 (ammonia gas), so that the PSZ film is
efficiently transformed into SiO.sub.2 (silica). At this time,
since an active area is covered with the SiN film 14, it is not
oxidized. The chemical reaction described above proceeds from the
surface side of the PSZ. It is confirmed that the PSZ film coated
on a wafer with a planar structure to a thickness of about 600 nm
can be transformed into an SiO.sub.2 film by combustion oxidation
(BOX oxidation) performed at, e.g., 850.degree. C. in a water vapor
atmosphere for about 30 minutes.
[0033] Furthermore, a heat treatment is carried out at about
850.degree. C. in an oxidizing atmosphere or an inert gas
atmosphere. The HDP film formed as a lower layer is then densified
and gases such as NH.sub.3, H.sub.2O, or the like remaining in the
SiO.sub.2 film obtained by changing the PSZ film formed as an upper
layer are discharged to perform a densifying treatment, whereby the
PSZ film is transformed into the SiO.sub.2 film 191 having a higher
density. At this time, since the active area is covered with the
SiN film 14, it is not oxidized. As the densifying process, not
only a process performed by an ordinary furnace but also rapid
thermal anneal (RTA) may be used. In the RTA, thermal treatment
performed at a higher temperature, e.g., 900.degree. C. for about
20 seconds can be used.
[0034] In the heating step, the heat treatment cannot be carried
out at a higher temperature than 850.degree. C. for a long time.
This is because an oxidant is diffused into edges of the tunnel
oxide film to form a wedge-shaped oxide film called bird's beak.
More specifically, densification of the PSZ film is limited because
an operating temperature is limited, and an etching rate which is
almost equal to that of a thermal oxide film or an HDP film cannot
be realized at present.
[0035] As described above, after the PSZ film is transformed into
the SiO.sub.2 (silica) film, planarization is performed by a CMP
method. When a CMP polishing agent (slurry) containing colloidal
silica as a base is used, 50 or more can be realized as an etching
selectivity between the PSZ film and the SiN film 14.
[0036] As shown in FIG. 4G, an etching back process is performed
under a condition under which the filled PSZ film can be completely
removed. An etching selectivity between the HDP film and the PSZ
film is desirably 2.5 or more. At this time, the HDP film on the
floating gate side wall may be slightly left due to a difference
between the etching rates of the HDP film and the PSZ film, but it
may not pose any problem. However, it is difficult to control the
level position of STI while removing the remaining HDP film on the
floating gate side wall.
[0037] That is, since the level position of STI filling at a width
of 90 nm is close to the tunnel oxide film 11, the level position
is already lower than a desired level position of STI. Furthermore,
if protection from the chemical from the tunnel film edges is also
considered, STI filling at the desired level position cannot be
easily realized by only the HDP film serving as the first
layer.
[0038] Therefore, as shown in FIG. 4G, after the silica film 191 is
removed by wet etching to form a second recessed portion 20, as
shown in FIG. 4H, a second HDP film 21 is deposited by an HDP-CVD
method. Thereafter, as shown in FIG. 4I, a step coverage on the
surface is planarized by a CMP method using the SiN film 14 as a
stopper, and then a heat treatment is carried out at about
850.degree. C. in an inert gas atmosphere for one hour. As a
result, the HDP films 18 and 21 are densified to be HDP films 182
and 211, respectively, and the STI structure is uniformly filled
with these HDP films.
[0039] As shown in FIG. 4J, the HDP film 211 is etched back by a
hydrogen-fluoride-based (HF) chemical solution to lower the filling
level to a desired level. Thereafter, as shown in FIG. 4K, the SiN
film 14 is removed by a hot phosphoric acid. As a result, good
planarity and preferable level controllability of the surface of
the filled HDP film in the STI structure can be provided to realize
a desired STI shape which suppresses a variation in a coupling
ratio.
[0040] Thereafter, as shown in FIG. 4L, the ONO film 22, the
control gate electrode 23, and the interlayer insulating film 24
are formed. Although the subsequent steps are not shown,
continuously, contacts, wiring layers, a passivation film, pads,
and the like are provided to complete an NAND flash memory.
[0041] As is apparent from the above explanation, in the first
embodiment, as shown in FIGS. 4F and 4G, after planarization is
performed by using the PSZ film as a sacrificial film, the PSZ film
is selectively removed to make the aspect ratio more moderate than
the aspect ratio of the trench 17. When the silica film 191
transformed from the PSZ film is selectively removed, the
peripheral HDP film 18, i.e., a part of the HDP film 18 is
isotropically etched to increase the opening of the first recessed
portion 181, thereby forming the second recessed portion 20. As a
result, the aspect ratio is further improved. As shown in FIG. 4H,
the second HDP film 21 is formed, and then the surface of the HDP
film 21 is planarized again outside and above the STI. Therefore,
the STI filling material surface can be planarized with good
controllability.
[0042] A process for manufacturing an STI structure of 70-nm
generation will be described below. In the 90-nm generation
described above, the level of the first HDP film on the STI bottom
is higher than that of the interface of the tunnel insulating film
11. However, in the STI structure having a width of 70 nm or less,
as shown in FIG. 4M, the level of the first HDP film is generally
lower than that of the interface of the tunnel oxide film 11.
[0043] Furthermore, as described in FIGS. 4D-4F, a coating film 19
is formed and transformed into a silica film 191 by a densifying
process, and the silica film 191 is planarized by the CMP method or
the like. Thereafter, in order to control the level of the filled
film in the STI trench, wet etching is performed.
[0044] In this case, the PSZ film used in filling may be left
without being completely removed in wet etching. More specifically,
as shown in FIG. 4N, the silica film 191 transformed from the PSZ
film is partially left. Thereafter, as shown in FIG. 4O, the second
HDP film 21 is filled in the STI to realize a structure in which
the silica film 191 is included in the HDP film.
[0045] According to the manufacturing method described above,
filling of the HDP film can be realized for an NAND-STI structure
of 90-70-nm-width generation or later. A drawback such as a wet
etching rate difference caused by using different materials in
uncontrollable adjustment of an STI filling level can be
eliminated. Therefore, a production yield can be considerably
increased.
[0046] A second embodiment will be described below. In the first
embodiment, the PSZ film is used as the coating type insulating
film. However, a polymer material such as a photoresist film or a
material which is changed into an inorganic material after a
hardening process by curing can be used. The same reference
numerals as in the first embodiment denote the same parts in the
second embodiment.
[0047] More specifically, when a coating film is formed as shown in
FIG. 4E, a photoresist film is used for the STI structure of 90-nm
generation shown in FIG. 4D as a coating material. After the
photoresist film is coated, a baking process at 120.degree. C. for
about 30 seconds is performed. In this manner, a solvent remaining
in the photoresist film is vaporized to make it possible to harden
the film, or the film is polymerized by generating cross-linkage by
light irradiation to make it possible to harden the film.
[0048] As in FIG. 4F, surface polishing is carried out by a CMP
method using an SiN film 14 as a stopper. Thereafter, ashing is
performed at 150.degree. C. for 30 seconds in an O.sub.2 atmosphere
to remove a photoresist film partially filled in the STI.
Furthermore, the resultant structure is cleaned by oxidizing acid
treatment using a sulfuric acid or the like to remove residue.
[0049] As a result, a structure as shown in FIG. 5A is obtained
although an opening 30 is narrower than that in FIG. 4G. When an
aspect ratio which is almost equal to that of the opening 30 is
used, an HDP film can be filled. For this reason, as shown in FIG.
5B, an HDP film 21 is filled. The subsequent steps are the same as
those in the steps subsequent to the step in FIG. 4H in the first
embodiment. Finally, a structure shown in FIG. 4L is provided.
[0050] This method can be similarly applied to an STI structure of
70-nm generation. More specifically, as shown in FIGS. 4M and 4N,
even though the level position of the STI bottom is lower than the
interface of the tunnel insulating film 11, similarly, a material
such as a photoresist is coated, and a baking process and a
planarizing process by a CMP method are performed. Furthermore, the
ashing process and the cleaning process using a sulfuric acid or
the like are performed. At this time, since the HDP film 18 is
densified by the curing process, dissolution caused by an acid
rarely occurs. Therefore, as shown in FIG. 5C, the photoresist film
can be completely removed by the acid treatment.
[0051] In this case, since the aspect ratio of an opening 31
increases, the second HDP film 21 cannot be easily filled.
Therefore, as shown in FIG. 5D, the opening is etched by an RIE
method or the like to increase the opening, thereby forming a
structure of a bowl-shaped STI bottom. In an opening 32 obtained in
this manner, the second HDP film 21 can be filled. For this reason,
as in the case shown in FIG. 5B, an STI structure in which the
second HDP film 21 is filled can be obtained.
[0052] The subsequent steps are the same as the steps subsequent to
the step in FIG. 4H in the first embodiment. Finally, a structure
shown in FIG. 4L can be formed. A structure in which a coating film
is included in the HDP film filled in the STI as shown in the case
of FIG. 4O can be similarly obtained. At this time, as the coating
film, a film which is changed into an inorganic material free from
carbon after the hardening process by curing is desirably used.
[0053] As described in the first embodiment or the second
embodiment, the PSZ film (silica film) or the inorganic material
film included in the HDP film filled in the STI acts as a buffer
film which moderates stress in the STI to make it possible to
suppress drawbacks such as cracks or film peeling.
[0054] A third embodiment will be described below. The same steps
as in the first embodiment will be omitted, and only characteristic
steps will be described below. The same reference numerals as in
the first embodiment denote the same parts in the third embodiment.
In FIGS. 4F and 4G, the coated PSZ film 19 is transformed into a
silica film 191 by applying a hardening process to the PSZ film 19.
Thereafter the silica film 191 is removed by wet etching.
[0055] In this embodiment, as shown in FIGS. 6A to 6C, after the
PSZ film 19 is deposited and transformed into the silica film 191
by the heat treatment, the silica film 191 is directly etched back
by a dry process such as an RIE method or the like to a level
position where the silica film 191 is completely removed.
Thereafter, as shown in FIG. 4H, a second HDP film 21 is provided.
In this manner, the steps of planarization and wet etching in FIGS.
4F and 4G can be omitted.
[0056] Furthermore, a fourth embodiment will be described below.
The same steps as in the first embodiment will be omitted, and only
characteristic steps will be described below. The same reference
numerals as in the first embodiment denote the same parts in the
fourth embodiment. More specifically, as shown in FIG. 4D in the
first embodiment, after the HDP film 18 is deposited, the CMP step
is directly carried out without performing the coating step of the
PSZ film or the like as it is as shown in FIG. 7A in the fourth
embodiment.
[0057] At this time, as a CMP polishing agent (slurry), a
colloidal-silica-based agent containing a small amount of additive
such as sodium (Na) is selected. When this CMP process is
performed, as shown in FIG. 7A, a slurry 41 is inserted into an
incomplete filling trench 40 of the HDP film and remains
therein.
[0058] However, since the slurry 41 is provided by single particles
containing hydrated silica as a main component, it can be easily
dissolved by a buffered hydrofluoric acid. At this time, a ratio of
the etching rate of the slurry 41 to the etching rate of the HDP
film around the trench is about 5 or more because the slurry is
granular and has a wide etching area and because the film quality
of the HDP film is closer to the film quality of a thermal oxide
film than that of the slurry. In addition, since a small amount of
additive is selected as the additive such as Na, as shown in FIG.
7B, the additive can be removed by water washing. As a result, a
structure having a second recessed portion 20 as shown in FIG. 7C
is provided. The resultant aspect ratio is more moderate than the
aspect ratio of the recessed portion in the HDP film. Since the
subsequent steps are the same as those in the first embodiment, a
desired STI structure as shown in FIG. 4K is obtained.
[0059] A case in which the slurry 41 is allowed to remain in the
incomplete trench 40 of the HDP film will be described below. More
specifically, after the additive in the slurry is removed by an
appropriate acid or water washing, as shown in FIG. 4H, a second
HDP film 21 is formed on the structure in which the HDP film and
the residue are filled. In a process in which subsequent annealing
to densify these oxide films is performed, the particles of the
slurry residue are melted to form a porous region. As a result, as
shown in FIG. 7D, like the silica film in FIG. 4O, a filling
structure of the HDP film 21 including a crystallized porous film
42 is obtained.
[0060] The characteristic features of the structure described above
will be described below. More specifically, when a PSZ coating film
having a large thermal contraction is used, for example, when a PSZ
film remains as a film included in the STI, the PSZ film is not a
porous film after a heat treatment to generate tensile stress to
the silicon substrate and the floating gate portion which are
adjacent to the PSZ. As a result, dislocation and point defects are
caused in the silicon film. In the worst case, the filled film in
the STI may be cleaved in the vertical direction. In the first
embodiment (FIG. 4O), the cleavage does not occur because the
region of the PSZ film (silica film) is narrow. However, with
scaling down of the STI structure, the occupied area of the coating
film in the STI increases to make these problems serious.
[0061] However, the porous region formed by using the slurry as a
material acts as a buffer film which moderates the internal stress
in the STI to make it possible to suppress drawbacks such as
defects and cleavage. The coating solution is a coating solution
for forming a silica-based coating film or the like, and is not
limited to PSZ.
[0062] The aspect of the embodiments are as follows.
[0063] (1) The coating solution is a coating solution for forming a
silica-based coating film or the like, and is not limited to
PSZ.
[0064] (2) Heat treatment is carried out in an oxidizing atmosphere
or an inert gas atmosphere to perform a process of densifying the
HDP film formed as the lower layer and a process of discharging
NH.sub.3, H.sub.2O, and the like remaining in the SiO.sub.2 film
obtained by changing the PSZ film formed as the upper layer, so
that these films are changed into SiO.sub.2 films having higher
densities.
[0065] (3) After the coating film is transformed into the second
insulating film, the second insulating film is etched back by an
RIE method. Thereafter, a second HDP film is formed.
[0066] (4) As the coating film, a material such as a photoresist
film which is changed into an inorganic material after a hardening
process by curing is coated and then applied with a baking
process.
[0067] (5) The filled photoresist film is removed by an ashing
process.
[0068] (6) The level of the planarized surface is higher than the
level position of the tunnel oxide film.
[0069] (7) In 70-nm-width generation or later, the level of the
polanarized surface is lower than the level position of the tunnel
oxide film.
[0070] (8) The first and second HDP films are formed and applied
with heat treatment in an inert gas atmosphere to densify the HDP
films.
[0071] (9) The second HDP film is filled in the STI such that the
silica film is partially left, thereby obtaining a structure in
which the silica film is included in the HDP film.
[0072] (10) After additive in the slurry is removed by an acid or
water washing, the second HDP film is formed on a structure in
which the HDP film and the residue are buried. In the subsequent
heat treatment process to densify these oxide films, a filling
structure of the HDP film including a porous film which is formed
such that the particles of slurry residue are melted and then
crystallized is obtained.
[0073] (11) At least a part of the porous inorganic film included
in the HDP film acts as a buffer film which moderates the internal
stress of the STI.
[0074] (12) Water washing is performed before the slurry remaining
in the recessed portion is removed by a chemical solution to remove
water-soluble impurities.
[0075] (13) The porous film is formed by melting the particles of
the slurry residue.
[0076] (14) The method described above is applied to STI filling of
a flash memory or a CMOS logic product.
[0077] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *