U.S. patent application number 12/185389 was filed with the patent office on 2010-02-04 for method of fabricating a semiconductor device and semiconductor device.
This patent application is currently assigned to INFINEON TECHNOLOGIES AG. Invention is credited to Gottfried Beer, Irmgard Escher-Poeppel.
Application Number | 20100025848 12/185389 |
Document ID | / |
Family ID | 41528312 |
Filed Date | 2010-02-04 |
United States Patent
Application |
20100025848 |
Kind Code |
A1 |
Beer; Gottfried ; et
al. |
February 4, 2010 |
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR
DEVICE
Abstract
A method of fabricating a semiconductor device and semiconductor
device is provided. The method provides a first layer. The first
layer includes through-holes. At least one semiconductor chip is
provided. The semiconductor chip includes contact elements. The
semiconductor chip is placed onto the first layer with the contact
elements being aligned with the through-holes. An encapsulant
material is applied over the semiconductor chip.
Inventors: |
Beer; Gottfried;
(Nittendorf, DE) ; Escher-Poeppel; Irmgard;
(Regensburg, DE) |
Correspondence
Address: |
DICKE, BILLIG & CZAJA
FIFTH STREET TOWERS, 100 SOUTH FIFTH STREET, SUITE 2250
MINNEAPOLIS
MN
55402
US
|
Assignee: |
INFINEON TECHNOLOGIES AG
Neubiberg
DE
|
Family ID: |
41528312 |
Appl. No.: |
12/185389 |
Filed: |
August 4, 2008 |
Current U.S.
Class: |
257/738 ;
257/774; 257/787; 257/E21.001; 257/E23.116; 257/E23.141; 438/106;
438/110; 438/127 |
Current CPC
Class: |
H01L 2924/01029
20130101; H01L 21/561 20130101; H01L 2224/97 20130101; H01L
2924/1461 20130101; H01L 23/49827 20130101; H01L 24/96 20130101;
H01L 2224/97 20130101; H01L 2924/01027 20130101; H01L 2924/01005
20130101; H01L 2924/14 20130101; H01L 2224/12105 20130101; H01L
23/3128 20130101; H01L 24/19 20130101; H01L 2924/12044 20130101;
H01L 23/49816 20130101; H01L 2924/01075 20130101; H01L 2924/1461
20130101; H01L 2924/15311 20130101; H01L 2224/97 20130101; H01L
2924/01079 20130101; H01L 2224/04105 20130101; H01L 2924/01078
20130101; H01L 2224/0401 20130101; H01L 2924/01006 20130101; H01L
2224/20 20130101; H01L 2924/00 20130101; H01L 2224/82 20130101;
H01L 2924/01082 20130101; H01L 2924/15311 20130101; H01L 2924/01013
20130101; H01L 24/97 20130101; H01L 2924/01047 20130101; H01L
2924/1815 20130101; H01L 2924/014 20130101 |
Class at
Publication: |
257/738 ;
438/106; 438/110; 438/127; 257/774; 257/787; 257/E21.001;
257/E23.141; 257/E23.116 |
International
Class: |
H01L 23/52 20060101
H01L023/52; H01L 21/00 20060101 H01L021/00; H01L 23/28 20060101
H01L023/28 |
Claims
1. A method of fabricating a semiconductor device, comprising:
providing a first layer, the first layer comprising through-holes;
providing at least one semiconductor chip, the semiconductor chip
defining a first surface comprising contact elements and a second
surface opposite to the first surface of the semiconductor chip;
placing the semiconductor chip onto the first layer with the first
surface facing the first layer; and applying an encapsulant
material over the second surface of the semiconductor chip.
2. The method of claim 1, further comprising: placing the
semiconductor chip onto the first layer with the contact elements
being aligned with the through-holes.
3. The method of claim 1, further comprising forming the
through-holes by at least one of stamping, laser drilling, and
selective etching the first layer.
4. The method of claim 1, wherein the first layer is an insulating
layer.
5. The method of claim 1, wherein the first layer is comprised of a
first insulation layer facing the semiconductor chip and a metal
layer facing away from the semiconductor chip.
6. The method of claim 1, further comprising attaching the first
layer to a second layer.
7. The method of claim 6, further comprising separating the second
layer from the first layer after placing the semiconductor chip
onto the first layer.
8. The method of claim 1, further comprising fabricating an
encapsulated structure having a shape of a wafer.
9. The method of claim 1, further comprising fabricating an
encapsulated structure having a rectangular shape.
10. A method of fabricating a semiconductor device, comprising:
providing a first layer, the first layer comprising through-holes;
providing at least one semiconductor chip, the semiconductor chip
comprising contact elements; placing the semiconductor chip onto
the first layer with the contact elements being aligned with the
through-holes; and applying an encapsulant material over the
semiconductor chip.
11. The method of claim 10, further comprising the semiconductor
chip defining a first surface comprising the contact elements and a
second surface opposite to the first surface, and placing the
semiconductor chip onto the first layer with the first surface
facing the first layer.
12. The method of claim 10, further comprising forming the
through-holes by at least one of stamping, laser drilling, or
selective etching the first layer.
13. The method of claim 10, wherein the first layer is an
insulating layer.
14. The method of claim 10, wherein the first layer is comprised of
a first insulation layer facing the semiconductor chip and a metal
layer facing away from the semiconductor chip.
15. The method of claim 10, further comprising attaching the first
layer to a second layer.
16. The method of claim 15, further comprising separating the
second layer from the first layer after placing the semiconductor
chip onto the first layer.
17. The method of claim 10, further comprising fabricating an
encapsulated structure having a shape of a wafer.
18. The method of claim 10, further comprising fabricating an
encapsulated structure having a rectangular shape.
19. A method of fabricating a plurality of semiconductor devices,
comprising: providing a first layer, the first layer comprising
through-holes; providing a plurality of semiconductor chips, each
one of the semiconductor chips defining a first surface comprising
contact elements and a second surface opposite to the first surface
of the semiconductor chips and side surfaces between the first and
second surfaces, respectively; placing the semiconductor chips onto
the first layer with the first surface facing the first layer;
applying an encapsulant material over at least the side surfaces of
the semiconductor chips; applying a conducting layer over the first
layer and the contact elements, the conducting layer comprising
conducting areas, each one of the conducting areas connected with
one of the contact elements, respectively; and dividing the
resulting structure into semiconductor devices.
20. The method of claim 19, further comprising placing the
semiconductor chips onto the first layer with the contact elements
being aligned with the through-holes.
21. The method of claim 19, further comprising forming the
through-holes by at least one of stamping, laser drilling, or
selective etching the first layer.
22. The method of claim 19, wherein the first layer is an
insulating layer.
23. The method of claim 19, wherein the first layer is comprised of
a first insulation layer facing the semiconductor chips and a metal
layer facing away from the semiconductor chips.
24. The method of claim 19, further comprising attaching the first
layer to a second layer.
25. The method of claim 24, further comprising separating the
second layer from the first layer after placing the semiconductor
chips onto the first layer.
26. The method of claim 19, further comprising fabricating an
encapsulated structure having a shape of a wafer.
27. The method of claim 19, further comprising fabricating an
encapsulated structure having a rectangular shape.
28. A semiconductor device, comprising: at least one semiconductor
chip comprising contact elements on a first surface of the chip; a
encapsulant material covering at least partly the semiconductor
chip; a dielectric layer situated on the first surface of the chip,
a dielectric layer situated on the first surface of the chip, the
dielectric layer comprising vias aligned with the contact elements;
and a layer of a conductive material covering a surface of the
dielectric layer above the vias, the conductive material produced
by applying conductive ink to the surface and one or more of
drying, curing and sintering the conductive ink.
29. The semiconductor device of claim 28, further comprising: a
conducting layer comprising contact areas, each one of the contact
areas connected with the vias, respectively.
30. The semiconductor device of claim 29, further comprising: a
solder resist layer applied above the conducting layer, the solder
resist layer comprising openings above the contact areas.
31. The semiconductor device of claim 30, further comprising:
solder balls applied above the openings of the solder resist layer,
the solder balls being electrically connected to the contact areas,
respectively.
32. A semiconductor device, comprising: at least one semiconductor
chip comprising contact elements on a first surface of the
semiconductor chip; an encapsulant material covering at least
partly the semiconductor chip; a dielectric layer situated on the
first surface of the semiconductor chip, the dielectric layer
comprising vias aligned with the contact elements; and a layer of a
conductive material covering a surface of the dielectric layer
above the vias, the conductive material being comprised of
conductive particles embedded in a matrix.
33. The semiconductor device of claim 32, further comprising: a
conducting layer comprising contact areas, each one of the contact
areas connected with one of the vias, respectively.
34. The semiconductor device of claim 33, further comprising: a
solder resist layer applied above the conducting layer, the solder
resist layer comprising openings above the contact areas.
35. The semiconductor device of claim 34, further comprising:
solder balls applied above the openings of the solder resist layer,
the solder balls being electrically connected to the contact areas,
respectively.
Description
BACKGROUND
[0001] The present invention relates to a method of fabricating a
semiconductor device and a semiconductor device.
[0002] Semiconductor chips include contact pads of contact elements
on one or more of their surfaces. When fabricating a semiconductor
device, in one embodiment when housing the semiconductor chip in a
semiconductor chip package, the contact pads of the semiconductor
chip have to be connected to external contact elements of the
semiconductor chip package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The accompanying drawings are included to provide a further
understanding of embodiments and are incorporated in and constitute
a part of this specification. The drawings illustrate embodiments
and together with the description serve to explain principles of
embodiments. Other embodiments and many of the intended advantages
of embodiments will be readily appreciated as they become better
understood by reference to the following detailed description. The
elements of the drawings are not necessarily to scale relative to
each other. Like reference numerals designate corresponding similar
parts.
[0004] FIG. 1 illustrates a flow diagram of a method of fabricating
a semiconductor device according to one embodiment.
[0005] FIGS. 2A-D illustrate schematic cross-sectional
representations of intermediate products and a semiconductor device
for illustrating one embodiment of a method of fabricating a
semiconductor device.
[0006] FIG. 3 illustrates a flow diagram of a method of fabricating
a semiconductor device according to one embodiment.
[0007] FIGS. 4A-D illustrate schematic cross-sectional
representations of intermediate products and a semiconductor device
for illustrating one embodiment of a method of fabricating a
semiconductor device.
[0008] FIGS. 5A-M illustrate schematic cross-sectional
representations of intermediate products and a semiconductor device
for illustrating one embodiment of a method of fabricating a
semiconductor device.
[0009] FIG. 6 illustrates a flow diagram of a method of fabricating
a plurality of semiconductor devices according to one
embodiment.
[0010] FIGS. 7A-F illustrate schematic cross-sectional
representations of intermediate products and semiconductor devices
for illustrating one embodiment of a method of fabricating a
plurality of semiconductor devices.
[0011] FIG. 8 illustrates a schematic cross-sectional
representation of a semiconductor devices according to one
embodiment.
[0012] FIG. 9 illustrates a schematic cross-sectional
representation of a semiconductor device according to one
embodiment.
[0013] FIG. 10 illustrates a schematic cross-sectional
representation of a semiconductor device according to one
embodiment.
DETAILED DESCRIPTION
[0014] In the following Detailed Description, reference is made to
the accompanying drawings, which form a part hereof, and in which
is shown by way of illustration specific embodiments in which the
invention may be practiced. In this regard, directional
terminology, such as "top," "bottom," "front," "back," "leading,"
"trailing," etc., is used with reference to the orientation of the
Figure(s) being described. Because components of embodiments can be
positioned in a number of different orientations, the directional
terminology is used for purposes of illustration and is in no way
limiting. It is to be understood that other embodiments may be
utilized and structural or logical changes may be made without
departing from the scope of the present invention. The following
detailed description, therefore, is not to be taken in a limiting
sense, and the scope of the present invention is defined by the
appended claims.
[0015] It is to be understood that the features of the various
exemplary embodiments described herein may be combined with each
other, unless specifically noted otherwise.
[0016] The aspects and embodiments are now described with reference
to the drawings, wherein like reference numerals are generally
utilized to refer to like elements throughout. In the following
description, for purposes of explanation, numerous specific details
are set forth in order to provide a thorough understanding of one
or more aspects of the embodiments. It may be evident, however, to
one skilled in the art that one or more aspects of the embodiments
may be practiced with a lesser degree of the specific details. In
other embodiments, known structures and elements are illustrated in
schematic form in order to facilitate describing one or more
aspects of the embodiments. It is to be understood that other
embodiments may be utilized and structural or logical changes may
be made without departing from the scope of the present invention.
It should be noted further that the drawings are not to scale or
not necessarily to scale.
[0017] In addition, while a particular feature or aspect of one
embodiment may be disclosed with respect to only one of several
implementations, such feature or aspect may be combined with one or
more other features or aspects of the other implementations as may
be desired and advantageous for any given or particular
application. Furthermore, to the extent that the terms "include",
"have", "with" or other variants thereof are used in either the
detailed description or the claims, such terms are intended to be
inclusive in a manner similar to the term "comprise". The terms
"coupled" and "connected", along with derivatives may be used. It
should be understood that these terms may be used to indicate that
two elements co-operate or interact with each other regardless
whether they are in direct physical or electrical contact, or they
are not in direct contact with each other. Also, the term
"exemplary" is merely meant as an example, rather than the best or
optimal. The following detailed description, therefore, is not to
be taken in a limiting sense, and the scope of the present
invention is defined by the appended claims.
[0018] The embodiments of a method of fabricating a semiconductor
device and the embodiments of a semiconductor device may use
various types of semiconductor chips or semiconductor substrates,
among them logic integrated circuits, analog integrated circuits,
mixed signal integrated circuits, sensor circuits, MEMS
(Micro-Electro-Mechanical Systems), power integrated circuits,
chips with integrated passives, discrete passives and so on. In
general the term "semiconductor chip" as used in this application
can have different meanings one of which is a semiconductor die or
semiconductor substrate including an electrical circuit.
[0019] In several embodiments layers or layer stacks are applied to
one another or materials are applied or deposited onto layers. It
should be appreciated that any such terms as "applied" or
"deposited" are meant to cover literally all kinds and techniques
of applying layer onto each other. In one embodiment, they are
meant to cover techniques in which layers are applied at once as a
whole, like, for example, laminating techniques, as well as
techniques in which layers are deposited in a sequential manner,
like, for example, sputtering, plating, molding, chemical vapor
deposition (CVD) and so on.
[0020] The semiconductor chips may include contact elements or
contact pads on one or more of their outer surfaces wherein the
contact elements serve for electrically contacting the
semiconductor chips. The contact elements may be made from any
electrically conducting material, e.g., from a metal as aluminum,
gold, or copper, for example, or a metal alloy, or an electrically
conducting organic material, or an electrically conducting
semiconductor material.
[0021] The semiconductor chips may become covered with an
encapsulating material. The encapsulating material can be any
electrically insulating material like, for example, any kind of
molding material, any kind of epoxy material, or any kind of resin
material. In special cases it could be advantageous to use a
conductive encapsulant material. In the process of covering the
semiconductor chips or dies with the encapsulating material,
fan-out embedded dies can be fabricated. The fan-out embedded dies
can be arranged in an array having the form e.g., of a wafer and
will thus be called a "re-configured wafer" further below. However,
it should be appreciated that the fan-out embedded die array is not
limited to the form and shape of a wafer but can have any size and
shape and any suitable array of semiconductor chips embedded
therein.
[0022] Referring to FIG. 1, there is illustrated a flow diagram of
a method of fabricating a semiconductor device according to one
embodiment. The method includes providing a first layer, the first
layer including through-holes (s1), providing at least one
semiconductor chip, the semiconductor chip defining a first surface
including contact elements and a second surface opposite to the
first surface of the semiconductor chip (s2), placing the
semiconductor chip onto the first layer with the first surface
facing the first layer (s3), and applying an encapsulant material
over the second surface of the semiconductor chip (s4).
[0023] According to one embodiment of the method of fabricating a
semiconductor device, the method further includes placing the
semiconductor chip onto the first layer with the contact elements
being aligned with the through-holes.
[0024] According to one embodiment of the method of fabricating a
semiconductor device, the through-holes are formed by at least one
of stamping, laser drilling, or selectively etching the first
layer.
[0025] According to one embodiment of the method of fabricating a
semiconductor device, the first layer is an insulation layer.
[0026] According to one embodiment of the method of fabricating a
semiconductor device, the first layer is comprised of a first
insulation layer facing the semiconductor chip and a metal layer
facing away from the semiconductor chip. The metal layer may
include the function of a seed layer for a later metallization
process.
[0027] According to one embodiment of the method of fabricating a
semiconductor device, the first layer is attached to a second
layer. According to a further embodiment thereof, the second layer
is separated from the first layer after placing the semiconductor
chip onto the first layer and the encapsulation.
[0028] According to one embodiment of the method of fabricating a
semiconductor device, the method further includes applying a
conducting layer over the first layer and the contact elements
wherein the conducting layer may include conducting areas which are
aligned with the through-holes and which can be electrically
connected with the contact elements of the semiconductor chips by
filling electrically conductive material into the through-holes.
The conducting layer may include the function of a redistribution
layer for redistributing the arrangement of the contact elements
over a larger area.
[0029] According to one embodiment of the method of fabricating a
semiconductor device, the method further includes applying solder
balls and electrically connecting the solder balls with the contact
elements of the semiconductor chip. According to one embodiment
thereof, the method further includes applying a solder resist
layer, the solder resist layer including openings wherein the
solder balls are applied above the openings of the solder resist
layer.
[0030] Referring to FIGS. 2A-D, there are illustrated
cross-sectional representations of intermediate products and a
semiconductor device for illustrating one embodiment of a method of
fabricating a semiconductor device corresponding to the embodiment
of FIG. 1. FIG. 2A illustrates a cross-sectional representation of
a first layer 1 wherein the first layer 1 includes through-holes
1A. The first layer 1 can be made of a dielectric, insulating
material which can, for example, be comprised of a foil based on an
acrylate or which can also be an epoxy-bistage foil. The first
layer 1 can, for example, also be made of a prepreg
(preimpregnated) foil such as that known from conventional
substrate technology. The first layer 1, for example, can be
comprised of a photo-structurable prepreg which can be etched after
lithographical exposure. It is also possible that the first layer 1
could be ablated or structured with a laser beam. The first layer 1
can also include an additive, which releases electrically
conducting material or which releases a catalytic layer for plating
upon irradiation. The first layer 1 can also have adhesion
properties in order to fix semiconductor chips which are to be
applied on its surface. If, however, the first layer 1 does not
have itself sufficient adhesion force at its surface, a third layer
(not illustrated) including an adhesion promoter can be applied to
the surface of the first layer 1.
[0031] The through-holes 1A can be produced, for example, by one of
stamping, laser drilling, or selective etching of the first layer
1.
[0032] FIG. 2B illustrates a cross-sectional representation of a
semiconductor chip 2 including a first surface having contact
elements or contact pads 2A thereon, and a second surface opposite
to the first surface. The semiconductor chips to be used here may
be of extremely different types and may include integrated
electrical or electro-optical circuits. The semiconductor chips may
be, for example, configured as power transistors, power diodes,
control circuits, micro-processors or micro-electro-mechanical
components or discrete passives. The semiconductor chips need not
necessarily be manufactured from specific semiconductor material
and, furthermore, may contain inorganic and/or organic materials
that are not semiconductors, such as, for example, insulators,
plastics or metals.
[0033] FIG. 2C illustrates an intermediate product after applying
the semiconductor chip 2 to the first layer 1. The semiconductor
chip 2 is placed onto the first layer 1 with the first surface of
the semiconductor chip 2 facing the first layer 1. The
semiconductor chip 2 can be placed in such a way onto the first
layer 1 that the contact elements 2A of the semiconductor chip 2
are aligned with the through-holes 1A of the first layer 1. The
semiconductor chip 2 can be placed by different means onto the
first layer 1 wherein, for example, in case of placing a plurality
of semiconductor chips 2 onto the first layer 1, a pick-and-place
machine can be used. A pattern recognition of the through-holes can
be implemented for placing the semiconductor chip in the correct
position.
[0034] FIG. 2D illustrates a cross-sectional representation of a
semiconductor device after applying an encapsulant material 3 over
the semiconductor chip 2. The encapsulant material 3 can, for
example, include a molding material wherein the molding technique
can be, for example, compression molding. The encapsulant material
can also be applied by other process techniques like, for example,
screen printing. The encapsulant materials include, for example,
aliphatic and aromatic polymers including thermoplastic and
thermoset type polymers and blends of these and also other various
types of polymers.
[0035] Typical values of the thicknesses of the layers may be as
follows. The thickness of the first layer 1 typically ranges from 5
.mu.m to 150 .mu.m, whereas the thickness of the semiconductor chip
2 typically ranges from 50 .mu.m to 450 .mu.m, and the thickness of
the encapsulant material typically ranges from 300 .mu.m to 700
.mu.m.
[0036] Referring to FIG. 3, there is illustrated a flow diagram of
a method of fabricating a semiconductor device according to one
embodiment. The method includes providing a first layer, the first
layer including through-holes (s1), providing at least one
semiconductor chip, the semiconductor chip including contact
elements (s2), placing the semiconductor chip onto the first layer
with the contact elements being aligned with the through-holes
(s3), and applying an encapsulant material over the semiconductor
chip.
[0037] According to one embodiment of the method of fabricating a
semiconductor device, the method further includes the semiconductor
chip defining a first surface including the contact elements and a
second surface opposite to the first surface, and placing the
semiconductor chip onto the first layer with the first surface
facing the first layer.
[0038] There can be provided further embodiments of the method of
fabricating a semiconductor device corresponding with the
embodiment as described above in connection with the semiconductor
device as depicted in FIGS. 1 and 2.
[0039] Referring to FIGS. 4A-D, there are illustrated
cross-sectional representations of intermediate products and a
semiconductor device for illustrating one embodiment of a method of
fabricating a semiconductor device corresponding to the embodiment
of FIG. 3. FIG. 4A illustrates a cross-sectional representation of
a first layer 1 wherein the first layer 1 includes through-holes
1A. The first layer 1 can be made of a dielectric, insulating
material which can, for example, be comprised of a foil based on an
acrylate or which can also be an epoxy-B-stage foil. The first
layer 1 can, for example, also be made of a prepreg
(preimpregnated) foil such as that known from conventional
substrate technology. The first layer 1, for example, can be
comprised of a photo structurable prepreg which can be etched after
lithographical exposure. It is also possible that the first layer 1
could be ablated or structured with a laser beam. The first layer 1
can also include an additive, which releases electrically
conducting material or which releases a catalytic layer for plating
upon irradiation. The first layer 1 can also have adhesion
properties in order to fix semiconductor chips which are to be
applied on its surface. If, however, the first layer does not have
itself sufficient adhesion force at its surface, a third layer (not
illustrated) including an adhesion promoter can be applied to the
surface of the first layer 1.
[0040] The through-holes 1A can be produced, for example, by
stamping, laser drilling, or etching of the first layer 1.
[0041] FIG. 4B illustrates a cross-sectional representation of a
semiconductor chip including a first surface having contact
elements or contact pads 2A thereon, and a second surface opposite
to the first surface. The semiconductor chips to be used here may
be of extremely different types and may include for integrated
electrical or electro-optical circuits. The semiconductor chips may
be, for example, configured as power transistors, power diodes,
control circuits, micro-processors or micro-electro-mechanical
components. The semiconductor chips need not be manufactured from
specific semiconductor material and, furthermore, may contain
inorganic and/or organic materials that are not semiconductors,
such as, for example, insulators, plastics or metals.
[0042] FIG. 4C illustrates an intermediate product after applying
the semiconductor chip 2 to the first layer 1. The semiconductor
chip 2 is placed onto the first layer 1 with the first surface of
the semiconductor chip 2 facing the first layer 1. The
semiconductor chip 2 can be placed in such a way onto the first
layer 1 that the contact elements 2A of the semiconductor chip 2
are aligned with the through-holes 1A of the first layer 1. The
semiconductor chip 2 can be placed by different means onto the
first layer 1 wherein, for example, in case of placing a plurality
of semiconductor chips 2 onto the first layer 1, a pick-and-place
machine can be used.
[0043] FIG. 4D illustrates a cross-sectional representation of a
semiconductor device after applying an encapsulant material 3 over
the semiconductor chip 2. The encapsulant material 3 can, for
example, include a molding material wherein the molding technique
can be, for example, compression molding. The encapsulant material
can also be applied by other process techniques like, for example,
screen printing. The encapsulant materials include, for example,
aliphatic and aromatic polymers including thermoplastic and
thermoset type polymers and blends of these and also other various
types of polymers.
[0044] Typical values of the thicknesses of the layers may be as
follows. The thickness of the first layer 1 typically ranges from 5
.mu.m to 150 .mu.m, whereas the thickness of the semiconductor chip
2 typically ranges from 150 .mu.m to 450 .mu.m, and the thickness
of the encapsulant material typically ranges from 300 .mu.m to 700
.mu.m.
[0045] According to one embodiment of the embodiments as described
in this application, the through-holes are formed into the first
layer in a stage of the process in which the at least one
semiconductor chip has not yet been applied to the first layer.
Therefore, there are no specific restrictions in handling of the
first layer and no particular measures to be taken in order to
prevent any damages. The through-holes can therefore be easily
formed by any sort of process like, for example, stamping of the
first layer, laser drilling or laser structuring of the first
layer, selective etching of the first layer and so on. Furthermore,
a metallic layer can be grown on or deposited on the first layer
which metallic layer is to be utilized for later electro plating or
galvanic processes. The metallic layer can also be deposited onto
the first layer without any particular restrictions or measures to
be taken. A further advantage lies in the fact that the
semiconductor chips can be applied to the first layer and they can
be easily placed onto the first layer with the contact elements of
the semiconductor chips being aligned with the through-holes of the
first layer. The through-holes can be utilized for a pattern
recognition of an automated process of placing of the semiconductor
chips by using, for example, a pick-and-place-machine.
[0046] Referring to FIGS. 5A-M, there are illustrated
cross-sectional representations of intermediate products and
semiconductor devices for illustrating a method of fabricating a
semiconductor device according to one embodiment. FIG. 5A
illustrates a layer stack including a first layer 1 which may
correspond to the first layer 1 as described in the previous
embodiments, i.e. which may be fabricated of a dielectric resin. On
one surface of the first layer 1 a thin metallic layer 4 is
deposited. The metallic layer 4 serves the purpose of a seed layer
utilized to assist a metallization plating process, e.g., a
galvanic metallization process, which is performed in a later
process for the fabrication of a redistribution layer. The metallic
layer 4 can have a thickness in a range from 20 nm to 300 nm. It
can be deposited as a single layer of, for example, an element
metal like Ti or Cu or it can be deposited as a layer stack
including, for example, a 50 nm Ti layer and a Cu layer of a
thickness between 100 nm and 200 nm. The metallic layer 4 can be
produced by different ways. It, for example, can be produced by
depositing onto the surface of the first layer 1, in one embodiment
by sputtering. It is also possible to choose a specific material of
the first layer 1, the specific material containing an additive,
which releases electrically conducting material upon irradiation.
The specific material may also release upon irradiation a catalytic
starter for a subsequent plating process. It is also possible to
omit the metallic layer 4 which will be explained further below.
The layer stack as illustrated in FIG. 5A also illustrates an
auxiliary layer 5 which is applied onto the first layer 1 or the
metallic layer 4. The auxiliary layer 5 may include the form of a
transparent tape and it may serve the purpose of a protection tape
which is to be removed in a later stage.
[0047] FIG. 5B illustrates a cross sectional representation of a
further intermediate product. The intermediate product of FIG. 5B
is obtained after producing through-holes 1A into the first layer
1. The through-holes 1A can be produced by photo-structuring of the
first layer 1 by using a laser beam if the first layer 1 is made of
a photo-structurable material. If the material of the first layer 1
is not only comprised of a photo-structurable material but also
contains an additive, which releases electrically conducting
material as described above, it would be possible to generate the
through-holes 1A and at the same time to generate a thin
electrically conducting surface layer at the walls of the
through-holes 1A. The structuring of the first layer 1 by laser
irradiation can be performed e.g., by a scanned laser beam or by an
optical imaging system including a conventional (incoherent) light
source, a mask and a lens. The structuring of the first layer 1 can
also be performed by a stamping process or by a selective etching
process of the first layer 1.
[0048] FIG. 5C illustrates a cross-sectional representation of a
further intermediate product obtained after applying of a
semiconductor chip 2 to the first layer 1. The semiconductor chip 2
will be placed onto a surface of the first layer 1 which is
situated opposite to the (optional) metallic layer 4 and the
(optional) auxiliary layer 5. The semiconductor chip 2 includes
contact elements 3A and will be placed such that the contact
elements 3A are aligned with the through-holes 1A of the first
layer 1. The semiconductor chip 2 can be placed by use of a
pick-and-place-machine which can be equipped with a pattern
recognition tool using the through-holes 1A as an orientation for
the placement process. In the embodiment of FIGS. 5A-M only two
contact elements 2A per chip 2 are illustrated. However, it should
be noted that the chip 2 can have even more contact elements.
[0049] FIG. 5D illustrates a cross-sectional representation of a
further intermediate product obtained after applying an encapsulant
material 3 onto the semiconductor chip 2. The encapsulant material
can be made of any material as described in one of the previous
embodiments. The encapsulant material can be applied in such a way
onto the semiconductor chip 2 so that the semiconductor chip 2 is
embedded in the encapsulant material, in one embodiment surrounded
by the encapsulant material on all sides besides the surface on
which the contact elements 2A are provided. After applying of the
encapsulant material, a tempering or curing process is performed
for curing or hardening the encapsulant material.
[0050] FIG. 5E illustrates a cross-sectional representation of a
further intermediate product obtained after removing the auxiliary
layer 5 and filling a conductive ink 6 into the through-holes 1A.
The intermediate product is illustrated upside down with respect to
the previous drawing of FIG. 5D. The conductive ink 6 can be
comprised of, for example, any liquid medium in which electrically
conductive particles, in one embodiment microscopic particles like
nano-particles are embedded wherein e.g., silver nano-particles
could be used. The through-holes 1A could be filled each with an
amount of 3 to 40 pl per drop of conductive ink 6. The application
of the conductive ink 6 and the subsequent drying and/or curing
provides a conducting seed layer on the bottom of the through-holes
1A, i.e. on the contact elements 2A of the semiconductor chip 2 and
the side walls of the through-holes 1A. The ink-jetting can also be
performed with the help of pattern recognition on the basis of the
location of the through-holes 1A. The curing of the deposited ink
could be performed in a way that the encapsulant material 3 will be
cured or post-cured at the same time. The curing temperature should
be higher than 150.degree. C., in one embodiment higher than
200.degree. C. in order to ensure a good conductivity of the cured
conductive ink 6. After curing of the conductive ink 6 the walls of
the through-holes 1A and the contact elements 2A are covered with a
conductive material, the conductive material being comprised of
conductive particles embedded in a matrix.
[0051] In one embodiment, no metallic layer 4 is applied to the
first layer 1 when fabricating the intermediate product of FIG. 5A;
so when fabricating the intermediate product of FIG. 5E, the
conductive ink 6 is applied to the whole upper surface of the first
layer 1 including the through-holes 1A.
[0052] In FIG. 5F there is illustrated a cross-sectional
representation of a further intermediate product after application
of a resist layer 7 onto the upper surface of the metallic layer 4
and the through-holes 1A of the first layer 1. The resist layer 7
can be comprised of a dry resist or a sprayed resist which may have
a thickness of, for example, 10 .mu.m-30 .mu.m, in one embodiment
15 .mu.m. The resist layer 7 can be laminated onto the surface of
the metallic layer 4 if it is in the form of a dry resist.
[0053] FIG. 5G illustrates a cross-sectional representation of a
further intermediate product after exposing and developing the
resist layer 7. The resist layer 7, for example, can be exposed
with a laser direct imaging (LDI) process or with any other
conventional imaging method. After developing of the resist layer
7, predetermined portion of the resist layer are removed in order
to fabricate electrically conductive contact areas thereon.
[0054] FIG. 5H illustrates a cross-sectional representation of a
further intermediate product after forming contact areas 8A into
the through-holes 1A and on the regions of the metallic layer 4
which are connected with the through-holes 1A, respectively. The
contact areas 8A are intended to form part of a redistribution
layer 8 for redistributing the distribution of the contact elements
2A to a larger area. The contact areas 8A can, for example, be
fabricated by electro-plating in a strong agitated electrolyte. In
FIG. 5H there is illustrated only one contact area 8A to its full
extent, the contact area 8A being connected with the right one of
the through-holes 1A as illustrated. It is to be understood that
the other contact areas 8A may also be fabricated with the same
geometric dimensions, wherein, for example, the contact area 8A
connected with the left through-hole 1A may extend in a direction
perpendicular to the image plane. The contact areas 8A can be
produced by galvanic plating or by other means like, for example,
chemical plating or even by a screen printing process.
[0055] FIG. 5I illustrates a cross-sectional representation of a
further intermediate product after etching of the remaining
portions of the resist layer 7.
[0056] FIG. 5J illustrates a cross-sectional representation of a
further intermediate product obtained after etching of the
remaining portions of the metallic layer 4 under the remaining
portions of the resist layer 7 removed in the process before so
that the contact areas 8A of the redistribution layer 8 become
electrically separated from each other. In case of the
above-mentioned alternative embodiment in which no metallic layer
is deposited onto the first layer 1 from the beginning but instead
a conductive ink layer is applied onto the entire surface of the
first layer 1 to obtain the intermediate product of FIG. 5E, the
remaining portions of the conductive ink layer are removed between
the contact areas 8A. In the case of screen printing no seed layer
will have to be applied.
[0057] FIG. 5K illustrates a cross sectional representation of a
further intermediate product obtained after applying and
structuring of a solder resist layer 9. The solder resist layer 9
is structured so that essential or large portions of the contact
areas 8A are not covered by the solder resist layer 9.
[0058] In FIG. 5L there is illustrated a cross-sectional
representation of a further intermediate product obtained after
filling solder balls 10 into the openings of the solder resist
layer 9 so that each solder ball 10 is connected with one of the
contact areas 8A of the redistribution layer 8, respectively.
[0059] In FIG. 5M there is illustrated a cross-sectional
representation of a further intermediate product obtained after
applying further material of the solder resist in regions at the
bottom of the solder balls 10 in order to stabilize and strengthen
the fixation of the solder balls 10 within the openings of the
solder resist layer 9.
[0060] Referring to FIG. 6, there is illustrated a flow diagram of
a method of fabricating a plurality of semiconductor devices
according to one embodiment. The method includes providing a first
layer, the first layer including through-holes (s1), providing a
plurality of semiconductor chips, each one of the semiconductor
chips defining a first surface including contact elements and a
second surface opposite to the first surface of the semiconductor
chips and side surfaces between the first and second surfaces,
respectively (s2), placing the semiconductor chips onto the first
layer with the first surface facing the first layer (s3), applying
an encapsulant material over at least the side surfaces of the
semiconductor chips (s4), applying a conducting layer over the
first layer and the contact elements, the conducting layer
including conducting areas, each one of the conducting areas
connected with one of the contact elements, respectively (s5), and
dividing the resulting structure into semiconductor devices
(s6).
[0061] According to one embodiment of the method of fabricating a
plurality of semiconductor devices, the method further includes
placing the semiconductor chips onto the first layer with the
contact elements being aligned with the through-holes.
[0062] According to one embodiment of the method of fabricating a
plurality of semiconductor devices, the through-holes are formed by
at least one of stamping, laser drilling, or selective etching the
first layer.
[0063] According to one embodiment of the method of fabricating a
plurality of semiconductor devices, the first layer is an
insulating layer.
[0064] According to one embodiment of the method of fabricating a
plurality of semiconductor devices, the first layer is comprised of
a first insulation layer facing the semiconductor chips and a metal
layer facing away from the semiconductor chips.
[0065] According to one embodiment of the method of fabricating a
plurality of semiconductor devices, the first layer is attached to
a second layer. According to a further embodiment thereof, the
second layer is separated from the first layer after placing the
semiconductor chips onto the first layer and encapsulating the
semiconductor chips.
[0066] Referring to FIGS. 7A-E, there are illustrated
cross-sectional representations of intermediate products and
semiconductor devices for illustrating a method of fabricating a
plurality of semiconductor devices according to one embodiment of
the embodiment as depicted in FIG. 6. This embodiment illustrates a
complete embedding packaging process. FIG. 7A illustrates a
cross-sectional representation of a first layer 1, the first layer
1 including through-holes 1A, and of a plurality of semiconductor
chips 2, wherein each one of the semiconductor chips 2 defines a
first surface including contact elements 2A and a second surface
opposite to the first surface of the semiconductor chips 2,
respectively.
[0067] FIG. 7B illustrates a cross-sectional representation of an
intermediate product obtained after placing the plurality of
semiconductor chips 2 onto the first layer 1 with the first surface
of the semiconductor chips 2 facing the first layer 1. The
semiconductor chips 2 are placed onto the first layer 1 with a
sufficient spacing from each other in order to allow a fan-out of
the electrical contacts. A pick-and-place-machine can be used for
placing the semiconductor chips 2 onto the first layer 1. There are
illustrated three semiconductor chips 2 which is to be understood
only as an example. In fact the number of semiconductor chips can
be much higher than that and the semiconductor chips 2 can be
placed in the form of a regular array onto the first layer 1. Also
the semiconductor chip 2 can represent a multichip arrangement
resulting in a system-in-package (SIP).
[0068] In FIG. 7C there is illustrated a cross-sectional
representation of a further intermediate product obtained after
applying an encapsulant material 3 onto the semiconductor chips 2
so that the semiconductor chips 2 are embedded in the encapsulant
material 3. The encapsulant material can be applied by, for
example, molding, in one embodiment by using a mold form
corresponding to the form of a wafer so that an embedded wafer can
be formed.
[0069] FIG. 7D illustrates a cross-sectional representation of a
further intermediate product obtained after applying a conducting
layer 8 over the first layer 1 and the contact elements 2A, the
conducting layer 8 including conducting areas 8A, each one of the
conducting areas 8A connected with one of the contact elements 2A
of the semiconductor chips 2, respectively.
[0070] FIG. 7E illustrates a cross-sectional representation of an
intermediate product obtained after applying a solder resist layer
9. The solder resist layer 9 is structured after being applied so
that it forms openings 9A, the openings 9A of the solder resist
layer 9 being aligned with the contact areas 8A of the conducting
layer 8. According to a further embodiment the solder resist is
applied in a structured form by, for example, a printing process
like e.g., ink jetting or screen or stencil printing.
[0071] FIG. 7F illustrates a cross-sectional representation of an
intermediate product obtained after filling solder balls 10 into
the openings 9A of the solder resist layer 9. The solder balls 10
are thus electrically connected to the contact areas 8A and extend
outwardly over the surface of the solder resist layer 9. Finally,
as illustrated by the dashed lines, the resulting structure is
divided along the dashed lines to reveal a plurality of
semiconductor devices.
[0072] In FIG. 8 there is illustrated a cross-sectional
representation of a semiconductor device or a semiconductor chip
package according to one embodiment. The semiconductor chip package
20 includes at least one semiconductor chip 2 including contact
elements 2A on a first surface of the semiconductor chip 2, an
encapsulant material 3 covering at least partly the semiconductor
chip 2, a dielectric layer 1 situated on the first surface of the
semiconductor chip 2, the dielectric layer 1 including
through-holes 1A aligned with the contact elements 2A, and a layer
26 of a conductive material covering a surface of the dielectric
layer 1 above the through-holes 1A, the conductive material being
produced by applying conductive ink to the surface and one or more
of drying, curing and sintering the conductive ink.
[0073] According to one embodiment of the semiconductor device 20,
the semiconductor device 20 further includes a conducting layer
including conducting areas, each one of the conducting areas
connected with respective contact elements 2A by an electrically
conducting material filled in the through-holes 1A, respectively,
wherein the conducting material can be conductive ink. According to
a further embodiment thereof, the semiconductor device 20 further
includes a solder resist layer applied above the conducting layer,
the solder resist layer including openings above the conducting
areas. According to a further embodiment thereof, the semiconductor
device 20 further includes solder balls applied above the openings
of the solder resist layer, the solder balls being electrically
connected to the contact areas, respectively.
[0074] Referring to FIG. 9, there is illustrated a cross-sectional
representation of a semiconductor device according to one
embodiment. The semiconductor device 30 as illustrated in FIG. 9
includes at least one semiconductor chip 2 including contact
elements 2A on a first surface of the semiconductor chip 2, an
encapsulant material 3 covering at least partly the semiconductor
chip 2, a dielectric layer 1 situated on the first surface of the
semiconductor chip 2, the dielectric layer 1 including
through-holes 1A aligned with the contact elements 2A, and a layer
36 of a conductive material covering a surface of the dielectric
layer 1 above the through-holes 1A, the conductive material being
comprised of conductive particles embedded in a matrix.
[0075] According to one embodiment of the semiconductor device 30,
the semiconductor device 30 further includes a conducting layer
including conducting areas, each one of the conducting areas
connected with respective contact elements 2A by an electrically
conducting material filled in the through-holes 1A, respectively,
wherein the conducting material can be conductive ink or conductive
paste. According to a further embodiment thereof, the semiconductor
device 30, further includes a solder resist layer applied above the
conducting layer, the solder resist layer including openings above
the contact areas. According to a further embodiment thereof, the
semiconductor device 30 further includes solder balls applied above
the openings of the solder resist layer, the solder balls being
electrically connected to the contact areas, respectively.
[0076] In FIG. 10 there is illustrated a cross-sectional
representation of a semiconductor device or a semiconductor chip
package according to one embodiment. The semiconductor chip package
40 includes at least one semiconductor chip 2 including contact
elements 2A on a first surface of the semiconductor chip 2, an
encapsulant material 3 covering at least partly the semiconductor
chip 2, a dielectric layer 1 situated on the first surface of the
semiconductor chip 2, the dielectric layer 1 including
through-holes 1A aligned with the contact elements 2A, and a layer
46 of a conductive material covering a surface of the dielectric
layer 1 above the through-holes 1A, the layer 46 being produced by
a sputtering process. According to one embodiment the layer 46 is a
sputtered metallic layer including an element metal or metal
alloy.
[0077] According to one embodiment of the semiconductor device 40,
the semiconductor device 40 further includes a conducting layer
including conducting areas, each one of the conducting areas
connected with respective contact elements 2A by an electrically
conducting material filled in the through-holes 1A, respectively,
wherein the conducting material can be conductive ink. According to
a further embodiment thereof, the semiconductor device 20 further
includes a solder resist layer applied above the conducting layer,
the solder resist layer including openings above the conducting
areas. According to a further embodiment thereof, the semiconductor
device 20 further includes solder balls applied above the openings
of the solder resist layer, the solder balls being electrically
connected to the contact areas, respectively.
[0078] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that a variety of alternate and/or equivalent
implementations may be substituted for the specific embodiments
shown and described without departing from the scope of the present
invention. This application is intended to cover any adaptations or
variations of the specific embodiments discussed herein. Therefore,
it is intended that this invention be limited only by the claims
and the equivalents thereof.
* * * * *