U.S. patent application number 12/475807 was filed with the patent office on 2009-12-17 for method for producing semiconductor wafer.
This patent application is currently assigned to SUMCO CORPORATION. Invention is credited to Tomohiro Hashii, Yuichi Kakizono.
Application Number | 20090311949 12/475807 |
Document ID | / |
Family ID | 41415224 |
Filed Date | 2009-12-17 |
United States Patent
Application |
20090311949 |
Kind Code |
A1 |
Hashii; Tomohiro ; et
al. |
December 17, 2009 |
METHOD FOR PRODUCING SEMICONDUCTOR WAFER
Abstract
A semiconductor wafer is produced by a method comprising a
slicing step of cutting out a thin disc-shaped semiconductor wafer
from a crystalline ingot; and a fixed grain bonded abrasive
grinding step of sandwiching the semiconductor wafer between a pair
of upper and lower plates each having a pad of fixed grain bonded
abrasive to simultaneously grind both surfaces of the semiconductor
wafer.
Inventors: |
Hashii; Tomohiro; (Tokyo,
JP) ; Kakizono; Yuichi; ( Tokyo, JP) |
Correspondence
Address: |
FITZPATRICK CELLA HARPER & SCINTO
1290 Avenue of the Americas
NEW YORK
NY
10104-3800
US
|
Assignee: |
SUMCO CORPORATION
Tokyo
JP
|
Family ID: |
41415224 |
Appl. No.: |
12/475807 |
Filed: |
June 1, 2009 |
Current U.S.
Class: |
451/54 |
Current CPC
Class: |
H01L 21/02008 20130101;
B24B 7/17 20130101; B24B 7/228 20130101; B24B 37/08 20130101 |
Class at
Publication: |
451/54 |
International
Class: |
B24B 1/00 20060101
B24B001/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 16, 2008 |
JP |
2008-157230 |
Claims
1. A method for producing a semiconductor wafer, comprising a
slicing step of cutting out a thin disc-shaped semiconductor wafer
from a crystalline ingot; and a fixed grain bonded abrasive
grinding step of sandwiching the semiconductor wafer between a pair
of upper and lower plates each having a pad of fixed grain bonded
abrasive to simultaneously grind both surfaces of the semiconductor
wafer.
2. A method for producing a semiconductor wafer, comprising a
slicing step of cutting out a thin disc-shaped semiconductor wafer
from a crystalline ingot; a double-sided polishing step of
simultaneously polishing both surfaces of the semiconductor wafer;
and a one-side finish polishing step being subjected to a one-side
face of the semiconductor wafer polished at the double-sided
polishing step, which further comprises between the slicing step
and the double-sided polishing step a fixed grain bonded abrasive
grinding step wherein the semiconductor wafer is fitted into a
circular hole of a carrier having a plurality of circular holes
closely aligned to each other and the carrier is sandwiched between
a pair of upper and lower plates each having a pad of fixed grain
bonded abrasive and then the upper and lower plates are rotated
while oscillating the carrier in the same horizontal plane to
simultaneously conduct a high-speed treatment from rough grinding
to finish grinding on both surfaces of the semiconductor wafer at
once; and a chemical treating step wherein reduction of working
strain on the surfaces and an end face of the semiconductor wafer
and a finish beveling of rendering the end face of the
semiconductor wafer into a given beveled form are simultaneously
conducted in any order.
3. A method for producing a semiconductor wafer according to claim
1 or 2, wherein the semiconductor wafer is a silicon wafer having a
diameter of not less than 450 mm.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention
[0001] This invention relates to a method for producing a
semiconductor wafer, and more particularly to a method for
producing a semiconductor wafer by cutting out a thin disc-shaped
semiconductor wafer from a crystalline ingot and then subjecting
both surfaces thereof to a mirror finishing. 2. Description of the
Related Art
[0002] The conventional method for producing a semiconductor wafer
typically comprises a series of a slicing step.fwdarw.a first
beveling step.fwdarw.a lapping step.fwdarw.a second beveling
step.fwdarw.a one-side grinding step.fwdarw.a double-sided
polishing step.fwdarw.a one-side finish polishing step in this
order.
[0003] In the slicing step, a thin disc-shaped semiconductor wafer
is cut out from a crystalline ingot. In the first beveling step, an
outer peripheral portion of the cut semiconductor wafer is beveled
to suppress the occurrence of cracking or chipping in the
semiconductor wafer at the subsequent lapping step. In the lapping
step, the beveled semiconductor wafer is lapped with a grindstone
of, for example, #1000 to increase a flatness of the semiconductor
wafer. In the second beveling step, an outer peripheral portion of
the lapped semiconductor wafer is beveled to render an end face of
the semiconductor wafer into a given beveled form. In the one-side
grinding step, a one-side face of the beveled semiconductor wafer
is ground with a grindstone of, for example, #2000-8000 to
approximate the thickness of the semiconductor wafer to a final
thickness. In the double-sided polishing step, both surfaces of the
one-side ground semiconductor wafer are polished. In the one-side
finish polishing step, a one-side face of the double-sided polished
semiconductor wafer as a device face is further subjected to finish
polishing.
[0004] In the aforementioned conventional method, a double-sided
mirror finished semiconductor wafer is produced through the two
beveling steps, the lapping step and the one-side grinding step, so
that there are problems that a kerf loss of a semiconductor
material (loss of semiconductor material due to the increase of
lapped scrap and one-side ground scrap) is brought about due to a
large number of steps.
[0005] Particularly, the above problem is remarkable on a
large-diameter semiconductor wafer such as a silicon wafer having a
diameter of not less than 450 mm. For example, when a silicon wafer
having a diameter of not less than 450 mm is produced at the same
machining allowance as a currently major silicon wafer having a
diameter of 300 mm, the kerf loss of the silicon wafer is 2.25
times.
[0006] In addition, when the above-mentioned lapping step is added
to the production method for a silicon wafer having a diameter of
not less than 450 mm, the size of the lapping apparatus is
considerably grown, which will be brought question on a place of
disposing the lapping apparatus or the like in the formulation of
the production line.
[0007] In Japanese Patent No. 3,328,193, a method for producing a
semiconductor wafer, which comprises a double-sided grinding step
instead of the lapping step in the above conventional method, is
proposed.
[0008] In the production method of the semiconductor wafer
disclosed in this patent document, the problem of growing the size
of the lapping apparatus in the production of the large-diameter
semiconductor wafer is solved and the first beveling step before
the double-sided grinding step can be omitted, but the double-sided
grinding step and the one-side grinding step are conducted, and
hence the machining allowance of the silicon material is still
large, which remains as a problem about the kerf loss.
[0009] Moreover, it is desired to improve the flatness of the
semiconductor wafer, which will be anticipated to become more
severe in future, by reducing the machining allowance of the
semiconductor wafer.
SUMMARY OF THE INVENTION
[0010] It is, therefore, an object of the invention is to
advantageously solve the above-mentioned problems and to provide a
method for producing a semiconductor wafer wherein both surfaces of
a semiconductor wafer cut out from a crystalline ingot can be
mirror-finished by a simple process flow obtained by omitting at
least the beveling step, and also the semiconductor wafer can be
obtained cheaply by reducing the machining allowance of silicon
material in the semiconductor wafer to reduce the kerf loss of the
semiconductor material. Particularly, the invention develops a
remarkable effect when the semiconductor wafer is a silicon wafer
having a large diameter of not less than 450 mm.
[0011] In order to solve the above problems, the inventors have
made various studies about a method for producing a semiconductor
wherein the number of production steps when a semiconductor wafer
cut out from a crystalline ingot is rendered into a double-sided
mirror-finished semiconductor wafer is decreased but also silicon
kerf loss in the semiconductor wafer is reduced as compared with
those of the conventional method.
[0012] As a result, it has been found that the number of production
steps can be decreased but also the machining allowance of the
semiconductor wafer can be reduced as compared with the
conventional method by conducting a fixed grain bonded abrasive
grinding step of simultaneously conducting a high-speed treatment
from rough grinding to finish grinding on both surfaces at once,
instead of the lapping step and the one-side grinding step in the
above conventional method, and a chemical treating step of
simultaneously conducting not only reduction of working strain on
surfaces and an end face of the semiconductor wafer but also a
beveling.
[0013] The invention is based on the above knowledge and the
summary and construction thereof are as follows.
[0014] 1. A method for producing a semiconductor wafer, comprising
a slicing step of cutting out a thin disc-shaped semiconductor
wafer from a crystalline ingot; and a fixed grain bonded abrasive
grinding step of sandwiching the semiconductor wafer between a pair
of upper and lower plates each having a pad of fixed grain bonded
abrasive to simultaneously grind both surfaces of the semiconductor
wafer.
[0015] 2. A method for producing a semiconductor wafer, comprising
a slicing step of cutting out a thin disc-shaped semiconductor
wafer from a crystalline ingot; a double-sided polishing step of
simultaneously polishing both surfaces of the semiconductor wafer;
and a one-side finish polishing step being subjected to a one-side
face of the semiconductor wafer polished at the double-sided
polishing step, which further comprises between the slicing step
and the double-sided polishing step a fixed grain bonded abrasive
grinding step wherein the semiconductor wafer is fitted into a
circular hole of a carrier having a plurality of circular holes
closely aligned to each other and the carrier is sandwiched between
a pair of upper and lower plates each having a pad of fixed grain
bonded abrasive and then the upper and lower plates are rotated
while oscillating the carrier in the same horizontal plane to
simultaneously conduct a high-speed treatment from rough grinding
to finish grinding on both surfaces of the semiconductor wafer at
once; and a chemical treating step wherein reduction of working
strain on the surfaces and an end face of the semiconductor wafer
and a finish beveling of rendering the end face of the
semiconductor wafer into a given beveled form are simultaneously
conducted in any order.
[0016] 3. A method for producing a semiconductor wafer according to
the item 1 or 2, wherein the semiconductor wafer is a silicon wafer
having a diameter of not less than 450 mm.
[0017] According to the production method of the semiconductor
wafer according to the invention, a fixed grain bonded abrasive
grinding step and a chemical treating step are conducted between
the slicing step and the double-sided polishing step, whereby the
number of production steps for the semiconductor wafer is shortened
as compared with the conventional method and the machining
allowance of the semiconductor wafer can be reduced to reduce the
kerf loss of the semiconductor material to thereby obtain the
semiconductor wafer cheaply.
[0018] Also, the flatness of the semiconductor wafer can be
improved by reducing the machining allowance of the semiconductor
wafer. Furthermore, a semiconductor wafer having an epitaxial layer
can be obtained by conducting an epitaxial layer growing step
between the chemical treating step and the double-sided polishing
step or after the double-sided polishing step. The production
method of the semiconductor wafer according to the invention is
especially suitable for the production of silicon wafers having a
large diameter of not less than 450 mm.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The invention will be described with reference to the
accompanying drawings, wherein:
[0020] FIG. 1 is a flow chart showing production steps according to
a first embodiment of the invention;
[0021] FIG. 2 (a) is a schematic cross-sectional view of an
apparatus used in a fixed grain bonded abrasive grinding step;
[0022] FIG. 2 (b) is a schematic top view of the apparatus showing
a state just before the start of the fixed grain bonded abrasive
grinding step;
[0023] FIG. 2 (c) is a schematic top view of the apparatus showing
a state after a predetermined time of the fixed grain bonded
abrasive grinding step;
[0024] FIG. 3 is a schematic cross-sectional view and a top view of
an apparatus used in the conventional lapping step;
[0025] FIG. 4 is a flow chart showing production steps according to
a second embodiment of the invention;
[0026] FIG. 5 is a flow chart showing production steps of
Conventional Example 1; and
[0027] FIG. 6 is a flow chart showing production steps of
Conventional Example 2.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] FIG. 1 is a flow chart showing production steps according to
a first embodiment of the invention. In the first embodiment of the
invention, the following five steps (1) to (5) are conducted in
this order:
[0029] (1) a slicing step of cutting out a thin disc-shaped
semiconductor wafer from a crystalline ingot;
[0030] (2) a fixed grain bonded abrasive grinding step wherein the
semiconductor wafer is fitted into a circular hole of a carrier
having a plurality of circular holes closely aligned to each other
and the carrier is sandwiched between a pair of upper and lower
plates each having a pad of fixed grain bonded abrasive and then
the upper and lower plates are rotated while oscillating the
carrier in the same horizontal plane to simultaneously conduct a
high-speed treatment from rough grinding to finish grinding on both
surfaces of the semiconductor wafer at once;
[0031] (3) a chemical treating step of simultaneously conducting
reduction of working strain on the surfaces and an end face of the
semiconductor wafer and a finish beveling of making the end face of
the semiconductor wafer to a given beveled form;
[0032] (4) a double-sided polishing step of simultaneously
polishing both surfaces of the semiconductor wafer; and
[0033] (5) a one-side finish polishing step of finish polishing a
one-side face of the double-sided polished semiconductor wafer.
[0034] Next, the each step in the first embodiment of the invention
will be described.
[0035] The slicing step is a step of cutting out a thin disc-shaped
wafer by contacting a wire saw with a crystalline ingot while
supplying a grinding solution, or by cutting a crystalline ingot
with an inner diameter blade. In order to reduce a processing load
in the subsequent fixed grain bonded abrasive grinding step and
chemical treating step, the semiconductor wafer after the slicing
step is preferable to have a high flatness and a small surface
roughness as far as possible.
[0036] Moreover, the crystalline ingot is typically an ingot of
silicon single crystal, but may be an ingot of polycrystalline
silicon for solar cells.
[0037] (Fixed Grain Bonded Abrasive Grinding Step)
[0038] The fixed grain bonded abrasive grinding step is a step of
roughly grinding both surfaces of the semiconductor wafer cut in
the slicing step to increase the flatness and to approximate the
thickness of the semiconductor wafer to the final thickness.
[0039] FIG. 2 is a schematic view of a fixed grain bonded abrasive
grinding apparatus 10 used in the fixed grain bonded abrasive
grinding step, wherein FIG. 2 (a) is a cross-sectional view of the
apparatus 10 used in the fixed grain bonded abrasive grinding step
and FIGS. 2 (b) and (c) are top views of the apparatus 10 used in
the fixed grain bonded abrasive grinding step, respectively. FIGS.
2 (a) and (b) show states just before the start of the fixed grain
bonded abrasive grinding step, and FIG. 2 (c) view shows a state
after a predetermined time of the fixed grain bonded abrasive
grinding step.
[0040] The fixed grain bonded abrasive grinding apparatus 10
comprises a carrier 12 having a plurality of circular holes 11a,
11b and 11c closely aligned to each other, pads 13a, 13b each
having a fixed grain bonded abrasive, a pair of upper and lower
plates 14a, 14b having the pads 13a and 13b, and guide rollers 15a,
15b, 15c, 15d arranged so as to contact with a side face of the
carrier 12 at four divided positions of the circumference of the
carrier 12.
[0041] The semiconductor wafers 16a, 16b, 16c cut out in the
slicing step are fitted into the circular holes 11a, 11b, 11c of
the carrier 12, and thereafter the carrier 12 is sandwiched between
the pair of upper and lower plates 14a, 14b having the pads 13a,
13b with the fixed grain bonded abrasive, and then the upper and
lower plates 14a, 14b are rotated while moving the guide rollers
15a, 15b, 15c, 15d to oscillate the carrier 12 in the same
horizontal plane, whereby both surfaces of each of the wafers 16a,
16b, 16c are ground simultaneously.
[0042] Although there are shown three circular holes 11a, 11b, 11c
in the FIG. 2, the number of circular holes is not limited to
three. However, as shown in FIGS. 2 (b) and (c), it is important
that all of the circular holes 11a, 11b, 11c are disposed so as to
enter into the circumferences of the upper and lower plates 14a,
14b even if the carrier 12 takes any positional relationship with
respect to the upper and lower plates 14a, 14b through oscillating.
This is due to the fact that a pressure applied to the
semiconductor wafer during the fixed gain bonded abrasive grinding
is made uniform as far as possible, whereby the occurrence of
cracking or chipping in the semiconductor wafer during the fixed
grain bonded abrasive grinding is prevented but also the flatness
of the semiconductor wafer after the fixed grain bonded abrasive
grinding is improved without beveling an outer peripheral portion
of the semiconductor wafer after the slicing step. It is preferable
that the circular hole 11 has the same diameter and the number
thereof is 3, because as shown in FIGS. 2 (b) and (c), if the
circular holes 11a, 11b, 11c are aligned closely to each other, the
diameter of the plates 14 can be made minimum and the size of the
fixed grain bonded abrasive grinding apparatus 10 is not
unnecessarily grown. When the diameter of the plate 14 is L1 in
FIG. 2, L1 if three silicon wafers each having a diameter of 450 mm
are ground with the fixed grain bonded abrasive is approximately
985 mm.
[0043] Since the pad has the fixed grain bonded abrasive, it is not
required to supply a slurry of free abrasive grains during the
fixed grain bonded abrasive grinding. Therefore, it is possible to
avoid the deterioration of the flatness of the semiconductor wafer
after the grinding due to non-uniform supply of the free abrasive
grains, which is especially advantageous in a case that a diameter
of the semiconductor wafer is large as in a silicon wafers having a
diameter of not less than 450 mm and it is difficult to supply the
free abrasive grains uniformly.
[0044] The material of the abrasive grains in the pad having the
fixed grain bonded abrasive is generally diamond, but abrasive
grains of SiC may be also used. Although the pad with the fixed
grain bonded abrasive may have a roughness of #1000-8000, as
previously mentioned, the pressure applied to the semiconductor
wafer during the fixed grain bonded abrasive grinding is uniform
and the grinding action of the abrasive grains to the semiconductor
wafer is uniform owing to the use of the fixed grain bonded
abrasive instead of the free abrasive grains, so that it is
possible to conduct a high-speed treatment from rough grinding to
finish grinding at once without occurrence of cracking or chipping
even if a semiconductor wafer having a rough surface state just
after the slicing step is subjected to a fixed grain bonded
abrasive grinding with a fine pad of about #8000.
[0045] During the fixed grain bonded abrasive grinding, it is
preferable to wash out ground scraps, or to supply water or an
alkali solution for the purpose of lubrication.
[0046] Moreover, when a grinding margin at the fixed grain bonded
abrasive grinding step is less than 20 .mu.m per one-side surface,
the undulation of the wafer generated in the cutting will be a
problem, while when it exceeds 50 .mu.m, the strength of the wafer
becomes lacking. Therefore, the grinding margin at the fixed grain
bonded abrasive grinding step is preferable to be 20-50 .mu.m per
one-side surface.
[0047] Now, the lapping step will be briefly described to compare
the fixed grain bonded abrasive grinding step employed in the
invention with the lapping step employed in the conventional
method.
[0048] In the FIG. 3 is schematically shown an apparatus used in
the lapping step employed in the conventional method. The lapping
apparatus 50 comprises carriers 52a, 52b, 52c, 52d, 52e each having
a respective circular hole 51a, 51b, 51c, 51d, or 51e and provided
on its side face with a gear, pads 53a, 53b, a pair of upper and
lower plates 54a, 54b having the pads 53a, 53b, an outer peripheral
gear 55 in the sun-and-planet motion of the carriers 52a, 52b, 52c,
52d, 52e, and a center gear 56 engaging with the gears provided on
the side faces of the carriers 52a, 52b, 52c, 52d, 52e.
[0049] The semiconductor wafers 57a, 57b, 57c, 57d, 57e cut in the
slicing step are fitted into the circular holes 51a, 51b, 51c, 51d,
51e of the carriers 52a, 52b, 52c, 52d, 52e, and thereafter the
carriers 52a, 52b, 52c, 52d, 52e are sandwiched between the pair of
the upper and lower plates 54a, 54b having the pads 53a, 53b, and
then the center gear 56 is rotated to conduct the sun-and-planet
motion of the carriers 52a, 52b, 52c, 52d, 52e along the outer
peripheral gear 55 while supplying free abrasive grains to the
wafers 57a, 57b, 57c, 57d, 57e, to thereby lap the wafers 57a, 57b,
57c, 57d, 57e.
[0050] In the lapping apparatus 50, the area occupied by the center
gear 56 is large and the area of the plate 54 becomes large
accompanied therewith, and hence the whole size of the lapping
apparatus 50 tends to be grown. In the lapping of the
large-diameter semiconductor wafers, the sizes of the carriers 52a,
52b, 52c, 52d, 52e are grown and hence the force required for the
sun-and-planet motion of the carriers 52a, 52b, 52c, 52d, 52e
becomes large to grow the size of the center gear 56, and as a
result, the size of the lapping apparatus 50 becomes more larger,
which is a serious problem. In FIG. 3, when the diameter of the
plate 54 is L2, if three semiconductor wafers of 450 mm in diameter
are lapped, L2 is about 2200 mm, which is much larger than LI in
the fixed grain bonded abrasive grinding apparatus 10. Thus, when
silicon wafers having a diameter of not less than 450 mm are
produced by a method including the lapping step, it is required to
use a very large lapping apparatus, which may cause a problem in
the installation site and the like.
[0051] Also, in the lapping step, the size of the guide becomes
larger since the lapping is conducted while supplying free abrasive
grains. As a result, the supply area of free abrasive grains
becomes wider, and it is difficult to supply them uniformly, which
may easily deteriorate the flatness of the semiconductor wafer
after the lapping step but also may cause the cracking or chipping
in the lapping.
[0052] (Chemical Treating Step)
[0053] The chemical treating step simultaneously conducts reduction
of working strain on the surfaces and end face of the semiconductor
wafer applied at the slicing step or both the slicing step and the
fixed grain bonded abrasive grinding step, and a finish beveling of
making the end face of the semiconductor wafer to a given beveled
form, which may be either a batch type or a sheet-feed type
chemical treatment.
[0054] The batch type chemical treatment is a treatment of
immersing a plurality of semiconductor wafers (e.g. 24 wafers) into
a vessel containing a given etching solution to simultaneously
conduct the reduction of working strain on both surfaces and end
faces of the semiconductor wafer and the finish beveling of making
the end face of the semiconductor wafer to a given beveled
form.
[0055] The sheet-feed type chemical treating step is a treatment
that one semiconductor wafer is rotated while adding dropwise an
etching solution to a one-side face of the semiconductor wafer,
whereby the etching solution is extended over the both surfaces and
end faces of the semiconductor wafer through centrifugal force to
reduce working strain on both the surfaces and end faces of the
semiconductor wafer, and at the same time the end face of the
semiconductor wafer is subjected to a finish beveling to a given
beveled form. The sheet-feed type chemical treatment is conducted
twice so that both surfaces are etched by subjecting each one-side
face thereto. On the end face, conditions of etching are set for
making a given form by two etchings.
[0056] As the etching solution used in the sheet-feed type chemical
treatment, it is preferable to use a mixed acids of hydrofluoric
acid, nitric acid and phosphoric acid, because it is required that
when the etching solution is added dropwise to the rotating
semiconductor wafer, it is extended over the surface of the
semiconductor wafer to be etched at a proper rate to form a uniform
film of the etching solution on this surface. A mixed acid of
hydrofluoric acid, nitric acid and acetic acid usually used as the
etching solution in the batch type chemical treatment is not
preferable because it is low in the viscosity and when it is added
dropwise to the rotating semiconductor wafer, a rate of extending
over the surface to be etched is too fast and the film of the
etching solution is not formed, resulting in irregular etching.
[0057] Moreover, the mixed acid of hydrofluoric acid, nitric acid
and phosphoric acid used as the etching solution in the sheet-feed
type chemical treatment is preferable to comprise 5-20 mass % of
hydrofluoric acid, 5-40 mass % of nitric acid, 30-40 mass % of
phosphoric acid.
[0058] (Double-sided Polishing Step)
[0059] In the double-side polishing step, both surfaces of the
semiconductor wafer subjected to the fixed grain bonded abrasive
grinding step and the chemical treating step are polished with an
abrasive cloth made of urethane and the like while supplying an
abrasive slurry. The kind of the abrasive slurry is not
particularly limited, but colloidal silica having a particle size
of 0.5 to 2 .mu.m is preferable.
[0060] (One-side Finish Polishing Step)
[0061] In the one-side finish polishing step, a one-side face of
the double-sided polished semiconductor wafer as a device surface
is polished with an abrasive cloth made of urethane or the like
while supplying an abrasive slurry. The kind of the abrasive slurry
is not particularly limited, but colloidal silica having a particle
size of not more than 0.5 .mu.m is preferable.
[0062] Next, the second embodiment according to the invention will
be described. FIG. 4 is a flow chart showing production steps of
the second embodiment according to the invention. It should be
noted that the same steps as in FIG. 1 are named the same in FIG.
4
[0063] Here, the second embodiment shown in FIG. 4 is common to the
first embodiment shown in FIG. 1 in a point that the fixed grain
bonded abrasive grinding step and the chemical treating step are
conducted between the slicing step and the double-sided grinding
step, but the order of conducting the fixed grain bonded abrasive
grinding step and the chemical treating step differs between both
the embodiments.
[0064] As mentioned in the explanation of the chemical treating
step, the chemical treating step has an action of finish-beveling
the end face of the semiconductor wafer to a given beveled form.
Therefore, it is advantageous that only the double-sided polishing
step and the one-side finish polishing step are conducted after the
chemical treating step in view of a point that the grinding step
showing a large reduction amount of the thickness of the
semiconductor wafer is avoided to suppress a variation of a beveled
width in the semiconductor wafer.
[0065] That is, the first embodiment according to the invention
shown in FIG. 1, i.e., the order of the fixed grain bonded abrasive
grinding step the chemical treating step is preferable.
[0066] Even when the semiconductor wafer is produced by the order
of the chemical treating step the fixed grain bonded abrasive
grinding step in the second embodiment according to the invention
shown in FIG. 2, the effects on the reduction of the production
step number and the reduction of the kerf loss in the semiconductor
wafer similar to those of the first embodiment are advantageously
obtained as compared with the conventional method though the
variation of the beveled width in the semiconductor wafer becomes
somewhat big to retain working strain caused at the fixed grain
bonded abrasive grinding step. Therefore, when the variation of the
beveled width and the residual working strain in the semiconductor
wafer are included in a quality standard required for the
semiconductor wafer, the second embodiment according to the
invention is an effective means for reducing the production cost of
the semiconductor wafer. In addition, if it is emphasized to
mitigate the working strain on the end face of the wafer, a finish
beveling step may be conducted after the fixed grain bonded
abrasive grinding step.
[0067] Although the above is described with respect to the main
steps in the production method according to the invention, a
polishing step of beveled portion and/or an epitaxial layer growing
step may be included, if desired. The polishing step of beveled
portion and the epitaxial layer growing step will be described
below.
[0068] (Polishing Step of Beveled Portion)
[0069] The polishing step of the beveled portion is conducted after
the double-sided polishing step for polishing the beveled portion
of the semiconductor wafer to reduce a variation of the beveled
width in the wafer. In this case, the beveled portion is polished
with an abrasive cloth made of urethane or the like while supplying
an abrasive slurry. The kind of the abrasive slurry is not
particularly limited, but colloidal silica having a particle size
of about 0.5 .mu.m is preferable.
[0070] (Epitaxial Layer Growing Step)
[0071] A semiconductor wafer having an epitaxial layer can be
obtained by conducting an epitaxial layer growing step between the
chemical treating step and the double-sided polishing step or after
the double-sided polishing step. When the epitaxial layer is grown
on the surface of the semiconductor wafer, it is required to remove
surface damage of the semiconductor wafer applied at the slicing
step and optionally at the fixed grain bonded abrasive grinding
step, so that the epitaxial layer growing step is preferable to be
conducted between the chemical treating step and the double-sided
polishing step, or after the double-sided polishing step.
[0072] Although the above is merely described with respect to one
embodiment of the invention, various modifications may be made
without departing from the scope of the appended claims.
[0073] A semiconductor wafer is prepared by the production method
according to the invention as stated below.
INVENTION EXAMPLE 1
[0074] A silicon wafer having a diameter of 300 mm is prepared
according to a flow chart of FIG. 1 in the first embodiment
according to the invention.
INVENTION EXAMPLE 2
[0075] A silicon wafer having a diameter of 450 mm is prepared in
the same production method as in Invention Example 1.
INVENTION EXAMPLE 3
[0076] A silicon wafer having a diameter of 300 mm is prepared
according to a flow chart of FIG. 4 in the second embodiment
according to the invention.
INVENTION EXAMPLE 4
[0077] A silicon wafer having a diameter of 450 mm is prepared in
the same production method as in Invention Example 3.
CONVENTIONAL EXAMPLE 1
[0078] A silicon wafer having a diameter of 300 mm is prepared by
the conventional production method shown in FIG. 5 inclusive of a
lapping step.
CONVENTIONAL EXAMPLE 2
[0079] A silicon wafer having a diameter of 300 mm is prepared by a
production method shown in FIG. 6 using a double-sided polishing
step instead of the lapping step.
[0080] With respect to each of the thus obtained samples are
evaluated the silicon kerf loss and flatness. The evaluation method
will be described below.
[0081] (Silicon Kerf Loss)
[0082] The silicon kerf loss is evaluated by a reduction quantity
(.mu.m) of a thickness in the semiconductor wafer before and after
the fixed grain bonded abrasive grinding step in Invention Examples
1 to 4, the sum of a reduction quantity (.mu.m) of a thickness in
the semiconductor wafer before and after the lapping step and a
reduction quantity (.mu.m) of a thickness in the semiconductor
wafer before and after the one-side grinding step in Conventional
Example 1, and the sum of a reduction quantity (.mu.m) of a
thickness in the semiconductor wafer before and after the
double-sided grinding step and a reduction quantity (.mu.m) of a
thickness in the semiconductor wafer before and after the one-side
grinding step in Conventional Example 2, respectively.
[0083] (Flatness)
[0084] The flatness of each sample is measured with a capacitance
type thickness sensing meter and is evaluated as follows:
[0085] .largecircle.: The flatness is less than 0.5 .mu.m.
[0086] .DELTA.: The flatness is not less than 0.5 .mu.m and not
more than 1 .mu.m.
[0087] X: The flatness is more than 1 .mu.m.
[0088] The evaluation results of the each sample are shown in Table
1.
TABLE-US-00001 TABLE 1 Invention Invention Invention Invention
Conventional Conventional Example 1 Example 2 Example 3 Example 4
Example 1 Example 2 Flow chart FIG. 1 FIG. 1 FIG. 4 FIG. 4 FIG. 5
FIG. 6 Diameter (mm) 300 450 300 450 300 300 Silicon kerf loss 40
60 40 60 100 105 (ground thickness: (.mu.m)) Flatness .largecircle.
.largecircle. .largecircle. .largecircle. .DELTA. .DELTA.
[0089] As seen from Table 1, Invention Example 1 shows a minimum
value of the silicon kerf loss and a good flatness, and Invention
Example 2 shows good results substantially equal to those in
Invention Example 1, from which it has been confirmed that a
silicon wafer having a large diameter of 450 mm is obtained by the
production method according to the first embodiment of the
invention. Moreover, good results substantially equal to those in
Invention Examples 1 and 2 on the silicon kerf loss and the
flatness are obtained in Examples 3 and 4 by the production method
according to the second embodiment of the invention. On the other
hand, Conventional Examples 1 and 2 show a large silicon kerf loss
and a poor flatness as compared with Invention Examples 1 to 4.
[0090] According to the production method of the semiconductor
wafer according to the invention, the fixed grain bonded abrasive
grinding step and the chemical treating step are conducted between
the slicing step and the double-sided polishing step, whereby the
number of production steps for the semiconductor wafer is shortened
as compared with the conventional method and the machining
allowance of the semiconductor wafer can be reduced to reduce the
kerf loss of the semiconductor material to thereby obtain the
semiconductor wafer cheaply. Also, the flatness of the
semiconductor wafer can be improved by reducing the machining
allowance of the semiconductor wafer. Furthermore, a semiconductor
wafer having an epitaxial layer can be obtained by conducting an
epitaxial layer growing step between the chemical treating step and
the double-sided polishing step, or after the double-sided
polishing step. The production method of the semiconductor wafer
according to the invention is especially suitable for the
production of silicon wafers having a large diameter of not less
than 450 mm.
* * * * *