U.S. patent application number 12/094768 was filed with the patent office on 2009-11-26 for semiconductor device.
Invention is credited to Masayuki Satoh.
Application Number | 20090290444 12/094768 |
Document ID | / |
Family ID | 38066980 |
Filed Date | 2009-11-26 |
United States Patent
Application |
20090290444 |
Kind Code |
A1 |
Satoh; Masayuki |
November 26, 2009 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device includes a plurality of memory cell
blocks, each including a plurality of memory cells each storing a
predetermined amount of data. Each of the memory cell blocks
stores, in the memory cells thereof, truth table data used for
outputting desired logical values in response to input of a given
address so as to function as a logic circuit. The number of inputs
and the number of outputs of the memory cell block is three or
more, and the memory cell blocks are connected to each other so
that three or more outputs from one memory cell block are input to
three or more other memory cell blocks.
Inventors: |
Satoh; Masayuki; (Gunma,
JP) |
Correspondence
Address: |
KNOBBE MARTENS OLSON & BEAR LLP
2040 MAIN STREET, FOURTEENTH FLOOR
IRVINE
CA
92614
US
|
Family ID: |
38066980 |
Appl. No.: |
12/094768 |
Filed: |
November 28, 2005 |
PCT Filed: |
November 28, 2005 |
PCT NO: |
PCT/JP2005/021758 |
371 Date: |
November 21, 2008 |
Current U.S.
Class: |
365/230.03 ;
365/189.011 |
Current CPC
Class: |
H03K 19/1776 20130101;
H03K 19/17728 20130101 |
Class at
Publication: |
365/230.03 ;
365/189.011 |
International
Class: |
G11C 8/00 20060101
G11C008/00 |
Claims
1. A semiconductor device comprising: a plurality of memory cell
blocks, each including a plurality of memory cells each storing a
predetermined amount of data; wherein each of the memory cell
blocks stores, in the memory cells thereof, truth table data used
for outputting desired logical values in response to input of a
given address so as to function as a logic circuit, and wherein the
number of inputs and the number of outputs of the memory cell block
is three or more, and the memory cell blocks are connected to each
other so that three or more outputs from one memory cell block are
input to three or more other memory cell blocks.
2. The semiconductor device according to claim 1, wherein the
number of inputs and the number of outputs of the memory cell block
is four, and the memory cell blocks are connected to each other so
that four outputs from one memory cell block are input to four
other memory cell blocks.
3. The semiconductor device according to claim 1, wherein the
plurality of memory cell blocks have a rectangular shape of the
same size, and wherein the memory cell blocks are connected to each
other such that at least some of the memory cell blocks are
positionally shifted from an array arrangement.
4. The semiconductor device according to claim 1, wherein the
plurality of memory cell blocks are arranged in an array and are
connected to each other using interconnection lines.
5. The semiconductor device according to claim 1, wherein each of
the memory cell blocks further includes two read address decoders
therein, and the memory cell includes two read word lines
corresponding to the two read address decoders, and wherein, when a
voltage is applied to the two read word lines, data stored in the
memory cell is read out using a read data line.
6. The semiconductor device according to claim 1, further
comprising: a write address decoder connected to the plurality of
memory cell blocks, the write address decoder specifying an x
address related to the plurality of memory cell blocks and the
memory cell in the memory cell blocks; and a write/read circuit
connected to the plurality of memory cell block, the write/read
circuit specifying a y address related to the plurality of memory
cell blocks and the memory cell in the memory cell blocks so as to
write data to the memory cell; wherein the data is written to the
memory cell by the write/read circuit when the memory cell is
specified by the write address decoder and the write/read
circuit.
7. The semiconductor device according to claim 1, wherein the
semiconductor device functions as a normal storage device when the
memory cell of the memory cell block does not store the truth table
data.
8. The semiconductor device according to claim 7, wherein an
operating area of the memory cell of the memory cell block is
separated into two, and wherein, when a particular address select
line of the read address decoder is switched, the operating areas
of the memory cell are switched so that switching between an
operation in which the memory cell functions as two logic circuits
and an operation in which the memory cell functions as a logic
circuit and a normal storage device is instantaneously
performed.
9. The semiconductor device according to claim 1, wherein, when
truth table data stored in memory cells in some of the memory cell
blocks is updated, the operation of the semiconductor device is
changed in accordance with the updated truth table data.
10. The semiconductor device according to claim 1, wherein the
semiconductor device is included in a system LSI, the semiconductor
device performs a self-test function, and the semiconductor device
tests other logic circuits included in the system LSI.
11. The semiconductor device according to claim 1, wherein the
semiconductor device operates on the basis of a compilation result
of a C language program that describes the operation of the
semiconductor device.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device
capable of operating a memory as a logic circuit.
[0003] 2. Description of the Related Art
[0004] Existing semiconductor devices, such as a large scale
integrations (LSIs), are manufactured through a plurality of steps
including a functional design step, a logic circuit design step, a
wafer production step, and an assembly step. These manufacturing
steps are suitable for mass production for manufacturing a large
number of products of the same type. However, the manufacturing
steps are not suitable for high-mix low-volume production, since
the steps are costly.
[0005] Accordingly, a technology suitable for high-mix low-volume
production has been developed. An example of such a technology is a
field programmable gate array (FPGA). An FPGA is a semiconductor
device (e.g., an LSI) that allows a user to program a logic circuit
after being manufactured.
[0006] However, since an FPGA includes a plurality of components
(e.g., a logic circuit, interconnection lines, and switches), a
multilayer interconnection structure including a plurality of
interconnection layers and a highly advanced manufacturing
technique are disadvantageously required for a semiconductor
process.
[0007] To solve such a problem, Japanese Unexamined Patent
Application Publication No. 2003-224468 describes a semiconductor
device that functions as a logic circuit after a truth table is
written to a memory, such as a static random access memory (SRAM).
When an address is input to the semiconductor device, the
semiconductor device outputs the content of the memory.
[0008] However, in the semiconductor device described in Japanese
Unexamined Patent Application Publication No. 2003-224468, memory
cell blocks each including a plurality of memory cells each storing
a predetermined amount of data are arranged in an array. Data
output from one of the memory cell blocks is output to only two of
the neighboring four memory cell blocks (for example, only the
right block in the horizontal direction and the lower block in the
vertical direction). Accordingly, it is difficult to operate as a
logic circuit that requires return of data (i.e., feedback of data
to the memory cell from which data was output). In addition, the
optimization of the scale of the memory cell block (e.g., the
number of inputs and the number of outputs) is not described.
SUMMARY OF THE INVENTION
[0009] Accordingly, it is an object of the present invention to
provide a semiconductor device for serving as a memory capable of
functioning as a logic circuit, facilitating feedback of data, and
having an optimum scale of a memory cell block.
[0010] According to an embodiment of the present invention, a
semiconductor device includes a plurality of memory cell blocks,
each including a plurality of memory cells each storing a
predetermined amount of data. Each of the memory cell blocks
stores, in the memory cells thereof, truth table data used for
outputting desired logical values in response to input of a given
address so as to function as a logic circuit. The number of inputs
and the number of outputs of the memory cell block is three or
more, and the memory cell blocks are connected to each other so
that three or more outputs from one memory cell block are input to
other three or more memory cell blocks.
[0011] In a semiconductor device according to the present
invention, a memory that functions as a logic circuit can easily
perform data feedback, and the scale of a memory cell block can be
optimized.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a block diagram of a semiconductor device and an
information processing apparatus according to an embodiment of the
present invention;
[0013] FIG. 2 is an exemplary configuration diagram of a memory
cell which is a storage element of the semiconductor device shown
in FIG. 1;
[0014] FIG. 3 is an exemplary configuration diagram of a memory
cell block;
[0015] FIG. 4 is a connection diagram of readout ports of the
semiconductor device;
[0016] FIG. 5 is an exemplary internal configuration diagram of the
semiconductor device;
[0017] FIG. 6 is an example configuration diagram of a 3-bit
adder;
[0018] FIG. 7A is a schematic illustration of the memory cell
block, and FIG. 7B is a truth table stored in a first memory cell
block group;
[0019] FIG. 8A is a schematic illustration of the memory cell
block, and FIG. 8B is a truth table stored in a second memory cell
block group;
[0020] FIG. 9A is a schematic illustration of the memory cell
block, and FIG. 9B is a truth table stored in a third memory cell
block group;
[0021] FIG. 10 is an exemplary connection diagram of readout ports
of a semiconductor device;
[0022] FIG. 11 is an exemplary internal configuration diagram of
the semiconductor device; and
[0023] FIG. 12 is a flow chart of an exemplary process performed
when bit data is loaded in the semiconductor device that functions
as a logic circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] A semiconductor device according to an embodiment of the
present invention is described below with reference to the
accompanying drawings.
[0025] FIG. 1 is a block diagram of a semiconductor device and an
information processing apparatus according to the present
embodiment. An information processing apparatus 100 is a computer
apparatus. The information processing apparatus 100 includes an
input unit 101 (e.g., a keyboard), a storage unit 102 (e.g., a hard
disk), a memory 103 (e.g., a random access memory (RAM)), an output
unit 104 (e.g., a cathode ray tube (CRT)), a communication unit 105
serving as communication equipment, and a processing unit 106
(e.g., a central processing unit (CPU)).
[0026] Note that bit data generated by the information processing
apparatus 100 (refer to step S1104 shown in FIG. 12 described
below) may be stored in a read only memory (ROM) (not shown).
[0027] A semiconductor device 110 is connected to the communication
unit 105 of the information processing apparatus 100. In terms of
hardware, the semiconductor device 110 is a storage device similar
to a widely used SRAM. The semiconductor device 110 is described in
more detail below with reference to FIG. 2 and the subsequent
drawings.
[0028] FIG. 2 is a configuration diagram of a memory cell which is
a storage element of the semiconductor device 110 shown in FIG. 1.
A memory cell 200 includes read word lines 201 and 202, a write
word line 211, read data lines 221 and 222, write data lines 231
and 232, gates 241, 242, 251, 252, 261, and 262, and a flip-flop
271.
[0029] In this embodiment, the gates 241, 242, 251, 252, 261, and
262 are of a negative-metal oxide semiconductor (N-MOS) type.
However, these gates may be of a positive-metal oxide semiconductor
(P-MOS) type. Furthermore, these gates may be of a complex gate
type including an N-MOS type and a P-MOS type. In such a case,
peripheral circuits can be appropriately changed as needed.
[0030] The read word lines 201 and 202 are interconnection lines to
which a voltage is applied when data is read out from the memory
cell 200. When a voltage is applied to the read word line 201, the
gates 241 and 242 are open. When a voltage is applied to the read
word line 202, the gates 251 and 252 are open.
[0031] The write word line 211 is an interconnection line to which
a voltage is applied when data is written to the memory cell 200.
When a voltage is applied to the write word line 211, the gates 261
and 262 are open.
[0032] The read word lines 221 and 222 are interconnection lines
used for reading out data stored in the flip-flop 271 when a
predetermined voltage is applied to the read word lines 201 and 202
so that the gates 241, 242, 251, and 252 are open. When data 11011
is read out from the read word line 221, data "1" is read out from
the read word line 222. In contrast, when data "1" is read out from
the read word line 221, data "0" is read out from the read word
line 222. In this way, the read word lines 221 and 222 operate as a
differential signal system.
[0033] The write data lines 231 and 232 are interconnection lines
used for writing data to the flip-flop 271 when a voltage is
applied to the write word line 211 so that the gates 261 and 262
are open. When data "0" is written from the write data line 231,
data "1" is written from the write data line 232. In contrast, when
data "1" is written from the write data line 231, data "0" is
written from the write data line 232.
[0034] The flip-flop 271 holds binary data ("0", or "1") stored in
the memory cell 200 in the above-described manner.
[0035] FIG. 3 is a configuration diagram of a memory cell block in
an internal structure of the semiconductor device 110 shown in FIG.
1 (see FIG. 2 if necessary).
[0036] A memory cell block 300 includes a plurality of the memory
cells 200 arranged in an array and connected to each other and read
address decoders 311 and 312. As described above, by disposing the
read address decoders 311 and 312 of the read word lines 201 and
202 on the left and right sides of the memory cell block 300, the
memory cell block 300 can have the following interconnection
function.
[0037] In the memory cell block 300, the read word lines 221 and
222 are connected to another memory cell block 300 (not shown) at
positions located above the uppermost and outer memory cells 200,
that is, the memory cell 200 (Cell31, 0) and the memory cell 200
(Cell31, 3). In addition, the read word lines 221 and 222 are
connected to another memory cell block 300 (not shown) at positions
below the lowermost and inner memory cells 200, that is, the memory
cell 200 (Cell0, 1) and the memory cell 200 (Cell0, 2).
[0038] Furthermore, in the memory cell block 300, the read word
lines 221 and 222 are disconnected at positions located above the
uppermost and inner memory cells 200, that is, the memory cell 200
(Cell31, 1) and the memory cell 200 (Cell31, 2). In addition, the
read word lines 221 and 222 are disconnected at positions located
below the lowermost and outer memory cells 200, that is, the memory
cell 200 (Cell0, 0) and the memory cell 200 (Cell0, 3).
[0039] That is, in the memory cell block 300, pairs of the outer
read data interconnection lines are connected upwardly while pairs
of the inner read data interconnection lines are connected
downwardly. In this way, the scale of the output (readout) of the
memory cell block 300 can be minimized, and therefore, the load of
a variety of data processing can be reduced. In addition, a
plurality of data items can be output in a plurality of
directions.
[0040] In the memory cell block 300, the read address decoder 311
is disposed on the left side so as to receive a plurality of
address differential signals from address input lines 322. In
addition, in the memory cell block 300, the read address decoder
312 is disposed on the right side so as to receive a plurality of
address differential signals from address input lines 323.
[0041] Note that the number of inputs or outputs "three" or "four"
described in the appended claims correspond to three pairs or four
pairs of differential signals.
[0042] In the memory cell block 300, any one of the plurality of
read word lines 331 to 362 (each corresponding to the read word
line 202 shown in FIG. 2) can be selected on the basis of the
inputs from the address input lines 322, the address input lines
323, and a select line 301 (an address selection line that selects
a particular address). Thereafter, a voltage can be applied to the
selected read word line.
[0043] Furthermore, the select line 301 includes an inverter 302.
The read address decoder 311 includes a plurality of logic circuits
370 (e.g., AND circuits). A write word line 371 (corresponding to
the write word line 211 shown in FIG. 2) is connected to a write
address decoder 411 (see FIG. 5).
[0044] Since logic circuits of the read address decoder 312 are
similar to those of the read address decoder 311, the descriptions
thereof are not repeated (for example, a logic circuit 380 is
connected to a read word line 381).
[0045] As shown in FIG. 3, for example, when data "1" is input from
the select line 301, the upper half of the memory cell 200 in the
memory cell block 300 operates. In contrast, when data "0" is input
from the select line 301, the lower half of the memory cell 200 in
the memory cell block 300 operates.
[0046] Accordingly, for example, if the upper half of the memory
cell 200 in the memory cell block 300 serves as an adder and the
lower half of the memory cell 200 serves as a subtractor, switching
between the adder and the subtractor can be conducted
instantaneously by simply switching a signal from the select line
301. Similarly, for example, switching between the adder and an
original storage device can be conducted.
[0047] The memory cell block 300 has been described in detail. As
described above, by arranging the memory cells 200 into a
32.times.4 array and decreasing the lengths of the read word lines
221 and 222 (see FIG. 2), the need for a sense amplifier can be
eliminated. Therefore, the circuits can be simplified.
[0048] FIG. 4 is a connection diagram of readout ports (pairs of
upper and lower outputs of the read data line shown in FIG. 3 and
pairs of inputs from the address input lines 322 and 323) of the
semiconductor device 110 shown in FIG. 1. In FIG. 4, only an upper
left portion of the semiconductor device 110 is illustrated when
viewed in plan.
[0049] In each of memory cell blocks 300d to 300l, an input A0 (for
simplicity, hereinafter simply referred to as "A0", and the same
for "A1" to "A3") represents a combination of A0 and /A0 shown in
FIG. 3. The same applies to A1 to A3.
[0050] In addition, in each of the memory cell blocks 300d to 300l,
an output D0 (for simplicity, hereinafter simply referred to as
"D0", and the same for "D1" to "D3") represents a combination of
two read data lines of the memory cell 200 (Cell31, 0) shown in
FIG. 3. The same applies to D1 to D3.
[0051] A0 to A3 and D0 to D3 of the memory cell blocks 300d to 300l
are connected as shown in FIG. 4.
[0052] A driver circuit 420 converts a signal input from an
external apparatus to this device (the semiconductor device 110)
into a differential signal. In addition, an amplifier 430 amplifies
the input differential signal, and converts the differential signal
to a normal signal. The amplifier 430 then outputs the normal
signal to the external apparatus.
[0053] By making interconnection in such a manner, the
semiconductor device 110 can easily achieve feedback of data. More
specifically, for example, when data is transmitted from D3 of the
memory cell block 300d to A1 of the memory cell block 300g, a truth
table indicating that data input from A1 is output from D1 is
written to the memory cell block 300g. In this way, the data can be
fed back to A3 of the memory cell block 300d.
[0054] In addition, by simply changing truth tables written to the
memory cell blocks 300d to 300l, the semiconductor device 110 can
function as a variety of logic circuit without changing the
interconnection lines.
[0055] Note that the number of turns and the shapes of the turns of
the interconnection lines are not limited to those shown in FIG. 4,
and can be changed as needed.
[0056] FIG. 5 is an internal configuration diagram of the
semiconductor device 110 shown in FIG. 1. The memory cell blocks
300 are arranged in an array. The write address decoder 411 is
disposed on the left side. A write/read circuit 401 is disposed on
the lower side. The write address decoder 411 and the write/read
circuit 401 are connected as shown in the drawing. That is, FIG. 5
is a diagram illustrating a state other than connection of the
readout ports in the semiconductor device 110 similar to that shown
in FIG. 4.
[0057] The write address decoder 411 identifies an x address of the
memory cell block 300 (an address in the vertical direction of the
semiconductor device 110 shown in FIG. 5) when writing data into
the memory cell block 300. An x address for identifying a
particular memory cell block 300 from among the plurality of memory
cell blocks 300 is input to a high address (in this example, A4w,
A5w, A6w . . . ). An x address for identifying an internal location
(one of the memory cells 200) of the identified memory cell block
300 is input to a low address (in this example, A0w to A3w).
[0058] The write/read circuit 401 identifies a y address of the
memory cell block 300 from and to which data is to be read and
written. The write/read circuit 401 then reads and writes data from
and to the identified memory cell block 300.
[0059] More specifically, a y address (an address in the horizontal
direction of the semiconductor device 110 shown in FIG. 5; Ayw2 in
this example) for identifying one of the memory cell blocks 300 is
input to the write/read circuit 401. A y address for identifying an
internal location (one of the memory cells 200) of the identified
memory cell block 300 is then input (in this example, Ayw0 and
Ayw1). In addition, data of a plurality of bits (four bits in this
example) are input from input 402 to the write/read circuit
401.
[0060] In this way, a particular memory cell 200 in a particular
memory cell block 300 can be selected, and the truth table data can
be updated.
[0061] That is, when truth table data stored in the memory cells
200 of one of the memory cell blocks 300 is updated, the
semiconductor device 110 can change the operation thereof in
accordance with the updated truth table data.
[0062] The case where the semiconductor device 110 shown in FIG. 4
is used for a 3-bit adder is described next with reference to FIGS.
6 to 9B.
[0063] FIG. 6 is a configuration diagram of a 3-bit adder. In FIG.
6, connection between memory cell blocks is similar to that shown
in FIG. 4.
[0064] The following description is made with reference to the case
where two 3-bit values E and F are added, and the sum Y is output.
"E0" represents the least significant bit of E. "E1" represents the
next bit. "E2" represents the most significant bit of E. In
addition, "F0" represents the least significant bit of F. "F1"
represents the next bit. "F2" represents the most significant bit
of F. Furthermore, "Y0" represents the least significant bit of Y.
"Y1" represents the next bit. "Y2" represents the most significant
bit of Y. "C0" represents a carry from the least significant bit as
a result of addition. "C1" represents a carry from the next bit as
a result of addition. "C2" represents a carry from the most
significant bit as a result of addition. Although each signal is a
differential signal, the notation is abbreviated for
simplicity.
[0065] In the memory cell block 300d, E0 is input to A0, and F0 is
input to A1. Subsequently, addition is performed. As a result of
the addition, Y0 is output from D3. C0 is output from D2. In the
memory cell block 300e, E1 is input to A0, and F1 is input to A1.
C0 is input to A3. Subsequently, addition is performed. As a result
of the addition, Y1 is output from D3. C1 is output from D2. In the
memory cell block 300f, E2 is input to A0, and F2 is input to A1.
C1 is input to A3. Subsequently, addition is performed. As a result
of the addition, Y2 is output from D3. C2 is output from D2.
[0066] Y0 output from D3 of the memory cell block 300d is output
from D3 of the memory cell block 300j through a route shown in the
drawing. Y1 output from D3 of the memory cell block 300e is output
from D3 of the memory cell block 300k through a route shown in the
drawing. Y2 output from D3 of the memory cell block 300f is output
from D3 of the memory cell block 300l through a route shown in the
drawing. In this way, as a result of the addition, Y0, Y1, and Y2
can be obtained.
[0067] FIG. 7A is a schematic illustration of the memory cell block
300. FIG. 7B illustrates a truth table stored in each of the memory
cell blocks 300d, 300e, and 300f (see FIG. 6 if necessary).
[0068] As shown in FIG. 7A, in the memory cell block 300, when
inputs are fed to A0 to A3, values defined in the truth table are
output from D0 to D3 in accordance with the inputs.
[0069] As shown in FIG. 7B, when E (E0 to E2), F (F0 to F2), and
C.sub.in (C0 to C2) are input to A0, A1, and A3, the three values
are summed. The resultant bit value Y (Y0 to Y2) is output from D3.
A carry C.sub.out (C0 to C2) is output from D2.
[0070] Note that since D0 and D1 are not used in this example, "0"
is output from D0 and D1 at all times. In addition, the first to
fourth rows, fifth to eighth rows, ninth to twelfth rows, and
thirteenth to sixteenth rows have the same pattern of truth values
except for the values of A2. This is because correct outputs can be
obtained even when either of "0" or "1" is input to A2.
[0071] FIG. 8A is a schematic illustration of the memory cell block
300. FIG. 8B illustrates a truth table stored in each of the memory
cell blocks 300g, 300j, 300k, and 300l (see FIG. 6 if
necessary).
[0072] As shown in FIG. 8A, in the memory cell block 300, when
inputs are fed to A0 to A3, values defined in the truth table are
output from D0 to D3 in accordance with the inputs.
[0073] As shown in FIG. 8B, when Y (Y0 to Y2) is input to A1, that
value is directly output from D3. Note that since D0 and D2 are not
used in this example, "0" is output from D0 and D2 at all
times.
[0074] In practice, a truth table having only two types (two rows)
of patterns from A1 to D3 (i.e., patterns of "0" to "0" and "1" to
"1") is required. However, in order to obtain correct output
results even when either value of "0" or "1" is input to A0, A2,
and A3, a truth table of sixteen rows is used.
[0075] FIG. 9A is a schematic illustration of the memory cell block
300. FIG. 9B illustrates a truth table stored in each of the memory
cell blocks 300h and 300i (see FIG. 6 if necessary). As shown in
FIG. 9A, in the memory cell block 300, when inputs are fed to A0 to
A3, values defined in the truth table are output from D0 to D3 in
accordance with the inputs.
[0076] As shown in FIG. 9B, when C (C0 to C2) is input to A0, that
value is directly output from D1. In addition, when Y (Y0 to Y2) is
input to A1, that value is directly output from D3. Note that since
D0 and D2 are not used in this example, "0" is output from D0 and
D2 at all times. In addition, as in the case of FIG. 5B, even when
either value of "0" or "1" is input to A2 and A3, a correct
resultant output value can be obtained.
[0077] FIG. 10 is a connection diagram of the readout ports of a
semiconductor device 110a which is a modification of the
semiconductor device 110 shown in FIG. 4. In the semiconductor
device 110a, memory cell blocks 300m to 300o are disposed in the
leftmost column. Memory cell blocks 300s to 300u are disposed in a
third column from the left. Memory cell blocks 300p to 300r
disposed in a column between the two columns are positionally
shifted by half a memory cell block in the vertical direction. In
addition, A0 to A3 and D0 to D3 of each of these memory cell blocks
are connected as shown in the drawing.
[0078] As described above, by disposing some of the memory cell
blocks while shifting the memory cell blocks, the length of the
interconnection line from one of D0 to D3 of one memory cell block
to a corresponding one of A0 to A3 of another memory cell block can
be reduced, as compared with the semiconductor device 110 shown in
FIG. 4.
[0079] Note that the number of turns and the shapes of the turns of
the interconnection lines are not limited to those shown in FIG.
10, and can be changed as needed. In addition, the internal
structure of the semiconductor device 110a (corresponding to FIG.
5) is shown in FIG. 11.
[0080] As noted above, according to the semiconductor device of the
present embodiment, a memory can function as a logic circuit. By
providing the output from one memory cell block to four memory cell
blocks, feedback of data can be easily achieved.
[0081] In an existing manufacturing process of FPGAs, for example,
a C language program is written, and subsequently, a hardware
description language (HDL) is generated. Thereafter, logic
synthesis is performed using the HDL so that a logic circuit is
generated. Logic modules and interconnection lines are distributed
on an FPGA on the basis of the logic circuit. That is, such
complicated and highly advanced process procedures are
required.
[0082] In contrast, according to the present embodiment, the
semiconductor device functions as a memory or a storage element.
Accordingly, after compiling a C language program, the resultant
data can be loaded into the semiconductor device in the form of a
truth table. Thus, the manufacturing process can be facilitated. In
addition, since the semiconductor device of the present embodiment
functions as a storage element, a different logic circuit can be
achieved by simply changing a truth table written to the memory
cell 200 without changing the interconnection lines.
[0083] This advantage is described in more detail below with
reference to FIG. 12 (see FIG. 1 if necessary). FIG. 12 is a flow
chart of an exemplary process performed when bit data is loaded
into the semiconductor device that functions as a logic
circuit.
[0084] First, in step S1101, the information processing apparatus
100 receives, from the input unit 101, a C language program that
describes a desired function, and stores the C language program in
the storage unit 102. The storage unit 102 prestores programs for
performing a variety of functions (e.g., addition and
subtraction).
[0085] Subsequently, in step S1102, an operator of the information
processing apparatus 100 adds a declaration statement (the
"Include" statements) to the C language program using the input
unit 101 in order to refer to a necessary program prestored in the
storage unit 102.
[0086] In step S1103, the processing unit 106 creates a truth table
(e.g., a truth table 600 shown in FIG. 7) on the basis of the C
language program including the added "Include" statement. In step
S1104, the processing unit 106 generates bit data on the basis of
the truth table. Subsequently, in step S1105, the processing unit
106 loads the bit data into the semiconductor device 110 via the
communication unit 105.
[0087] In this way, according to the present embodiment, the
operation that allows the semiconductor device 110 to function as a
logic circuit can be simplified.
[0088] In addition, according to the semiconductor device of the
present embodiment, since an actual logic circuit is not used,
malfunction of part of the memory can be easily dealt with by, for
example, not using the faulty part.
[0089] Furthermore, if, as described in the present embodiment, 32
word lines are used for one memory cell block, attenuation of data
(signals) can be reduced, and therefore, the need for a sense
amplifier can be eliminated. However, if the performance of the
semiconductor device is critical, the number of the word lines may
be increased to 33 or more by providing an intermediate buffer to
the read sense amplifier or the read data lines.
[0090] Furthermore, according to the semiconductor device of the
present embodiment, by using a plurality of memories and installing
test programs in some of the memories, one of the other memories
can be tested. In addition, after the test is completed, the test
programs are erased from the memories. Thus, these memories can be
used as normal memories.
[0091] Still furthermore, a memory included in a system LSI may be
configured so as to function as the semiconductor device of the
present embodiment. After the memory is self-tested, a C language
test program is written to the memory so that a test logic circuit
is achieved. Thus, other logic circuits in the system LSI can be
tested.
[0092] Yet still furthermore, connection between the memory cell
blocks is not limited to a connection pattern in which one memory
block is connected to four other memory blocks, For example, any
connection to three or more other memory cell blocks that enables
data feedback may be employed. In addition, while the
above-described embodiment has been described with reference to the
differential read data lines, the interconnection may be achieved
using one-side read data lines in accordance with a semiconductor
layout and the logic circuit of a read address decoder.
[0093] While the present invention has been described as carried
out in a specific embodiment thereof, it should be apparent to
those skilled in the art that it is not limited thereto. For
example, according to the present invention, a semiconductor device
may be achieved using a dynamic random access memory (DRAM) or a
flash memory in place of an SRAM.
[0094] Furthermore, in order to improve the performance of the
memories, a function such as a pre-charging function may be
employed.
[0095] Still furthermore, the invention is intended to cover
various modifications and equivalent arrangements included within
the spirit and scope of the appended claims.
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