U.S. patent application number 12/508775 was filed with the patent office on 2009-11-19 for semiconductor chip having gettering layer, and method for manufacturing the same.
This patent application is currently assigned to Renesas Technology Corp.. Invention is credited to Yoshiko Higashide, Tsuyoshi Koga, KAZUHITO MATSUKAWA, Akio Nishida, Jun Shibata, Hiroshi Tobimatsu.
Application Number | 20090286354 12/508775 |
Document ID | / |
Family ID | 35731192 |
Filed Date | 2009-11-19 |
United States Patent
Application |
20090286354 |
Kind Code |
A1 |
MATSUKAWA; KAZUHITO ; et
al. |
November 19, 2009 |
SEMICONDUCTOR CHIP HAVING GETTERING LAYER, AND METHOD FOR
MANUFACTURING THE SAME
Abstract
In a semiconductor chip A wherein an element layer 2 having
transistors and the like is formed on the front face, and the back
face is joined to an underlying member, such as a package
substrate, the thickness T is made 100 .mu.m or less, and
thereafter, a gettering layer 3 is formed on the back face of the
semiconductor chip A. The gettering layer 3 is formed, for example,
by polishing the back face of said semiconductor chip A using a
polishing machine. Thereby, the yield of devices can be improved in
the step for assembling the package.
Inventors: |
MATSUKAWA; KAZUHITO; (Tokyo,
JP) ; Koga; Tsuyoshi; (Tokyo, JP) ; Nishida;
Akio; (Tokyo, JP) ; Higashide; Yoshiko;
(Tokyo, JP) ; Shibata; Jun; (Tokyo, JP) ;
Tobimatsu; Hiroshi; (Tokyo, JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND MAIER & NEUSTADT, L.L.P.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Assignee: |
Renesas Technology Corp.
Tokyo
JP
|
Family ID: |
35731192 |
Appl. No.: |
12/508775 |
Filed: |
July 24, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11190011 |
Jul 27, 2005 |
7582950 |
|
|
12508775 |
|
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|
Current U.S.
Class: |
438/107 ;
257/E21.599; 257/E21.705; 438/113 |
Current CPC
Class: |
H01L 24/73 20130101;
H01L 2224/32225 20130101; H01L 2924/10253 20130101; H01L 2225/06575
20130101; H01L 2224/48091 20130101; H01L 2924/15311 20130101; H01L
2224/73265 20130101; H01L 2224/45144 20130101; H01L 25/0657
20130101; H01L 2224/48471 20130101; H01L 2224/48227 20130101; H01L
2924/15311 20130101; H01L 2224/45144 20130101; H01L 2924/15311
20130101; H01L 2225/06555 20130101; H01L 2224/73265 20130101; H01L
2225/0651 20130101; H01L 2224/73265 20130101; H01L 2224/73265
20130101; H01L 2924/00 20130101; H01L 2224/73265 20130101; H01L
2224/48227 20130101; H01L 2224/32225 20130101; H01L 2224/48227
20130101; H01L 2224/48227 20130101; H01L 2224/32145 20130101; H01L
2224/32225 20130101; H01L 2224/32225 20130101; H01L 2224/48471
20130101; H01L 2924/00 20130101; H01L 2224/32225 20130101; H01L
2924/00012 20130101; H01L 2224/48227 20130101; H01L 2924/00012
20130101; H01L 2924/00 20130101; H01L 2924/00014 20130101; H01L
2224/48227 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/48227 20130101; H01L 2924/00 20130101; H01L 2924/10253
20130101; H01L 2224/73265 20130101; H01L 2924/01079 20130101; H01L
2224/48091 20130101; H01L 2224/32145 20130101 |
Class at
Publication: |
438/107 ;
438/113; 257/E21.705; 257/E21.599 |
International
Class: |
H01L 21/98 20060101
H01L021/98; H01L 21/78 20060101 H01L021/78 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 28, 2004 |
JP |
2004-220319 |
Claims
1. A method for manufacturing a semiconductor package, comprising:
forming an element layer on a front face of a semiconductor wafer,
the element layer including a transistor; dicing the semiconductor
wafer so as to form a first semiconductor chip, after forming the
element layer; polishing a back face of the first semiconductor
chip so as to form a getting layer on the back face, after dicing
the semiconductor wafer; and assembling a semiconductor package
which includes a package substrate, a second semiconductor chip
formed over the package substrate, the first semiconductor chip
being formed over the second semiconductor chip, after polishing
the back face of the first semiconductor chip, wherein the
semiconductor package includes the gettering layer, the gettering
layer is a damaged layer; the damaged layer includes a plurality of
grooves, a thickness of the first semiconductor chip is thinner
than a thickness of the second semiconductor chip, and in plan view
to said first semiconductor chip, each of the grooves is a linear
groove.
2. The method for manufacturing the semiconductor package according
to claim 1, wherein the semiconductor package includes resin and a
spacer, the method comprising: covering the first and second
semiconductor chips and a front face of the package substrate with
the resin, and arranging the spacer between the first semiconductor
chip and the second semiconductor chip.
3. The method for manufacturing the semiconductor package according
to claim 2, wherein: the spacer is a silicon substrate or a
polysilicon film, a back face of the second semiconductor chip
includes a gettering layer, and the semiconductor package includes
a first wire and a second wire, the method comprising: electrically
coupling the first semiconductor chip to the package substrate via
the first wire, and electrically coupling the second semiconductor
chip to the package substrate via the second wire.
4. A method for manufacturing a semiconductor package, comprising:
forming an element layer on a front face of a semiconductor wafer,
the element layer including a transistor; dicing the semiconductor
wafer so as to form a first semiconductor chip, after forming the
element layer; polishing a back face of the first semiconductor
chip so as to form a getting layer on the back face, after dicing
the semiconductor wafer; and assembling a semiconductor package
which includes a package substrate, the first semiconductor chip
being formed over the package substrate, after polishing the back
face of the first semiconductor chip, wherein the semiconductor
package includes the gettering layer, the gettering layer is a
damaged layer, the damaged layer includes a plurality of grooves, a
depth of each of the grooves is 2 to 3 .mu.m, and in a plan view to
said first semiconductor chip, each of the grooves is a linear
groove.
5. The method for manufacturing the semiconductor package according
to claim 4, comprising covering the first semiconductor chip and a
front face of the package substrate with a resin.
6. The method for manufacturing the semiconductor package according
to claim 5, wherein the semiconductor package includes a first
wire, the method comprising electrically coupling the first
semiconductor chip to the package substrate via the first wire.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. application Ser.
No. 11/190,011, filed Jul. 27, 2005, the entire contents of which
are incorporated herein by reference and is based upon and claims
the benefit of priority from prior Japanese Patent Application No.
2004-220319, filed Jul. 28, 2004.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor chip having
a gettering layer for removing impurities such as heavy metals, and
to a method for manufacturing the same.
[0004] 2. Description of the Related Art
[0005] In the manufacture of semiconductor devices, heavy-metal
contamination due to copper and nickel, and the like leads to the
destruction of gate insulation films or the deterioration of
element reliability, and is one of causes to lower the yield of
devices. The heavy-metal contamination occurs not only in the
process for forming an element layer including transistors or the
like on the surface of a wafer (first-half process), but also in
the process for dicing the wafer and assembling the semiconductor
chips into a package (second-half process).
[0006] In order to prevent heavy-metal contamination, it is
effective that a gettering layer for removing (gettering) heavy
metals is previously formed in the part of a wafer or a
semiconductor chip (for example, refer to Japanese Patent Laid-Open
No. 2001-250957, or Japanese Patent Laid-Open No. 56-56660).
[0007] When a package having a structure wherein a plurality of
semiconductor chips are laminated, such as a multi-chip package
(MCP), is used, the thickness of each semiconductor chip must be
thinned in the second-half process in order to raise the
integration degree of the device.
[0008] By doing this, since the gettering layer formed inside or on
the back face of the wafer in the first-half process is lost or
thinned, there have been problems wherein the element layer is
contaminated by heavy metals in the second-half process, and the
yield of devices are lowered due to the defect of the gate
insulation film.
SUMMARY OF THE INVENTION
[0009] The present invention has been devised to solve the
above-described problems, and the object of the present invention
is to provide a semiconductor chip having a gettering layer formed
on the back face of the semiconductor chip for gettering heavy
metals in the second-half process, and a method for manufacturing
such a semiconductor chip.
[0010] The above object is achieved by a semiconductor chip wherein
an element layer is formed on the front face, and the back face is
joined to an underlying member, wherein a gettering layer is formed
on said back face.
[0011] The above object is achieved by a method for manufacturing a
semiconductor chip, wherein a gettering layer is formed on the back
face of a semiconductor chip by mechanically grinding the back face
of said semiconductor chip using a silica material to form a
damaged layer.
[0012] Other objects and further features of the present invention
will be apparent from the following detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a sectional view of a semiconductor chip of the
first embodiment;
[0014] FIG. 2 is a sectional view of a semiconductor chip of the
first embodiment;
[0015] FIG. 3 is a micrograph of the back face of a semiconductor
chip of the first embodiment;
[0016] FIG. 4 is a sectional view of a semiconductor chip of the
second embodiment;
[0017] FIG. 5 is a sectional view of a semiconductor chip of the
third embodiment;
[0018] FIG. 6 is a sectional view of a wafer of the fourth
embodiment;
[0019] FIGS. 7A and 7B are micrographs of a wafer of the fourth
embodiment;
[0020] FIGS. 8A and 8B are micrographs of a wafer of the fourth
embodiment; and
[0021] FIG. 9 is a sectional view of an MCP of the fifth
embodiment.
BEST MODE FOR CARRYING OUT THE INVENTION
[0022] The manufacture of a semiconductor device is completed
through steps for forming an element layer having transistors and
the like on the front face of a wafer and for performing electrical
measurements (hereafter, these steps will be collectively referred
to as the "first-half process"); and steps for cutting
semiconductor chips out of the wafer by dicing, and for assembling
them into a package (hereafter, these steps will be collectively
referred to as the "second-half process"). Although there are
various types of packages, a multi-chip package (hereafter referred
to as "MCP") formed by laminating a plurality of semiconductor
chips is widely used for raising the integration degree of the
device.
[0023] The embodiments of the present invention will be described
below referring to the drawings. In the drawings, the same or
corresponding parts will be denoted by the same reference numerals,
and the description thereof will be simplified or omitted.
First Embodiment
[0024] In the first embodiment, there will be described a
semiconductor chip, wherein an element layer having transistors and
the like is formed on the front face, and the back face is joined
to an underlying member such as an MCP substrate, wherein a
gettering layer is formed on the back face; and a method for the
manufacture thereof.
[0025] First, although not shown in the drawing, in the first-half
process, an element layer (2 to 3 .mu.m) having transistors and the
like is formed on the front face of a wafer of a thickness of 700
to 750 .mu.m, and electrical measurements, such as G/W (good
chip/wafer), are performed.
[0026] Next, the back face of the wafer (the surface opposite to
the surface on which the element layer has been formed) is ground
so that the thickness of the wafer becomes 100 .mu.m or less, for
example, about 90 .mu.m. Thereby, the thickness of a semiconductor
chip subsequently formed can be related to the MCP.
[0027] Then, the semiconductor chip is cut out of the wafer by
dicing. At this time, the thickness of the semiconductor chip is
about 90 .mu.m.
[0028] FIG. 1 is a sectional view of a semiconductor chip A cut out
of the wafer by dicing in the second-half process. The entire
thickness T of the semiconductor chip A is about 90 .mu.m. An
element layer 2 having transistors and the like is formed on the
front face of the semiconductor substrate 1, and a gettering layer
3 for trapping heavy metals is formed on the back face of the
semiconductor chip A. The gettering layer 3 can be a thin film
consisting of a polycrystalline silicon film or a silicon nitride
film, as well as a damaged layer formed by mechanical polishing,
grinding or ion implantation.
[0029] In the semiconductor chip A wherein the element layer 2
having transistors and the like was formed on the front face, a
gettering layer 3 was formed on the back face of the semiconductor
chip A which the back face is joined to an underlying member such
as an MCP substrate. Thereby, heavy metals can be gettered in the
second-half process.
[0030] Thereafter, a plurality of semiconductor chips A (not shown)
are assembled into an MCP. At this time, since the thickness of a
semiconductor chip A was 100 .mu.m or less, the semiconductor chip
A was related to the MCP, and the total thickness of the package
could be thinned. Thereby, the integration degree of the device can
be raised.
[0031] Next, as an example of forming the gettering layer 3 shown
in FIG. 1, an example of forming a damaged layer on the back face
of a semiconductor chip A will be shown.
[0032] The back face of a semiconductor chip A is mechanically
polished using, for example, abrasive grains of a diameter of
several microns consisting of a silica material containing silicon
dioxide (SiO.sub.2) as a major component, to form grooves 3b of a
depth of 2 to 3 .mu.m on the back face of a semiconductor chip A as
FIG. 2 shows.
[0033] Thus, a damaged layer 3a (gettering layer) having grooves 3b
can be formed on the back face of a semiconductor chip A. Thereby,
a gettering layer having a uniform convexo-concave pattern can be
formed.
[0034] FIG. 3 is a micrograph of the back face of a semiconductor
chip A after polishing using the above-described method (refer to
FIG. 2). Linear grooves 3b have been formed on the back face of a
semiconductor chip A.
[0035] The damaged layer 3a shown in FIG. 2 can also be formed by
grinding using grinding tools, such as a diamond wheel, sand blast,
file, and needle. Alternatively, the damaged layer 3a can be formed
using laser beams or focused ion beams (FIB). Thereby, the damaged
layer 3a can be formed using a simple method.
[0036] Here, if the back face of a wafer or a semiconductor chip is
ground to reduce thickness before assembling an MCP, there is a
possibility that the gettering layer previously formed inside or on
the back face of the wafer in the first-half process is lost or
thinned. In addition, the thinner the thickness of a semiconductor
chip, the more sensitive to the effect of heavy-metal contamination
of the back face.
[0037] However, as shown in this embodiment, by forming a gettering
layer 3 on the back face of a semiconductor chip A, heavy metals
can be gettered in the second-half process even if the thickness of
the semiconductor chip A is thinned to 100 .mu.m or less.
[0038] Next, the percent defectives of devices after assembling the
MCP (the lower the percent defectives, the higher the yield of
devices) were compared when the gettering layer 3 was formed and
not formed on the back face of the semiconductor chip A.
[0039] The results showed that when no gettering layer 3 was
formed, the percent defective of the device was 61%, whereas when a
gettering layer 3 was formed, the percent defective of the device
was suppressed to about 0.7%.
[0040] This is considered because heavy-metal contamination was
suppressed, and the percent defectives of devices caused by leakage
current through the gate insulation film or the like were
significantly lowered by the gettering layer 3.
[0041] As described above, in this embodiment, the gettering layer
3 formed on the back face of the semiconductor chip A was a damaged
layer 3a. Thereby, heavy metals can be gettered in the second-half
process. Therefore, the yield in the second-half process can be
improved.
[0042] In this embodiment, the gettering layer 3 could be formed on
the back face of the semiconductor chip A by forming the damaged
layer 3a by mechanically grinding the back face of the
semiconductor chip A using a silica material. Thereby, the
gettering layer having a uniform convexo-concave pattern can be
formed.
[0043] Alternatively, the gettering layer 3 could be formed on the
back face of the semiconductor chip A using a simple method for
forming the damaged layer 3a by grinding back face of the
semiconductor chip A using a grinder.
Second Embodiment
[0044] In this embodiment, as an example of forming the gettering
layer 3 described in the first embodiment, an example of forming a
damaged layer by ion implantation will be described.
[0045] FIG. 4 is a sectional view of a semiconductor chip A after a
damaged layer 3c has been formed as the gettering layer 3 shown in
FIG. 1 on the back face of the semiconductor chip A by ion
implantation. (In FIG. 4, for the convenience of description, the
back face of the semiconductor chip A was upside.)
[0046] The damaged layer 3c can be formed by ion implantation, for
example, using ionic species, such as Ar.sup.+, P.sup.+, and
BF.sub.2, at an implanting energy of 50 to 100 keV or equivalent,
and an implanting dose of 1.times.10.sup.13 to 1.times.10.sup.14
atoms/cm.sup.2.
[0047] Alternatively, by controlling the implanting energy or
implanting dose of ion implantation, the density of crystal lattice
defect can also be controlled. Thereby, the gettering capacity can
be improved as required.
[0048] In this embodiment, as described above, the gettering layer
3 formed on the back face of the semiconductor chip A was a damaged
layer 3c formed on the back face of the semiconductor chip A by ion
implantation. Thereby, in addition to the effect obtained in the
first embodiment, the gettering capacity can be improved as
required.
[0049] In this embodiment, a gettering layer 3 was formed on the
back face of the semiconductor chip A by forming a damaged layer 3c
by implanting ions into the back face of the semiconductor chip A.
By thus forming, a gettering layer having an improved gettering
capacity as required be controlling the implanting energy or
implanting dose of ion implantation.
Third Embodiment
[0050] In this embodiment, as an example of forming the gettering
layer 3 described in the first embodiment, an example of forming a
thin film will be described.
[0051] FIG. 5 is a sectional view of a semiconductor chip A after
forming a thin film 3d as a gettering layer 3 shown in FIG. 1 on
the back face of the semiconductor chip A.
[0052] As the thin film 3d, a polycrystalline silicon film or a
silicon nitride film is formed by low-temperature CVD at, for
example, about 350.degree. C. to 400.degree. C. Thereby, the
gettering layer can be formed by a simple method without affecting
the characteristics of transistors and the like.
[0053] The thickness of the thin film 3d is about 1 .mu.m,
preferably within a range between, for example, 0.5 and 1.5 .mu.m.
This is because if the film thickness is thinner than 0.5 .mu.m,
there is possibility that heavy metals cannot be sufficiently
gettered; and if the film thickness is thicker than 1.5 .mu.m,
there is possibility that defect is caused in the second-half
process, such as poor bonding due to film stress.
[0054] By thus forming a thin film 3d on the back face of the
semiconductor chip A, a gettering layer having a uniform thickness
can be formed. Thereby, uniform and stable gettering can be
performed against heavy metals.
[0055] In this embodiment, as described above, the gettering layer
3 formed on the back face of the semiconductor chip A was a thin
film 3d consisting of a polycrystalline silicon film or a silicon
nitride film. Thereby, in addition to the effect obtained by the
first embodiment, uniform and stable gettering can be
performed.
[0056] In this embodiment, a gettering layer 3 was formed on the
back face of the semiconductor chip A by forming a thin film 3d
consisting of a polycrystalline silicon film or a silicon nitride
film on the back face of the semiconductor chip A. Thereby, a
gettering layer 3 having a uniform thickness can be formed.
Fourth Embodiment
[0057] In this embodiment, a semiconductor chip wherein an element
layer having transistors and the like on the front face, and the
back face is joined to the underlying member such as an MCP
substrate, wherein crystal lattice defect is previously formed
inside of the wafer before forming an element layer in the
first-half process; and a method for manufacturing such a
semiconductor chip.
[0058] FIG. 6 is a sectional view of a wafer B, after a crystal
lattice defect layer 4 has been formed inside the wafer B in the
first-half process, then, forming an epitaxial layer 5 on the front
face of the wafer B, and then, forming an element layer 2 having
transistors and the like on the front face thereof. The wafer B is
a p-type silicon wafer having a resistivity of 10 to 15 m.OMEGA.cm
due to the addition of boron, and a total thickness T.sub.1 of 700
to 750 .mu.m.
[0059] Next, a method for forming a crystal lattice defect layer 4
and an epitaxial layer 5 shown in FIG. 6 will be described.
[0060] First, by a first heat treatment, a crystal lattice defect
layer 4 is formed at the location of a depth T2 (about 50 to 80
.mu.m) from the front face of a wafer B. The first heat treatment
is performed in a nitrogen gas or argon gas atmosphere having a
2-step treatment wherein after heat treatment at 500 to 600.degree.
C. for 1 to 2 hours, heat treatment is performed at 900 to
1000.degree. C. for 2 to 3 hours. At this time, the temperature and
treating time in each step are controlled so that the density of
crystal defect formed inside the wafer B becomes
1.times.10.sup.4/cm.sup.2 or more.
[0061] Next, by a second heat treatment, an epitaxial layer 5 of a
thickness of about 5 to 10 .mu.m is formed on the front face of the
wafer B. The second heat treatment is performed in a mixed-gas
atmosphere of SiH.sub.4 (monosilane) and hydrogen at 1100 to
1150.degree. C. for about 10 minutes. Thereby, the epitaxial layer
5 having a resistivity of 2 to 20 m.OMEGA. cm is formed on the
front face of the wafer B. Furthermore, an element layer 2 of a
thickness of about 2 to 3 .mu.m having transistors and the like is
formed on the surface of the epitaxial layer 5.
[0062] Thereafter, a semiconductor chip of a thickness of about 90
.mu.m (not shown) is formed by dicing the wafer B. At this time,
since the crystal lattice defect layer 4 has been formed at the
location about 50 to 80 .mu.m from the front face of the wafer B,
the density of the crystal lattice defects contained in the entire
semiconductor chip is 1.times.10.sup.4/cm.sup.2 or more even after
dicing.
[0063] Thus, a crystal lattice defect layer having a density of the
crystal lattice defects of 1.times.10.sup.4/cm.sup.2 or more was
previously formed inside the wafer B before forming the element
layer so that the density of the crystal lattice defects contained
in the entire semiconductor chip finally formed became
1.times.10.sup.4/cm.sup.2 or more.
[0064] FIG. 7A is a micrograph of the wafer after above-described
first and second heat treatments; and FIG. 7B is a micrograph of
the wafer without either heat treatment (prior art).
[0065] By the comparison of both wafers, it is seen that a crystal
lattice defect layer having a convexo-concave pattern formed by
heat treatments is formed inside the wafer B. The density of the
crystal lattice defects of the wafer shown in FIG. 7A is
5.1.times.10.sup.6/cm.sup.2.
[0066] Here, by performing heat treatment in an argon or hydrogen
atmosphere at 1200 to 1300.degree. C. instead of the step for
forming the epitaxial layer 5 by the above-described second heat
treatment, a non-defect layer (not shown) of a thickness of 5 to 20
.mu.m can be formed on the front surface of wafer B.
[0067] FIG. 8A is a micrograph of the wafer after the
above-described first heat treatment and the heat treatment for
forming the non-defect layer; and FIG. 8B is a micrograph of the
wafer without either heat treatment (prior art).
[0068] By the comparison of both wafers, it is seen that a crystal
lattice defect layer having a convexo-concave pattern formed by
heat treatments is formed inside the wafer B. The density of the
crystal lattice defects of the wafer shown in FIG. 8A is
4.5.times.10.sup.5/cm.sup.2.
[0069] Thus, in the first-half process, a crystal lattice defect
layer is formed at the location about 50 to 80 .mu.m from the front
face inside the wafer so that the density of crystal lattice
defects contained in the entire wafer becomes
1.times.10.sup.4/cm.sup.2 or more. Thereby, even after the wafer
has been diced to form a semiconductor chip having a thickness of
100 .mu.m or less, a semiconductor chip having a density of crystal
lattice defects contained in the entire semiconductor chip of
1.times.10.sup.4/cm.sup.2 or more can be obtained.
[0070] The percentage defect of the device after assembling an MCP
using this semiconductor chip was substantially equivalent to the
percentage defect of the device (0.5%) when a gettering layer was
formed on the back face of the semiconductor chip.
[0071] This is considered because the crystal lattice defects
contained in the semiconductor chip has a gettering effect in the
second-half process.
[0072] In this embodiment, before forming an element layer in the
first-half process, crystal lattice defects were previously formed
inside the wafer so that the density of crystal lattice defects
contained in the semiconductor chip finally formed became
1.times.10.sup.4/cm.sup.2 or more. In addition to this, a gettering
layer may be formed on the back face of the semiconductor chip
using the method shown in any of embodiments 1 to 3. Thereby, since
the gettering effect in the second-half process is improved, the
yield of devices in the second-half process can be further
improved.
[0073] In this embodiment, as described above, after forming a
crystal lattice defect layer 4 by the heat treatment of a wafer B
so that the density of crystal lattice defects contained in the
wafer became 1.times.10.sup.4/cm.sup.2 or more, an element layer 2
was formed and the wafer B was diced to form a semiconductor chip
having a density of crystal lattice defects of
1.times.10.sup.4/cm.sup.2 or more.
[0074] The semiconductor chip was thus formed so that a crystal
lattice defect layer is contained inside the semiconductor chip,
and the density of crystal lattice defects contained in the entire
semiconductor chip became 1.times.10.sup.4/cm.sup.2 or more.
[0075] By this forming, the yield in the second-half process can
also be improved.
Fifth Embodiment
[0076] In this embodiment, there will be described a method for
improving the yield of devices when a plurality of semiconductor
chips are laminated in the step for assembling an MCP. In the MCP,
although three or more semiconductor chips can be laminated on a
substrate of the package, here, to simplify the description, an
example wherein two semiconductor chips are laminated will be
chiefly described.
[0077] FIG. 9 is a sectional view of an MCP formed by laminating
two semiconductor chips having two different thicknesses. An MCP
substrate 7 is fixed on solder balls 6, and a resin 8 is
encapsulated inside the entire MCP. A lower semiconductor chip 10
is fixed on the MCP substrate 7 through an adhesive layer 9.
Further thereon, an upper semiconductor chip 12 is laminated
through adhesive layers 9 and a spacer 11. Wiring terminals 13a and
13b are installed on the lower semiconductor chip 10 and the upper
semiconductor chip 12, respectively, which are connected to wiring
terminals 15a and 15b on the MCP substrate 7 by gold wires 14a and
14b, respectively.
[0078] At this time, the lower semiconductor chip on the MCP
substrate 7 is laminated so that the thickness thereof is
relatively larger than the thickness of the upper semiconductor
chip laminated immediately above it. In other words, in the MCP
shown in FIG. 9, when the thickness of the upper semiconductor chip
12 is X .mu.m, and the thickness of the lower semiconductor chip 10
is Y .mu.m, the relation is X<Y.
[0079] When three or more semiconductor chips are laminated in an
MCP, the thickness of the semiconductor chip fixed on the substrate
of the MCP is made relatively larger than the thickness of the
semiconductor chip fixed immediately above it.
[0080] By the above-described method, the percentage defects of
devices were compared in the step for assembling two semiconductor
chips having different thicknesses into an MCP.
[0081] In FIG. 9, when the thickness of the upper semiconductor
chip 12, X=150 .mu.m, and the thickness of the lower semiconductor
chip 10, Y=90 .mu.m (X>Y), the percentage defect of the device
was 62.5%. Whereas, when X=90 .mu.m and Y=150 .mu.m (X<Y), the
percentage defect of the device was 1.2%, and the percentage defect
of the device could be significantly lowered.
[0082] This is considered because when the thickness of the lower
semiconductor chip is relatively larger than thickness of the upper
semiconductor chip, the stress imparted by the upper semiconductor
chip to the lower semiconductor chip can be relaxed. Thereby, the
yield of devices in the step for assembling the MCP can be
improved.
[0083] In addition, as FIG. 9 shows, a silicon substrate or a
polycrystalline silicon film was laminated as a spacer 11
(cushioning material) between the lower semiconductor chip 10 on
the MCP substrate 7 and the upper semiconductor chip 12 laminated
immediately above it. For example, a thin film formed by recovering
and polishing a P-type silicon substrate containing a P-type
impurity, such as boron, or a dummy wafer containing an N-type
silicon substrate consisting of an N-type impurity, such as
phosphorus, so that the resistivity becomes 1 to 100 .OMEGA.cm, is
used. Alternatively, a polycrystalline silicon film having a
resistivity of 1 to 100 .OMEGA.cm is used. Thereby, since the
spacer 11 can getter heavy metals in the step for assembling the
MCP, the yield of devices in this step can be further improved.
[0084] In order to raise the integration degree of devices
including the entire package, it is preferred to reduce the
thickness of the entire MCP. Therefore, the above-described spacer
11 is preferably formed to be thin. However, if the spacer 11 is
excessively thin, the gettering effect is reduced; therefore, the
spacer 11 is formed so as to have a film thickness of 50 to 100
.mu.m.
[0085] Since the spacer 11 acts as a cushioning material between
the lower semiconductor chip 10 and the upper semiconductor chip
12, the stress imparted by the upper semiconductor chip 12 to the
lower semiconductor chip 10 can be relaxed. Thereby, the yield of
devices in the step for assembling the MCP can be further
improved.
[0086] As a semiconductor chip mounted in the MCP, a semiconductor
chip having a gettering layer formed on the back face shown in the
first to fourth embodiments, or a semiconductor chip having a
density of crystal lattice defect contained inside the
semiconductor chip of 1.times.10.sup.4/cm.sup.2 or more can also be
used. By using such a semiconductor chip, since the gettering
effect in the second-half process is improved, the yield of devices
in the step for assembling the MCP can be further improved.
[0087] In this embodiment, as described above, in a semiconductor
package formed by laminating a plurality of semiconductor chips on
an MCP substrate 7, the thickness of the lower semiconductor chip
on the MCP substrate 7 was relatively larger than the thickness of
the upper semiconductor chip laminated immediately above it.
Thereby, the stress imparted by the upper semiconductor chip to the
lower semiconductor chip can be relaxed, and the yield of devices
in the step for assembling the MCP can be improved.
* * * * *