U.S. patent application number 12/510584 was filed with the patent office on 2009-11-19 for semiconductor device having insulated gate bipolar transistor.
This patent application is currently assigned to MITSUBISHI DENKI KABUSHIKI KAISHA. Invention is credited to Eisuke SUEKAWA.
Application Number | 20090283862 12/510584 |
Document ID | / |
Family ID | 35308580 |
Filed Date | 2009-11-19 |
United States Patent
Application |
20090283862 |
Kind Code |
A1 |
SUEKAWA; Eisuke |
November 19, 2009 |
SEMICONDUCTOR DEVICE HAVING INSULATED GATE BIPOLAR TRANSISTOR
Abstract
One of the aspects of the present invention is to provide a
semiconductor device, which includes a semiconductor layer of a
first conductive type having first and second surfaces. The
semiconductor layer includes a base region of a second conductive
type formed in the first surface and an emitter region of the first
conductive type formed in the base region. Also, the semiconductor
device includes a buffer layer of the first conductive type formed
on the second surface of the semiconductor layer, and a collector
layer of the second conductive type formed on the buffer layer. The
buffer layer has a maximal concentration of the first conductive
type impurity therein of approximately 5.times.10.sup.15 cm.sup.-3
or less, and the collector layer has a maximal concentration of the
second conductive type impurity therein of approximately
1.times.10.sup.17 cm.sup.-3 or more. Further, the ratio of the
maximal concentration of the collector layer to the maximal
concentration of the buffer layer being greater than 100. The
collector layer has a thickness of approximately 1 .mu.m or
less.
Inventors: |
SUEKAWA; Eisuke; (Tokyo,
JP) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Assignee: |
MITSUBISHI DENKI KABUSHIKI
KAISHA
Tokyo
JP
|
Family ID: |
35308580 |
Appl. No.: |
12/510584 |
Filed: |
July 28, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11108694 |
Apr 19, 2005 |
|
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|
12510584 |
|
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|
Current U.S.
Class: |
257/577 ;
257/146; 257/197; 257/E27.019 |
Current CPC
Class: |
H01L 29/7395 20130101;
H01L 2224/49111 20130101; H01L 2224/0603 20130101; H01L 29/0834
20130101; H01L 2224/48091 20130101; H01L 2224/49175 20130101; H01L
2224/48091 20130101; H01L 2924/00 20130101; H01L 2924/00014
20130101; H01L 2924/13055 20130101; H01L 2924/13055 20130101 |
Class at
Publication: |
257/577 ;
257/146; 257/197; 257/E27.019 |
International
Class: |
H01L 27/06 20060101
H01L027/06 |
Foreign Application Data
Date |
Code |
Application Number |
May 13, 2004 |
JP |
2004-143360 |
Feb 21, 2005 |
JP |
2005-043908 |
Claims
1-13. (canceled)
14. A semiconductor device, comprising: a semiconductor layer of a
first conductive type having first and second surfaces, said
semiconductor layer including a base region of a second conductive
type formed on the first surface and an emitter region of the first
conductive type formed in said base region; a buffer layer of the
first conductive type formed on the second surface of said
semiconductor layer, said buffer layer including a collector region
of the second conductive type formed in said buffer layer; and at
least one guard-ring of a second conductive type formed in said
buffer layer for surrounding said collector region.
15. The semiconductor device according to claim 14, further
comprising a diode connected in series with said collector region
via a wire.
16. The semiconductor device according to claim 14, further
comprising a first diode layer of the first conductive type on said
buffer layer, and a second diode layer of the second conductive
type on the first diode layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1) Technical Field of the Invention
[0002] The present invention relates to a semiconductor device used
for an inverter device, and in particular, relates to the
semiconductor device suppressing an operation of a parasitic
transistor, thereby reducing the power loss and improving the
ruggedness.
[0003] 2) Description of Related Arts
[0004] An inverter device uses a half-bridge circuit including an
Insulated Gate Bipolar Transistor (IGBT) and a Free Wheel Diode
reversely connected in parallel. In the art of the present
invention, several semiconductor devices used for the inverter
device have been proposed.
[0005] For example, a Japanese Patent Laid-Open Publication
Application JPA 2001-332729 discloses a transistor operating in a
bipolar mode which can reduce ON-resistance while reducing a
turn-off loss even at high temperature by controlling thickness and
peak impurity concentration of an n-type buffer layer and a p-type
emitter layer.
[0006] Also, according to another Japanese Patent Laid-Open
Publication Application JPA 2002-299623, a high breakdown-voltage
semiconductor device is proposed, in which the conduction power
loss can be stabilized. The ratio of the impurity quantity doped
within the n-type buffer layer to the impurity quantity doped
within the p-type emitter layer falls within a range from 2.5
through 8.2 so as to reduce the variation of the conduction power
loss even when the impurity quantity of those layers substantially
vary.
[0007] Further, another Japanese Patent Laid-Open Publication
Application JPA 04-240775 provides a triode semiconductor device
including an emitter short-circuit structure having a buffer layer
intervened between an anode-emitter region and a base region,
thereby to improve the trade-off relationship between turn-on and
turn-off characteristics.
[0008] In addition, another Japanese Patent Laid-Open Publication
Application JPA 10-050724 suggests an IGBT having a short-lifetime
region obtained by an ion radiation, in which the ion radiation is
processed substantially across the undepleted region so as to
suppress a tail current at a low voltage without reducing the
breakdown voltage and increasing leakage current and
ON-voltage.
[0009] As above, the inverter device used for electric trains or
industries incorporates the IGBT of a high breakdown voltage which
may exceed 4.5 kV, and includes a fairly thick n-type drift layer
for ensuring the high breakdown voltage. Still, a transient
ON-voltage applied across the FWD due to the electromotive force of
the inductive load may be raised up to several hundreds volts
higher than the reverse breakdown voltage of the IGBT, which allows
the reverse current from the emitter to collector electrode. Thus,
the transient ON-voltage across the FWD may severely affect the
induction load operation of the IGBT.
[0010] FIG. 14 illustrates a circuit diagram of a conventional
power converting circuit incorporating a half-bridge circuit
structure. FIG. 15 shows a set of timing diagrams of outputs when
the half-bridge circuit structure is used for the induction
load.
[0011] In the half-bridge circuit structure of FIG. 14, when the
IGBT 2 turns off (switching from ON-state to OFF-state, i.e., Stage
II to Stage III), a forward voltage is applied across the FWD and a
forward current (recovery current) I.sub.1 runs through the FWD.
Such a forward voltage has the transient voltage up to several
hundreds volts, thus, the IGBT 1 having insufficient reverse
breakdown voltage may have an avalanche current I.sub.2 from the
emitter to collector electrode with the transient voltage applied
thereto.
[0012] After the recovery operation of the FWD, when the IGBT 2
again turns on (switching from OFF-state to ON-state, i.e., Stage
III to Stage IV), the avalanche current I.sub.2 serves as a
base-current of a parasitic pnp transistor (pnp-Tr) triggering the
parasitic pnp-Tr current running through the IGBT 1. In conjunction
with the recovery current of the FWD, the parasitic pnp-Tr current
leads the power loss of the IGBT 1, the turn-off loss of the power
converting circuit (IGBT 2), and the recovery loss of the IGBT 1
and the FWD.
[0013] The present inventors addresses the aforementioned problems
by suppressing the parasitic pnp-Tr current of the IGBT with two
approaches as indicated below;
[0014] a) The reverse breakdown voltage of the IGBT is improved to
suppress the avalanche current I.sub.2 of the IGBT 1 generated at
the turning-on of the IGBT 2 (Stage III), which serves as the
base-current of a parasitic pnp-Tr triggering the parasitic pnp-Tr
current of the IGBT 1.
[0015] b) Even where the avalanche current I.sub.2, i.e., the
base-current of the parasitic pnp-Tr is generated, the parasitic
pnp-Tr is not likely to be acted or switched on. In particular, the
IGBT is provided with a short carrier-lifetime region to the extent
not to increase the operating voltage of the IGBT.
SUMMARY OF THE INVENTION
[0016] One of the aspects of the present invention is to provide a
semiconductor device, which includes a semiconductor layer of a
first conductive type having first and second surfaces. The
semiconductor layer includes a base region of a second conductive
type formed in the first surface and an emitter region of the first
conductive type formed in the base region. Also, the semiconductor
device includes a buffer layer of the first conductive type formed
on the second surface of the semiconductor layer, and a collector
layer of the second conductive type formed on the buffer layer. The
buffer layer has a maximal concentration of the first conductive
type impurity therein of approximately 5.times.10.sup.15 cm.sup.-3
or less, and the collector layer has a maximal concentration of the
second conductive type impurity therein of approximately
1.times.10.sup.17 cm.sup.-3 or more. Further, the ratio of the
maximal concentration of the collector layer to the maximal
concentration of the buffer layer being greater than 100. The
collector layer has a thickness of approximately 1 .mu.m or
less.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention more fully be understood from the
detailed description given herein and accompanying drawings which
are given by way of illustration only, and thus are not limitative
of the present invention.
[0018] FIG. 1 is a cross section of an Insulated Gate Bipolar
Transistor (IGBT) according to Embodiment 1 of the present
invention.
[0019] FIG. 2 is a chart showing an impurity concentration profile
of the IGBT according to Embodiment 1 of the present invention.
[0020] FIGS. 3A-3C are graphs illustrating the relationship between
the peak impurity concentration in the n.sup.+-buffer and
p.sup.+-collector layers and reverse breakdown voltages.
[0021] FIGS. 4A-4C are graphs illustrating the relationship between
the peak impurity concentration in the n.sup.+-buffer and
p.sup.+-collector layers and saturation voltages.
[0022] FIG. 5 is a graph illustrating the relationship between the
reverse breakdown voltage of the IGBT and the parasitic pnp-Tr
current.
[0023] FIG. 6 is a cross section of another IGBT according to
Embodiment 2 of the present invention.
[0024] FIG. 7 is a cross section of another IGBT according to
Embodiment 3 of the present invention.
[0025] FIG. 8 is a graph illustrating the relationship between the
depth of short carrier-lifetime region and the operating
voltage/the parasitic pnp-Tr current.
[0026] FIG. 9 is a cross section of another IGBT according to
Embodiment 4 of the present invention.
[0027] FIG. 10 is a cross section of another IGBT according to
Embodiment 5 of the present invention.
[0028] FIG. 11 is circuit diagram of another semiconductor device
according to Embodiment 6 of the present invention.
[0029] FIG. 12 is a top plan view of the IGBT according to
Embodiment 6 of the present invention.
[0030] FIG. 13 is a cross section of another IGBT according to
Embodiment 6 of the present invention.
[0031] FIG. 14 is a circuit diagram of a conventional power
converting circuit with a half-bridge circuit.
[0032] FIG. 15 is a timing diagram showing outputs of the power
converting circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0033] Referring to the attached drawings, the details of
embodiments according to the present invention will be described
herein. In those descriptions, although the terminology indicating
the directions (for example, "top" and "bottom") are conveniently
used just for clarity, it should not be interpreted that those
terminology limit the scope of the present invention. Also, it
should be noted that the conductive type of polarity such as p-type
and n-type in the semiconductor can arbitrarily be replaced to each
other.
Embodiment 1
[0034] Referring to FIGS. 1-5, an Insulated Gate Bipolar Transistor
(IGBT) 100 according to Embodiment 1 of the present invention will
be described herein. The IGBT 100 includes, in general, an
n.sup.+-type buffer layer 1 of semiconductor material such as
silicon and an n.sup.--type drift layer 2 formed thereon. As
illustrated in FIG. 1, the n.sup.--type drift layer 2 includes a
p-type base region 3 selectively formed therein, which also
includes an n-type emitter region 4 selectively formed. Also, a
gate electrode 7 is formed above at least an edge portion of the
n-type emitter region 4, the p-type base region 3, and the
n.sup.--type drift layer 2, via a gate oxide layer 6. Further, an
emitter electrode 5 is formed on and contacting with the n-type
emitter region 4 and the p-type base region 3.
[0035] Formed on the bottom surface of the n.sup.+-type buffer
layer 1 is a p.sup.+-type collector layer 8, also on which in turn
a collector electrode 9 is formed. The emitter electrode 5, the
gate electrode 7, and the collector electrode 9 are made of
material such as aluminum.
[0036] Next, the operation of the IGBT 100 according to the present
embodiment will be described herein. Once a voltage is applied
between the gate electrode 7 and the emitter electrode 5, the
p-type base region 3 serves as a channel region so that a forward
base current runs between the n.sup.--type drift layer 2 and the
n-type emitter region 4 through the p-type base region 3. The
forward base current triggers the IGBT 100 to turn on, allowing the
current between the collector electrode 9 and the emitter electrode
5. On the other hand, no voltage or a negative voltage applied
between the collector electrode 9 and the emitter electrode 5 turns
off the IGBT 100.
[0037] FIG. 2 is a chart showing an impurity concentration profile
along the vertical direction of the IGBT 100 according to
Embodiment 1, i.e., the p.sup.+-type collector layer 8, the
n.sup.+-type buffer layer 1, and the n.sup.--type drift layer 2.
The horizontal and vertical axes represent the impurity
concentration and the chip depth, respectively.
[0038] According to the IGBT 100 of the present embodiment, the
n.sup.+-type buffer layer 1 is designed to have the peak (maximal)
impurity concentration of 5.times.10.sup.15 cm.sup.-3 or less, and
the p.sup.+-type collector layer 8 is designed to have the surface
(maximal) impurity concentration of 1.times.10.sup.17 cm.sup.-3 or
more. Further, the buffer layer 1 and the collector layer 8 are
formed such that the ratio of the surface impurity concentration of
the collector layer 8 to the peak impurity concentration of the
buffer layer 1 is greater than 100. Also, the p.sup.+-type
collector layer 8 has the diffusion depth of 1 .mu.m or more.
[0039] As will be described herein in detail, the IGBT 100 so
structured can improve the reverse breakdown voltage allowing the
reverse current from the emitter to collector electrode, without
deteriorating characteristics of the forward breakdown voltage and
the operating voltage.
[0040] FIGS. 3A-3C illustrate the relationship between the peak
(maximal) impurity concentration (CS(N.sup.+)) of the N.sup.+-type
buffer layer 1 and the reverse breakdown voltage for several IGBTs
including the p.sup.+-type collector layers 8 of which maximal
impurity concentration (CS(P.sup.+)) vary. Also, FIGS. 3A-3C show
the relationship where the p.sup.+-type collector layer 8 has the
vertical thickness Xj of 0.5 .mu.m, 1.0 .mu.m, and 2.0 .mu.m,
respectively.
[0041] As shown in FIGS. 3A-3C, while the relationship does not
much depend on the thickness Xj of the p.sup.+-type collector layer
8. However, the reverse breakdown voltage of the IGBT is generally
decreased as the peak impurity concentration of the N.sup.+-type
buffer layer 1 (CS (N.sup.+)) is increased.
[0042] Meanwhile, FIG. 5 illustrates the relationship between the
reverse breakdown voltage of the IGBT 100 and the relative
parasitic pnp-Tr current, where the parasitic pnp-Tr current is set
to one (1.0) at the reverse breakdown voltage of about 40 volts of
the conventional IGBT 1. In FIG. 5, in order to realize the
parasitic pnp-Tr current of 65% or less of the conventional one,
the reverse breakdown voltage should be about 90 volts or more.
[0043] Back to FIGS. 3A-3C, in order to obtain the reverse
breakdown voltage of about 90 volts or more, the peak impurity
concentration of the N.sup.+-type buffer layer 1 has to be
5.times.10.sup.15 cm.sup.-3 or less.
[0044] Also, FIGS. 4A-4C illustrate the relationship between the
peak (maximal) impurity concentration (CS(N.sup.+)) of the
N.sup.+-type buffer layer 1 and the saturation voltage (operating
voltage) for several IGBTs including the p.sup.+-type collector
layers 8 of which maximal impurity concentration (CS(P.sup.+))
vary, where the p.sup.+-type collector layer 8 has the vertical
thickness Xj of 0.5 .mu.m, 1.0 .mu.m, and 2.0 .mu.m,
respectively.
[0045] As shown in FIGS. 4A-4C, the maximal impurity concentration
(CS(P.sup.+)) and the thickness Xj of the p.sup.+-type collector
layer 8 fairly gives an impact to the saturation voltage especially
at the thickness Xj of 0.5 .mu.m (FIG. 4A). In particular, the
saturation voltage shown in FIGS. 4B and 4C are less influenced by
the thickness Xj of 1.0 .mu.m and 2.0 .mu.m. In particular, when
the p.sup.+-type collector layer 8 has the peak impurity
concentration of 1.times.10.sup.17 cm.sup.-3 or more, the
saturation voltage can be controlled within a stable and/or narrow
range.
[0046] Therefore, according to the IGBT 100 including the
N.sup.+-type buffer layer with the peak impurity concentration of
5.times.10.sup.15 cm.sup.-3 or less, the p.sup.+-type collector
layer 8 have the thickness Xj of 1.0 .mu.m or more and the
p.sup.+-type collector layer 8 has the maximal impurity
concentration (CS(P.sup.+)) of 1.times.10.sup.17 cm.sup.-3 or more
so that the saturation voltage can be controlled within a stable
and/or narrow range.
[0047] Preferably, the p.sup.+-type collector layer 8 is designed
to have the maximal impurity concentration (CS(P.sup.+)) of
5.times.10.sup.17 cm.sup.-3 or more, so that the ratio of the
surface impurity concentration of the collector layer 8 to the peak
impurity concentration of the buffer layer 1 is greater than 100.
Thus, the saturation voltage can be controlled within a more stable
and/or narrower range.
[0048] To this end, the IGBT having the improved reverse breakdown
voltage and the stable saturation voltage can be realized by
controlling the peak (maximal) impurity concentration (CS(N.sup.+))
of the N.sup.+-type buffer layer 1 as being of 5.times.10.sup.15
cm.sup.-3 or less and the maximal impurity concentration
(CS(P.sup.+)) of the p.sup.+-type collector layer 8 as being of
1.times.10.sup.17 cm.sup.-3 or more, preferably, by controlling the
ratio of the surface impurity concentration of the collector layer
8 to the peak impurity concentration of the buffer layer 1 as being
greater than 100, and by designing the thickness Xj of the
p.sup.+-type collector layer 8 as being of 1.0 .mu.m or more.
[0049] This reduces the avalanche current of the IGBT 1, i.e., the
base current of the parasitic pnp-transistor generated when the
IGBT 2 turns off, thereby reducing the power loss and improving the
ruggedness of the IGBT.
[0050] As described above, when the reverse voltage is applied with
the PN junction consisting of the N.sup.+-type buffer layer 1 and
the p.sup.+-type collector layer 8, the suppression of the peak
(maximal) impurity concentration (CS(N.sup.+)) of the N.sup.+-type
buffer layer 1 forms an expanded depletion region in the
N.sup.+-type buffer layer 1 for reducing the electric field
strength in the depletion region so that the avalanche current can
be reduced. Also, the increase of the maximal impurity
concentration (CS(P.sup.+)) of the p.sup.+-type collector layer 8
reduces the resistance of the collector layer 8 thereby reducing
the saturation voltage (dropping voltage in the operating
ON-state). Therefore, the IGBT having the improved reverse
breakdown voltage can be realized without increasing the operating
voltage (saturation voltage).
[0051] When the IGBT 1 so structured is incorporated into the
circuit shown in FIG. 14, the reverse breakdown voltage of the IGBT
1 can be higher than that of the ON transient voltage, thus the
reverse current through the IGBT 1 due to the recovery operation of
the induction load circuit (not shown) is reduced, thereby
realizing the IGBT having the reduced power loss and the improved
ruggedness.
[0052] It should be noted that although the p.sup.+-type collector
layer 8 generally has the maximal impurity concentration
(CS(P.sup.+)) at the surface thereof, it may have the maximal
impurity concentration at any portions other than the surface.
Also, the maximal impurity concentration of the N.sup.+-type buffer
layer 1 and the p.sup.+-type collector layer 8 represents the peak
value, and if they are constant, it refers the constant value
thereof.
Embodiment 2
[0053] Referring to FIG. 6, another Insulated Gate Bipolar
Transistor (IGBT) 200 according to Embodiment 2 of the present
invention will be described herein. The components shown in FIG. 6
similar to those in FIG. 1 have the reference numerals similar
thereto. However, the IGBT 200 is illustrated in FIG. 6 with
eliminating the emitter electrode, the gate oxide layer, and the
gate electrode.
[0054] As illustrated in FIG. 6, the IGBT 200 has one or more
p-type guard-rings 11 formed on the top surface of the drift layer
2 for surrounding at least one base region 3. Also, the
p.sup.+-type collector layer 8 of the IGBT 200 is formed as a well
region on the bottom surface of the N.sup.+-type buffer layer 1, in
which the PN-junction between the collector layer 8 and the
N.sup.+-type buffer layer 1 is exposed on the bottom surface. This
causes the reverse voltage of the IGBT 200 to be unstable depending
upon the condition of the bottom surface thereof.
[0055] However, the IGBT 200 of Embodiment 2 includes at least one
p-type guard-ring 10 formed also on the bottom surface of the IGBT
200 for surrounding the collector layer 8, thereby stabilizing the
reverse voltage of the IGBT 200, and reducing the avalanche current
through the IGBT 200.
Embodiment 3
[0056] Referring to FIGS. 7-8, another Insulated Gate Bipolar
Transistor (IGBT) 300 according to Embodiment 3 of the present
invention will be described herein. The components shown in FIG. 7
similar to those in FIG. 1 have the reference numerals similar
thereto. However, the IGBT 300 is illustrated in FIG. 7 with
eliminating the emitter electrode, the gate oxide layer, and the
gate electrode.
[0057] As illustrated in FIG. 7, the IGBT 300 has a plurality of
annular p-type guard-rings 11 formed on the surface of the drift
layer 2. Also, the drift layer 2 includes a short carrier-lifetime
region 12 allowing the carrier therein to have the lifetime shorter
than in the drift layer 2. Such a short carrier-lifetime region 12
can be formed by radiating radioactive rays and/or particle beams
to provide the predetermined region with traps of carrier (electron
and hole).
[0058] The short carrier-lifetime region 12 traps undesired carrier
drifting in the n.sup.--type drift layer 2 so as to eliminate the
unnecessary current of the IGBT 300.
[0059] FIG. 8 illustrates the operating voltage and the parasitic
pnp-Tr current of the IGBT 300 varying with the depth (distance) of
the short carrier-lifetime region 12 measured from the top surface
of the drift layer 2. As can be seen in FIG. 8, the operating
voltage (the forward voltage during the ON-state of the IGBT) is
greater as the short carrier-lifetime region 12 is located more
deeply. In particular, the short carrier-lifetime region 12 is
preferably located at the depth of 40 .mu.m or less, more
preferably 30 .mu.m or less, so as to remain the operating voltage
to be relatively low. Also, the parasitic pnp-Tr current shows
higher, as the short carrier-lifetime region 12 is located more
deeply.
[0060] Thus, the short carrier-lifetime region 12 of the depth of
40 .mu.m or less keeps the ON-voltage and the parasitic pnp-Tr
current to be relatively low.
[0061] As above, in the IGBT according to Embodiment 3, the short
carrier-lifetime region 12 is formed within the drift layer 2 to
trap the carrier even where the reverse avalanche current is
generated in the IGBT, thereby preventing the parasitic pnp-Tr
current of the IGBT.
[0062] Thus, the parasitic pnp-Tr operation of the IGBT is
minimized, thereby reducing the loss and improving the ruggedness
of the IGBT.
Embodiment 4
[0063] Referring to FIG. 9, another Insulated Gate Bipolar
Transistor (IGBT) 400 according to Embodiment 4 of the present
invention will be described herein. The components shown in FIG. 9
similar to those in FIG. 7 have the reference numerals similar
thereto. However, the IGBT 400 is illustrated in FIG. 9 with
eliminating the emitter electrode, the gate oxide layer, and the
gate electrode.
[0064] In the IGBT 400 shown in FIG. 9, the short carrier-lifetime
region 13 is formed only beneath the cell portion (including the
base region 3 with the n.sup.--emitter region 4). Besides, the
remaining structure of the IGBT 400 is the same as that of the IGBT
300.
[0065] The short carrier-lifetime region 13 of the present
embodiment is located intervening in the current path between the
cell portion and the collector electrode 9. Thus, the undesired
carrier drifting through the short carrier-lifetime region 13 is
effectively trapped while preventing the increase of the operating
voltage (the forward dropping voltage during the ON condition of
the IGBT). This suppresses the parasitic pnp-Tr operation so as to
reduce the loss and improve the ruggedness of the IGBT.
Embodiment 5
[0066] Referring to FIG. 10, another Insulated Gate Bipolar
Transistor (IGBT) 500 according to Embodiment 5 of the present
invention will be described herein. The components shown in FIG. 10
similar to those in FIG. 7 have the reference numerals similar
thereto. However, the IGBT 500 is illustrated in FIG. 10 with
eliminating the emitter electrode, the gate oxide layer, and the
gate electrode.
[0067] The IGBT 500 of the present embodiment includes both the
guard-ring 10 similar to one of the IGBT 200 and the short
carrier-lifetime region 12 similar to one of the IGBT 300. Thus,
the IGBT 500 so structured can stabilize the reverse breakdown
voltage and also suppress the parasitic pnp-Tr operation. It should
be noted that the short carrier-lifetime region 12 can be formed
only beneath the cell portion (including the base region 3 with the
n.sup.--emitter region 4) as the IGBT 400.
Embodiment 6
[0068] Referring to FIGS. 11-12, a semiconductor device according
to Embodiment 6 of the present invention will be described herein.
The semiconductor device 600 shown in FIG. 11 includes a diode
connected in series between the collector terminal (c) of the IGBT
and the load (not shown). The diode has the reverse breakdown
voltage of, for example, about 300 volts. This additional diode has
an effect similar to the case where the reverse breakdown voltage
is improved, i.e., preventing the avalanche current running into
the collector terminal of the IGBT.
[0069] The IGBT includes the gate electrode and the emitter
electrode formed on the top surface, which are connected via
bonding-wires of aluminum with the gate terminal and the emitter
terminal, respectively. Also, the collector electrode formed on the
bottom surface of the IGBT is electrically connected with the
cathode electrode of the diode. Further, the anode electrode of the
diode is electrically connected via bonding-wires of metal such as
aluminum with the collector electrode.
[0070] The inverter device as illustrated in FIG. 14 can be
realized by directly connecting the emitter and collector terminals
across the load and by connecting the gate terminal with a gate
signal line.
[0071] As above, the semiconductor device including the IGBT and
the diode connected in series can prevent the avalanche current
from running into the collector electrode, thereby suppressing the
parasitic pnp-Tr current. This prevents the parasitic pnp-Tr
operation, thereby to reduce the power loss and improve the
ruggedness of the IGBT. To this end, since the parasitic pnp-Tr
current of the IGBT can be suppressed by connecting the diode via
bonding-wires, the inverter device with the improved breakdown
voltage can readily be achieved.
Embodiment 7
[0072] Referring to FIG. 13, another Insulated Gate Bipolar
Transistor (IGBT) according to Embodiment 7 of the present
invention will be described herein. The components shown in FIG. 13
similar to those in FIG. 1 have the reference numerals similar
thereto. The semiconductor device 700 shown in FIG. 13 also
includes a diode 20 consisting of n.sup.--type and p.sup.--type
layers 21, 22, which are sandwiched between the p.sup.+-type
collector layer 8 and the collector electrode 9.
[0073] In the semiconductor device 700, the IGBT and the diode are
integrated as one chip to achieve the circuit diagram as shown in
FIG. 11, thereby downsizing the semiconductor device 700. Also,
this eliminates the inductance with the bonding-wires as required
in Embodiment 6, and shortens the turn-on time in a forward
direction of the diode. Also, the one chip integration leads the
area of the device to be downsized.
[0074] The IGBT and the diode may be integrated in one
semiconductor manufacturing process, or may be separately produced
and bonded to each other with any conductive adhesive.
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