U.S. patent application number 12/384977 was filed with the patent office on 2009-10-29 for structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump.
This patent application is currently assigned to MegicA Corporation. Invention is credited to Ming-Ta Lei, Chuen-Jye Lin, Mou-Shiung Lin.
Application Number | 20090267213 12/384977 |
Document ID | / |
Family ID | 39187738 |
Filed Date | 2009-10-29 |
United States Patent
Application |
20090267213 |
Kind Code |
A1 |
Lin; Mou-Shiung ; et
al. |
October 29, 2009 |
Structure and manufacturing method of a chip scale package with low
fabrication cost, fine pitch and high reliability solder bump
Abstract
A new method and package is provided for the mounting of
semiconductor devices that have been provided with small-pitch
Input/Output interconnect bumps. Fine pitch solder bumps,
consisting of pillar metal and a solder bump, are applied directly
to the I/O pads of the semiconductor device, the device is then
flip-chip bonded to a substrate. Dummy bumps may be provided for
cases where the I/O pads of the device are arranged such that
additional mechanical support for the device is required.
Inventors: |
Lin; Mou-Shiung; (Hsinchu,
TW) ; Lei; Ming-Ta; (Hsinchu, TW) ; Lin;
Chuen-Jye; (Taichung, TW) |
Correspondence
Address: |
SAILE ACKERMAN LLC
28 DAVIS AVENUE
POUGHKEEPSIE
NY
12603
US
|
Assignee: |
MegicA Corporation
|
Family ID: |
39187738 |
Appl. No.: |
12/384977 |
Filed: |
April 9, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09837007 |
Apr 18, 2001 |
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12384977 |
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09798654 |
Mar 5, 2001 |
6818545 |
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09837007 |
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Current U.S.
Class: |
257/687 ;
257/692; 257/737; 257/741; 257/E23.023; 257/E23.136 |
Current CPC
Class: |
H01L 2924/181 20130101;
H01L 2924/01079 20130101; H01L 2924/00013 20130101; H01L 2924/01022
20130101; H01L 23/49816 20130101; H01L 2924/01082 20130101; H01L
2224/131 20130101; H01L 2924/351 20130101; H01L 2924/30105
20130101; H01L 2924/01074 20130101; H01L 2924/01015 20130101; H01L
2924/01014 20130101; H01L 2924/01042 20130101; H01L 2924/15311
20130101; H01L 24/12 20130101; H01L 2924/01029 20130101; H01L
2924/01073 20130101; H01L 2224/06136 20130101; H01L 2924/01006
20130101; H01L 2924/14 20130101; H01L 2224/13017 20130101; H01L
2224/05572 20130101; H01L 2224/04042 20130101; H01L 2924/01013
20130101; H01L 2924/01078 20130101; H01L 2224/13083 20130101; H01L
2224/13147 20130101; H01L 2924/12044 20130101; H01L 24/06 20130101;
H01L 2924/01005 20130101; H01L 2224/16 20130101; H01L 2924/014
20130101; H01L 2224/13023 20130101; H01L 24/17 20130101; H01L
2924/01033 20130101; H01L 2924/01018 20130101; H01L 24/16 20130101;
H01L 2224/0401 20130101; H01L 2224/13155 20130101; H01L 2924/0105
20130101; H01L 2224/13007 20130101; H01L 2924/01075 20130101; H01L
2224/1308 20130101; H01L 2924/04941 20130101; H01L 2224/13147
20130101; H01L 2924/00014 20130101; H01L 2224/13155 20130101; H01L
2924/00014 20130101; H01L 2224/131 20130101; H01L 2924/014
20130101; H01L 2224/1308 20130101; H01L 2224/131 20130101; H01L
2924/014 20130101; H01L 2924/00013 20130101; H01L 2224/13099
20130101; H01L 2924/351 20130101; H01L 2924/00 20130101; H01L
2924/181 20130101; H01L 2924/00 20130101; H01L 2224/05572 20130101;
H01L 2924/00014 20130101 |
Class at
Publication: |
257/687 ;
257/692; 257/E23.136; 257/737; 257/741; 257/E23.023 |
International
Class: |
H01L 23/488 20060101
H01L023/488; H01L 23/18 20060101 H01L023/18 |
Claims
1. A chip package comprising: a substrate; a semiconductor device
over said substrate, wherein said semiconductor device comprises a
silicon substrate, a dielectric layer under said silicon substrate,
a first metal layer under said dielectric layer, wherein said first
metal layer comprises a metal pad and a metal piece separate from
said metal pad and neighboring said metal pad, and a polymer layer
under said dielectric layer, under said metal pad, under said metal
piece and in a gap between said metal pad and said metal piece,
wherein an opening in said polymer layer is under a first contact
point of said metal pad, and said first contact point is at a top
of said opening; a copper pillar between said first contact point
and said substrate, wherein said copper pillar has a height between
10 and 100 micrometers, and wherein said copper pillar is connected
to said first contact point through said opening; a second metal
layer between said first contact point and said copper pillar,
wherein said second metal layer is on said first contact point, on
a bottom surface of said polymer layer and in said opening, wherein
said bottom surface has a first region directly over said second
metal layer and directly under said metal pad and a second region
directly under the middle of said gap, wherein said first region is
at a substantially same horizontal level as said second region, and
there is no significant step between said first region and said
second region, and wherein said copper pillar is connected to said
first contact point through said second metal layer; a solder
between said copper pillar and said substrate, wherein said solder
is joined with said substrate, and wherein said solder is connected
to said copper pillar; and an underfill between said semiconductor
device and said substrate, wherein said underfill contacts with
said semiconductor device and said substrate and encloses said
copper pillar.
2. The chip package of claim 1 further comprising a
nickel-containing layer between said solder and said copper
pillar.
3. The chip package of claim 2, wherein said nickel-containing
layer has a thickness between 1 and 10 micrometers.
4. The chip package of claim 1, wherein said second metal layer
comprises titanium.
5. The chip package of claim 1, wherein said metal pad comprises
copper.
6. The chip package of claim 1, wherein said substrate comprises a
solder mask, a second contact point in a channel in said solder
mask, a third contact point in said channel, wherein said second
contact point is separate from said third contact point, and
wherein said channel has a first sidewall and a second sidewall
opposite to and substantially parallel with said first sidewall, a
first interconnect covered by said solder mask and connected to
said second contact point through said first sidewall, and a second
interconnect covered by said solder mask and connected to said
third contact point through said second sidewall, wherein said
solder is joined with said second contact point.
7. A chip package comprising: a substrate; a semiconductor device
over said substrate, wherein said semiconductor device comprises a
silicon substrate, a dielectric layer under said silicon substrate,
a first metal layer under said dielectric layer, wherein said first
metal layer comprises a metal pad and a metal piece separate from
said metal pad and neighboring said metal pad, and a polymer layer
under said dielectric layer, under said metal pad, under said metal
piece and in a gap between said metal pad and said metal piece,
wherein an opening in said polymer layer is under a first contact
point of said metal pad, and said first contact point is at a top
of said opening; a copper-containing layer between said first
contact point and said substrate, wherein said copper-containing
layer is connected to said first contact point through said
opening; a second metal layer between said first contact point and
said copper-containing layer, wherein said second metal layer is on
said first contact point, on a bottom surface of said polymer layer
and in said opening, wherein said bottom surface has a first region
directly over said second metal layer and directly under said metal
pad and a second region directly under the middle of said gap,
wherein said first region is at a substantially same horizontal
level as said second region, and there is no significant step
between said first region and said second region, and wherein said
copper-containing layer is connected to said first contact point
through said second metal layer; a solder between said
copper-containing layer and said substrate, wherein said solder is
joined with said substrate, and wherein said solder is connected to
said copper-containing layer; and an underfill between said
semiconductor device and said substrate, wherein said underfill
contacts with said semiconductor device and said substrate and
encloses said solder.
8. The chip package of claim 7, wherein said second metal layer
comprises titanium.
9. The chip package of claim 7, wherein said metal pad comprises
copper.
10. The chip package of claim 7, wherein said copper-containing
layer has a thickness between 10 and 100 micrometers.
11. The chip package of claim 7, wherein said substrate comprises a
solder mask, a second contact point in a channel in said solder
mask, a third contact point in said channel, wherein said second
contact point is separate from said third contact point, and
wherein said channel has a first sidewall and a second sidewall
opposite to and substantially parallel with said first sidewall, a
first interconnect covered by said solder mask and connected to
said second contact point through said first sidewall, and a second
interconnect covered by said solder mask and connected to said
third contact point through said second sidewall, wherein said
solder is joined with said second contact point.
12. A chip package comprising: a substrate; a semiconductor device
over said substrate, wherein said semiconductor device comprises a
silicon substrate, a dielectric layer under said silicon substrate,
a first metal layer under said dielectric layer, wherein said first
metal layer comprises a metal pad and a metal piece separate from
said metal pad and neighboring said metal pad, and a polymer layer
under said dielectric layer, under said metal pad, under said metal
piece and in a gap between said metal pad and said metal piece,
wherein an opening in said polymer layer is under a first contact
point of said metal pad, and said first contact point is at a top
of said opening; a copper-containing layer between said first
contact point and said substrate, wherein said copper-containing
layer is connected to said first contact point through said
opening; a second metal layer between said first contact point and
said copper-containing layer, wherein said second metal layer is on
said first contact point, on a bottom surface of said polymer layer
and in said opening, wherein said bottom surface has a first region
directly over said second metal layer and directly under said metal
pad and a second region directly under the middle of said gap,
wherein said first region is at a substantially same horizontal
level as said second region, and there is no significant step
between said first region and said second region, and wherein said
copper-containing layer is connected to said first contact point
through said second metal layer; a solder between said
copper-containing layer and said substrate, wherein said solder is
joined with said substrate, and wherein said solder is connected to
said copper-containing layer; a nickel-containing layer between
said copper-containing layer and said solder; and an underfill
between said semiconductor device and said substrate, wherein said
underfill contacts with said semiconductor device and said
substrate and encloses said solder.
13. The chip package of claim 12, wherein said second metal layer
comprises titanium.
14. The chip package of claim 12, wherein said metal pad comprises
copper.
15. The chip package of claim 12, wherein said copper-containing
layer has a thickness between 10 and 100 micrometers.
16. The chip package of claim 12, wherein said nickel-containing
layer has a thickness between 1 and 10 micrometers.
17. A chip package comprising: a substrate; a semiconductor device
over said substrate, wherein said semiconductor device comprises a
silicon substrate, a dielectric layer under said silicon substrate,
a first metal layer under said dielectric layer, wherein said first
metal layer comprises a metal pad and a metal piece separate from
said metal pad and neighboring said metal pad, and a polymer layer
under said dielectric layer, under said metal pad, under said metal
piece and in a gap between said metal pad and said metal piece,
wherein an opening in said polymer layer is under a first contact
point of said metal pad, and said first contact point is at a top
of said opening; a nickel-containing layer between said first
contact point and said substrate, wherein said nickel-containing
layer is connected to said first contact point through said
opening; a second metal layer between said first contact point and
said nickel-containing layer, wherein said second metal layer is on
said first contact point, on a bottom surface of said polymer layer
and in said opening, wherein said bottom surface has a first region
directly over said second metal layer and directly under said metal
pad and a second region directly under the middle of said gap,
wherein said first region is at a substantially same horizontal
level as said second region, and there is no significant step
between said first region and said second region, and wherein said
nickel-containing layer is connected to said first contact point
through said second metal layer; a solder between said
nickel-containing layer and said substrate, wherein said solder is
joined with said substrate, and wherein said solder is connected to
said nickel-containing layer; and an underfill between said
semiconductor device and said substrate, wherein said underfill
contacts with said semiconductor device and said substrate and
encloses said solder.
18. The chip package of claim 17, wherein said second metal layer
comprises titanium.
19. The chip package of claim 17, wherein said metal pad comprises
copper .
20. The chip package of claim 17, wherein said nickel-containing
layer has a thickness between 1 and 10 micrometers.
Description
RELATED PATENT APPLICATION
[0001] This application is a Continuation application of Ser. No.
09/837,007, filed on Apr. 18, 2001, now pending, which is a
Continuation-in-part of Ser. No. 09/798,654, filed on Mar. 5, 2001,
now U.S. Pat. No. 6,818,545.
BACKGROUND OF THE INVENTION
[0002] (1) Field of the Invention
[0003] The invention relates to the fabrication of integrated
circuit devices, and more particularly, to a method and package for
packaging semiconductor devices.
[0004] (2) Description of the Prior Art
[0005] Semiconductor device performance improvements are largely
achieved by reducing device dimensions, a development that has, at
the same time, resulted in considerable increases in device density
and device complexity. These developments have resulted in placing
increasing demands on the methods and techniques that are used to
access the devices, also referred to as Input/Output (I/O)
capabilities of the device. This has led to new methods of
packaging semiconductor devices whereby structures such as Ball
Grid Array (BGA) devices and Column Grid Array (CGA) devices have
been developed. A Ball Grid Array (BGA) is an array of solder balls
placed on a chip carrier. The balls contact a printed circuit board
in an array configuration where, after reheat, the balls connect
the chip to the printed circuit board. BGA's are known with 40, 50
and 60 mil spacings. Due to the increased device miniaturization,
the impact that device interconnects have on device performance and
device cost has also become a larger factor in package development.
Device interconnects, due to their increase in length in order to
package complex devices and connect these devices to surrounding
circuitry, tend to have an increasingly negative impact on the
package performance. For longer and more robust metal
interconnects, the parasitic capacitance and resistance of the
metal interconnection increase, which degrades the chip performance
significantly. Of particular concern in this respect is the voltage
drop along power and ground buses and the RC delay that is
introduced in the critical signal paths.
[0006] One of the approaches that has been taken to solve these
packaging problems is to develop low resistance metals (such as
copper) for the interconnect wires, while low dielectric constant
materials are being used in between signal lines. Another approach
to solve problems of I/O capability has been to design chips and
chip packaging techniques that offer dependable methods of
increased interconnecting of chips at a reasonable manufacturing
cost.
[0007] One of the more recent developments that is aimed at
increasing the Input-Output (I/O) capabilities of semiconductor
device packages is the development of Flip Chip Packages. Flip-chip
technology fabricates bumps (typically Pb/Sn solders) on aluminum
pads on a semiconductor device. The bumps are interconnected
directly to the package media, which are usually ceramic or plastic
based. The flip-chip is bonded face down to the package medium
through the shortest paths. These technologies can be applied not
only to single-chip packaging, but also to higher or integrated
levels of packaging in which the packages are larger, and to more
sophisticated substrates that accommodate several chips to form
larger functional units.
[0008] In general, Chip-On-Board (COB) techniques are used to
attach semiconductor dies to a printed circuit board; these
techniques include the technical disciplines of flip chip
attachment, wirebonding, and tape automated bonding (TAB). Flip
chip attachment consists of attaching a flip chip to a printed
circuit board or to another substrate. A flip chip is a
semiconductor chip that has a pattern or arrays of terminals that
are spaced around an active surface area of the flip chip, allowing
for face down mounting of the flip chip to a substrate.
[0009] Generally, the flip chip active surface has one of the
following electrical connectors: BGA (wherein an array of minute
solder balls is created on the surface of the flip chip that
attaches to the substrate); Slightly Larger than Integrated Circuit
Carrier (SLICC) (which is similar to the BGA but has a smaller
solder ball pitch and diameter than the BGA); a Pin Grid Array
(PGA) (wherein an array of small pins extends substantially
perpendicularly from the attachment surface of a flip chip, such
that the pins conform to a specific arrangement on a printed
circuit board or other substrate for attachment thereto). With the
BGA or SLICC, the solder or other conductive ball arrangement on
the flip chip must be a mirror image of the connecting bond pads on
the printed circuit board so that precise connection can be
made.
[0010] In creating semiconductor devices, the technology of
interconnecting devices and device features is a continuing
challenge in the era of sub-micron devices. Bond pads and solder
bumps are frequently used for this purpose, whereby continuous
effort is dedicated to creating bond pads and solder bumps that are
simple, reliable and inexpensive.
[0011] Bond pads are generally used to wire device elements and to
provide exposed contact regions of the die. These contact regions
are suitable for wiring the die to components that are external to
the die. An example is where a bond wire is attached to a bond pad
of a semiconductor die at one end and to a portion of a Printed
Circuit Board at the other end of the wire. The art is constantly
striving to achieve improvements in the creation of bond pads that
simplify the manufacturing process while enhancing bond pad
reliability.
[0012] Materials that are typically used for bond pads include
metallic materials, such as tungsten and aluminum, while heavily
doped polysilicon can also be used for contacting material. The
bond pad is formed on the top surface of the semiconductor device
whereby the electrically conducting material is frequently embedded
in an insulating layer of dielectric. In using polysilicon as the
bond pad material, polysilicon can be doped with an n-type dopant
for contacting N-regions while it can be doped with p-type dopant
for contacting P-regions. This approach of doping avoids
inter-diffusion of the dopants and dopant migration. It is clear
that low contact resistance for the bond pad area is required while
concerns of avoidance of moisture or chemical solvent absorption,
thin film adhesion characteristics, delamination and cracking play
an important part in the creation of bond pads.
[0013] The conventional processing sequence that is used to create
an aluminum bond pad starts with a semiconductor surface, typically
the surface of a silicon single crystalline substrate. A layer of
Intra Metal Dielectric (IMD) is deposited over the surface, a layer
of metal, typically aluminum, is deposited over the surface of the
layer of IMD. The layer of metal is patterned and etched typically
using a layer of photoresist and conventional methods of
photolithography and etching. After a bond pad has been created in
this manner, a layer of passivation is deposited over the layer of
IMD. An opening that aligns with the bond pad is created in the
layer of passivation, again using methods of photolithography and
etching.
[0014] A conventional method that is used to create a solder bump
over a contact pad is next highlighted. FIGS. 1 through 4 show an
example of one of the methods that is used to create an
interconnect bump. A semiconductor surface 10 has been provided
with a metal contact pad 14; the semiconductor surface 10 is
protected with a layer 12 of passivation. An opening 19 has been
created in the layer 12 of passivation; the surface of the metal
contact pad 14 is exposed through this opening 19. Next, in FIG. 2,
a dielectric layer 16 is deposited over the surface of the layer 12
of passivation. The layer 16 of dielectric is patterned and etched,
creating an opening 21 in the layer 16 of dielectric that aligns
with the metal pad 14 and that partially exposes the surface of the
metal pad 14. A layer 18 of metal, typically using
Under-Bump-Metallurgy (UBM), is created over the layer 16 of
dielectric; layer 18 of metal is in contact with the surface of the
metal pad 14 inside opening 21. The region of layer 18 of metal
that is above the metal pad 14 will, at a later point in the
processing, form a pedestal over which the interconnect bump will
be formed. This pedestal can be further extended in a vertical
direction by the deposition and patterning of one or more
additional layers that may contain a photoresist or a dielectric
material; these additional layers are not shown in FIG. 2. These
layers essentially have the shape of layer 16 and are removed
during one of the final processing steps that is applied for the
formation of the interconnect bump.
[0015] A layer of photoresist (not shown) is deposited, patterned
and etched, creating an opening that aligns with the contact pad
14. A layer 20 of metal, such as copper or nickel, shown in FIG. 3,
that forms an integral part of the pedestal of the to-be-created
interconnect bump, is next electroplated in the opening created in
the layer of photoresist and on the surface of the layer 18 of
metal, whereby the layer 18 serves as the lower electrode during
the plating process. Layer 20 in prior art applications has a
thickness of between about 1 and 10 .mu.m with a typical value of
about 5 .mu.m. The final layer 22 of solder is electroplated on the
surface of layer 20. The patterned layer of photoresist is then
removed.
[0016] The layer 18 of metal is next etched, as in FIG. 4, leaving
in place only the pedestal for the interconnect bump. During this
etch process the deposited layers 20 and 22 serve as a mask. If, as
indicated above, additional layers of dielectric or photoresist
have been deposited for the further shaping of pedestal 18 in FIG.
2, these layers are also removed at this time.
[0017] A solder paste or flux (not shown) is now applied to the
layer 22 of solder, and the solder 22 is melted in a reflow surface
typically under a nitrogen atmosphere, creating the spherically
shaped interconnect bump 22 that is shown in FIG. 4.
[0018] In addition to the above indicated additional layers of
dielectric or photoresist that can be used to further shape the
pedestal of the interconnect bump, many of the applications that
are aimed at creating interconnect bumps make use of layers of
metal that serve as barrier layers or that have other specific
purposes, such as the improvement of adhesion of the various
overlying layers or the prevention of diffusion of materials
between adjacent layers. These layers collectively form layer 18 of
FIG. 4 and have, as is clear from the above, an effect on the shape
of the completed bump and are therefore frequently referred to as
Ball Limiting Metal (BLM) layer. Frequently used BLM layers are
successive and overlying layers of chrome, copper and gold, whereby
the chrome is used to enhance adhesion with an underlying aluminum
contact pad, the copper layer serves to prevent diffusion of solder
materials into underlying layers, while the gold layer serves to
prevent oxidation of the surface of the copper layer. The BLM layer
is layer 18 of FIGS. 2 through 4.
[0019] Increased device density brings with it increased closeness
of components and elements that are part of the created
semiconductor devices. This increased closeness is expressed as a
reduction in the spacing or "pitch" between elements of a
semiconductor device. State-of-the-art technology uses solder bumps
having a pitch of about 200 .mu.m, which imposes a limitation on
further increasing device density. The limitation in further
reducing the pitch of solder bumps is imposed by concerns of
reliability, which impose a relatively large ball size for the
solder bump. This relatively large solder ball restricts further
reducing the solder ball pitch.
[0020] In the majority of applications, solder bumps are used as
interconnections between I/O bond pads and a substrate or printed
circuit board. A large solder ball brings with it high standoff
since a solder ball with high standoff has better thermal
performance (CTE mismatching is easier to avoid resulting in
reduced thermal stress on the solder balls). Large solder balls are
therefore required in order to maintain interconnect reliability.
Low-alpha solder is applied to avoid soft error (electrical or
functional errors) from occurring, thereby eliminating the
potential for inadvertent memory discharge and incorrect setting of
the voltage (1 or 0).
[0021] U.S. Pat. No. 6,169,329 (Farnworth et al.) shows
standardized die to substrate bonding locations (Ball grid or other
array).
[0022] U.S. Pat. No. 5,741,726 (Barber) shows an assembly with
minimized bond finger connections.
[0023] U.S. Pat. No. 5,744,843 (Efland et al.), U.S. Pat. No.
5,172,471 (Huang), U.S. Pat. No. 6,060,683 (Estrade), U.S. Pat. No.
5,643,830 (Rostoker et al.), and U.S. Pat. No. 6,160,715 (Degani et
al.) are related patents.
[0024] The invention addresses concerns of creating a BGA type
package whereby the pitch of the solder ball or solder bump of the
device interconnect is in the range of 200 .mu.m or less. The
conventional, state-of-the-art solder process runs into limitations
for such a fine interconnect pad pitch. The invention provides a
method and a package for attaching devices having very small ball
pitch to an interconnect medium such as a Printed Circuit
Board.
SUMMARY OF THE INVENTION
[0025] A principal objective of the invention is to provide a
method of creating a fine-pitch solder bump.
[0026] Another objective of the invention is to provide a method of
creating smaller solder bumps, further allowing for the creation of
fine-pitched solder bumps.
[0027] Another objective of the invention is to provide a
cost-effective method to create a fine-pitch solder bump of high
reliability, due to the increased height of the solder bump. This
objective is based on the belief that solder bump reliability
improves proportionally to the square of the distance between the
solder ball and the underlying substrate.
[0028] Another objective of the invention is to provide a
cost-effective way of creating a solder bump. This cost-effective
way is realized by using standard solder material and therewith
eliminating the need for expensive "low-.alpha. solder".
[0029] Another objective of the invention is to provide a
cost-effective method of creating a fine-pitch solder bump by
reducing the alpha-effect on memory products.
[0030] Another objective of the invention is to provide a method of
creating solder bumps which allows an easy method of cleaning flux
after the process of creating the solder bumps has been
completed.
[0031] Another objective of the invention is to provide a method of
creating solder bumps which allows easy application of
underfill.
[0032] Another objective of the invention is to provide a method
for applying fine-pitch solder bumps directly to the I/O pads of a
semiconductor device, without a redistribution interface, and
bonding the semiconductor device directly to a Ball Grid Array
substrate using the flip-chip bonding approach.
[0033] Another objective of the invention is to provide a method
for shortening the interconnection between a semiconductor device
and a substrate on which the semiconductor device is mounted, thus
improving the electrical performance of the semiconductor
device.
[0034] Yet another objective of the invention is to eliminate
conventional methods of re-distribution of device I/O interconnect,
thereby making packaging of the device more cost-effective and
eliminating performance degradation.
[0035] A still further objective of the invention is to improve
chip accessibility during testing of the device, thus eliminating
the need for special test fixtures.
[0036] A still further objective of the invention is to improve
performance and device reliability of BGA packages that are used
for the mounting of semiconductor devices having small-pitch I/O
interconnect bumps.
[0037] A still further objective of the invention is to perform
Chip Scale Packaging (CSP) without re-distribution, including for
various pad designs such as peripheral or central pad designs.
[0038] A still further objective of the invention is to provide a
method of mounting small-pitch semiconductor devices in such a
manner that flux removal and the dispensing of device encapsulants
is improved.
[0039] In accordance with the objectives of the invention, a new
method and package is provided for the mounting of semiconductor
devices that have been provided with small-pitch Input/Output
interconnect bumps. Fine pitch solder bumps, consisting of pillar
metal and a solder bump, are applied directly to the I/O pads of
the semiconductor device, and the device is then flip-chip bonded
to a substrate. Dummy bumps may be provided for cases where the I/O
pads of the device are arranged such that additional mechanical
support for the device is required.
BRIEF DESCRIPTION OF THE DRAWINGS
[0040] FIGS. 1 through 4 show a prior-art method of creating a
solder bump overlying a point of electrical contact, as
follows:
[0041] FIG. 1 shows a cross section of a semiconductor surface on
the surface of which a contact pad has been created; the
semiconductor surface is covered with a patterned layer of
passivation.
[0042] FIG. 2 shows a cross section of FIG. 1 after a patterned
layer of dielectric and a layer of metal have been created on the
semiconductor surface.
[0043] FIG. 3 shows a cross section of FIG. 2 after a layer of bump
metal and solder compound have been selectively deposited.
[0044] FIG. 4 show a cross section that after excessive layers have
been removed from the semiconductor surface and after the solder
has been reflowed, the interconnect bump is formed.
[0045] FIG. 5 shows a cross section of a BGA package; a
semiconductor device is encapsulated in a molding compound.
[0046] FIG. 6 shows a cross section of a BGA package; an underfill
is provided to the semiconductor device.
[0047] FIGS. 7 through 16 address the invention, as follows:
[0048] FIG. 7 shows a cross section of a semiconductor surface, a
layer of dielectric, metal pads, a layer of passivation, and a
layer of barrier material.
[0049] FIG. 8 shows a cross section after a patterned layer of
photoresist has been created over the structure of FIG. 7.
[0050] FIG. 9 shows a cross section after pillar metal has been
created aligned with the metal pads and under bump metal has been
deposited over the surface of the pillar metal.
[0051] FIG. 10 shows a cross section after solder metal has been
plated over the under bump metal.
[0052] FIG. 11 shows a cross section after the patterned layer of
photoresist has been removed from the surface.
[0053] FIG. 12 shows a cross section after the diameter of the
pillar metal has been reduced.
[0054] FIG. 13 shows a cross section after the barrier layer has
been etched using isotropic etching, creating a first profile.
[0055] FIG. 14 shows a cross section after the barrier layer has
been etched using anisotropic etching or RIE, creating a second
profile.
[0056] FIG. 15 shows a cross-section of a first completed solder
bump of the present invention.
[0057] FIG. 16 shows a cross-section of a second completed solder
bump of the present invention.
[0058] FIG. 17 shows a cross section of a BGA package of the
invention; the semiconductor device is encapsulated in a molding
compound.
[0059] FIG. 18 shows a cross section of a BGA package of the
invention; an underfill is provided to the semiconductor
device.
[0060] FIG. 19 shows a top view of an array type I/O pad
configuration of the semiconductor device.
[0061] FIG. 20 shows a top view of a peripheral type I/O pad
configuration of the semiconductor device.
[0062] FIG. 21 shows a top view of a center type I/O pad
configuration of the semiconductor device.
[0063] FIG. 22 shows a top view of a center type I/O pad
configuration of the semiconductor device; dummy solder bumps have
been provided in support of the semiconductor device.
[0064] FIG. 23 shows a top view of the substrate with exposed I/O
contact pads; this exposure is accomplished by not depositing the
solder mask in close proximity to the contact pads of the
semiconductor device.
[0065] FIG. 24 shows a cross section of the substrate of FIG.
23.
[0066] FIG. 25 shows a top view of a prior-art substrate with
exposed I/O contact pads; a solder mask is in close proximity to
the contact pads of a semiconductor device.
[0067] FIG. 26 shows a cross section of the substrate of FIG.
25.
[0068] FIGS. 27a through 27f show examples of applications of the
invention.
[0069] FIGS. 28a and 28b show a conventional substrate and a
substrate of the invention and demonstrate how the invention leads
to the ability to reduce the pitch between I/O pads.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0070] The above stated objective of improving chip accessibility
during testing of the device, thus eliminating the need for special
test fixtures, can further be highlighted as follows. The disclosed
method of the invention, using Chip Scale Packaging (CSP), can
control the cost of testing CSP devices by keeping the same body
size of the chip and by using the same size substrate. For
conventional CSP packages, the chip may have different body sizes,
which imposes the requirement of different size test fixtures. With
the continued reduction of the size of semiconductor devices,
additional and varying device sizes are expected to be used. This
would result in ever increasing costs for back-end testing of the
devices in a production environment. The invention provides a
method where these additional back-end testing costs can be
avoided.
[0071] Referring now to FIG. 5, there is shown a cross section of a
typical flip chip package with a semiconductor device being
encapsulated in a molding compound. An Integrated Circuit (IC)
device 10 enters the process as a separate unit with contact points
(balls 16) attached to the bottom of the chip 10. The IC 10 is
placed on the surface of a BGA substrate 12, and an (optional)
interconnect substrate 14 has been provided for additional routing
of the electrical network to which the device 10 is attached. Balls
18 that are connected to the lower surface of the substrate 12 make
contact with surrounding circuitry (not shown). The paths of
electrical interconnect of the device 10 as shown in cross section
in FIG. 5 are as follows: contact bumps (points of I/O
interconnect, not shown in FIG. 5) are provided on the surface of
the device that faces the substrate 12 and the contact balls 16 are
connected to these contact bumps. Contact balls 16 interface with
points of contact (contact pads) provided in the surface of the
(optional) interconnect network 14 or, for applications where the
interconnect interface 14 is not provided, with points of contact
(contact pads) provided in the surface of the Ball Grid Array (BGA)
substrate 12. BGA substrate 12 may further have been provided with
one or more layers of interconnect metal; all of the interfaces
(the interconnect substrate 12 and the optional redistribution
lines provided in BGA substrate 12) result in interconnecting balls
16 with the balls 18. The Balls 18 are the contact points that
connect the package that is shown in cross section in FIG. 5 to
surrounding circuitry.
[0072] Whereas the cross section that is shown in FIG. 5 shows the
contact balls 16 for the establishment of contacts between the
device 10 and the underlying substrate 12, some prior art
applications still used wire bond connections (not shown in FIG.
5), in order to achieve optimum electrical performance of the
device package.
[0073] Further shown in the cross section of FIG. 5 is layer 19,
which may be provided over the surface of the semiconductor device
10 facing the substrate 12. This re-distribution layer provides
interconnect lines over the surface of the device 10 and is
required in prior art applications if solder bumps are required on
current pad layout for wire bonding purposes. The main purpose of
the redistribution layer is to enlarge the pitch of solder bump
interconnects if the bond pads are originally designed for wire
bonding applications. It will be clear from later explanations that
the invention removes the need for the redistribution layer.
[0074] FIG. 6 shows a cross section of a conventional BGA package
whereby the semiconductor device 10 is provided with underfill 22,
and no molding compound (20, FIG. 5) has been provided in the
package that is shown in cross section in FIG. 6. All the other
statements that relate to the electrical interconnection of the
device 10 of FIG. 6 are identical to the statements that have been
made in the description provided for the package of FIG. 5. It
should be noted in FIG. 6 that the sides of the underfill 22 are
sloping such that the physical contact between the underfill 22 and
the substrate 12 is extended beyond the dimensions of the bottom
surface of the chip 10. This is a normal phenomenon with liquid
underfill, which enhances the mechanical strength between the
substrate 12 and the IC chip 10.
[0075] Referring now to FIG. 15, there is shown a cross section of
a first solder bump that has been created in accordance with the
above referenced related application. The elements that are shown
in FIG. 15 that form part of the solder bump of the related
application are the following: [0076] 10, a semiconductor surface
such as the surface of a substrate, [0077] 30, a layer of
dielectric that has been deposited over the semiconductor surface
10, [0078] 32, contact pads that have been created on the surface
of the layer 30 of dielectric, [0079] 34, a patterned layer of
passivation that has been deposited over the surface of the layer
30 of dielectric; openings have been created in the layer 34 of
passivation, partially exposing the surface of the contact pads 32,
[0080] 36, an isotropically etched layer of barrier metal; this
layer of barrier metal has been isotropically etched; that is, the
barrier metal has been completely removed from the surface of the
layer 34 of passivation except where the barrier metal is covered
by overlying pillar metal (38) of a solder bump, [0081] 38, the
pillar metal of the solder bump, [0082] 40, a layer of under bump
metal created overlying the pillar metal 38 of the solder bump,
wherein the distance between an edge of the under bump metal layer
40 and an edge of the metal pillar 38 of the solder bump is greater
than 0.2 micrometers, and [0083] 42, a solder metal.
[0084] The cross section that is shown in FIG. 16 is similar to the
cross section of FIG. 15 with the exception of layer 35, which is
an anisotropically etched layer of barrier metal (etched after the
solder bump 42 has been created) which, due to the nature of the
anisotropic etch, protrudes from the pillar metal 38 as shown in
the cross section of FIG. 16.
[0085] The cross sections that are shown in FIGS. 15 and 16 and
that have been extracted from the above referenced related
application have been shown in order to highlight that the
referenced application provides a method of creating:
[0086] a fine-pitch solder bump,
[0087] smaller solder bumps,
[0088] a fine-pitch solder bump of high reliability due to the
increased height of the solder bump,
[0089] a cost-effective solder bump by using standard solder
material and eliminating the need for expensive "low-.alpha.
solder",
[0090] a solder bump that allows easy cleaning of flux after the
process of flip chip assembly and before the process of underfill
and encapsulation, and
[0091] a solder bump which allows easy application of
underfill.
[0092] FIGS. 7 through 16 provide details of the process of the
invention which leads to the solder bumps that have been shown in
cross section in FIGS. 5 and 6.
[0093] FIG. 7 shows a cross section of a substrate 10 and the
following elements: [0094] 10, a silicon substrate over the surface
of which metal contact pads 32 have been created, [0095] 30, a
layer of dielectric that has been deposited over the surface of the
substrate 10, [0096] 32, the metal contact pads, typically
comprising aluminum, created over the surface of the layer 30 of
dielectric, [0097] 34, a layer of passivation that has been
deposited over the surface of the layer 30 of dielectric. Openings
have been created in the layer 34 of passivation that align with
the metal contact pads 32, partially exposing the surface of the
contact pads 32, [0098] 36, a layer of barrier metal that has been
created over the surface of the layer 34 of passivation, including
the openings that have been created in the layer 34 of passivation,
contacting the underlying contact pads 32.
[0099] As dielectric material for the layer 30 can be used any of
the typically applied dielectrics such as silicon dioxide (doped or
undoped), silicon oxynitride, parylene, polyimide, spin-on-glass,
plasma oxide or LPCVD oxide. The material that is used for the
deposition of the layer 30 of dielectric of the invention is not
limited to the materials indicated above, but can include any of
the commonly used dielectrics in the art.
[0100] The creation of the metal contact pads 32 can use
conventional methods of metal rf sputtering at a temperature
between about 100 and 400 degrees C. and a pressure between about 1
and 100 mTorr using as source, for instance, aluminum-copper
material (for the creation of aluminum contact pads) at a flow rate
of between about 10 and 400 sccm to a thickness between about 4000
and 11000 Angstroms. After a layer of metal has been deposited, the
layer must be patterned and etched to create the aluminum contact
pads 32. This patterning and etching uses conventional methods of
photolithography and patterning and etching. A deposited layer of
AlCu can be etched using Cl.sub.2/Ar as an etchant at a temperature
between 50 and 200 degrees C., an etchant flow rate of about 20
sccm for the Cl.sub.2 and 1000 sccm for the Ar, a pressure between
about 50 mTorr and 10 Torr, and a time of the etch between 30 and
200 seconds.
[0101] In a typical application, insulating layers, such as silicon
oxide and oxygen-containing polymers, are deposited using a
Chemical Vapor Deposition (CVD) technique over the surface of
various layers of conducting lines in a semiconductor device or
substrate to separate the conductive interconnect lines from each
other. The insulating layers can also be deposited over patterned
layers of interconnecting lines; electrical contact between
successive layers of interconnecting lines is established with
metal vias created in the insulating layers. Electrical contact to
the chip is typically established by means of bonding pads or
contact pads that form electrical interfaces with patterned levels
of interconnecting metal lines. Signal lines and power/ground lines
can be connected to the bonding pads or contact pads. After the
bonding pads or contact pads have been created on the surfaces of
the chip, the bonding pads or contact pads are passivated and
electrically insulated by the deposition of a passivation layer
over the surface of the bonding pads. A passivation layer can
contain silicon oxide/silicon nitride (SiO.sub.2/Si.sub.3N.sub.4)
deposited by CVD. The passivation layer is patterned and etched to
create openings in the passivation layer for the bonding pads or
contact pads after which a second and relatively thick passivation
layer can be deposited for further insulation and protection of the
surface of the chips from moisture and other contaminants and from
mechanical damage during assembling of the chips.
[0102] Various materials have found application in the creation of
passivation layers. The passivation layer can contain silicon
oxide/silicon nitride (SiO.sub.2/Si.sub.3N.sub.4) deposited by CVD,
or a passivation layer can be a layer of photosensitive polyimide
or can comprise titanium nitride. Another material often used for a
passivation layer is phosphorous doped silicon dioxide that is
typically deposited over a final layer of aluminum interconnect
using a Low Temperature CVD process. In recent years,
photosensitive polyimide has frequently been used for the creation
of passivation layers. Conventional polyimides have a number of
attractive characteristics for their application in a semiconductor
device structure which have been highlighted above. Photosensitive
polyimides have these same characteristics but can, in addition, be
patterned like a photoresist mask and can, after patterning and
etching, remain on the surface on which it has been deposited to
serve as a passivation layer. Typically and to improve surface
adhesion and tension reduction, a precursor layer is first
deposited by, for example, conventional photoresist spin coating.
The precursor is, after a low temperature pre-bake, exposed using,
for example, a step and repeat projection aligner and Ultra Violet
(UV) light as a light source. The portions of the precursor that
have been exposed in this manner are cross-linked, thereby leaving
unexposed regions (that are not cross-linked) over the bonding
pads. During subsequent development, the unexposed polyimide
precursor layer (over the bonding pads) is dissolved, thereby
providing openings over the bonding pads. A final step of thermal
curing leaves a permanent high quality passivation layer of
polyimide over the substrate.
[0103] The preferred material of the invention for the deposition
of the layer 34 of passivation is Plasma Enhanced silicon nitride
(PE Si.sub.3N.sub.4), deposited using PECVD technology at a
temperature between about 350 and 450 degrees C. with a pressure of
between about 2.0 and 2.8 Torr for the duration between about 8 and
12 seconds. The layer 34 of PE Si.sub.3N.sub.4 can be deposited to
a thickness between about 200 and 800 Angstroms.
[0104] The layer 34 of PE Si.sub.3N.sub.4 is next patterned and
etched to create openings in the layer 34 that overlay and align
with the underlying contact pads 32.
[0105] The etching of the layer 34 of passivation can use
Ar/CF.sub.4 as an etchant at a temperature of between about 120 and
160 degrees C. and a pressure of between about 0.30 and 0.40 Torr
for a time of between about 33 and 39 seconds using a dry etch
process.
[0106] The etching of the layer 34 of passivation can also use
He/NF.sub.3 as an etchant at a temperature of between about 80 and
100 degrees C. and a pressure of between about 1.20 and 1.30 Torr
for a time of between about 20 and 30 seconds using a dry etch
process.
[0107] Barrier layers, such as the layer 36, are typically used to
prevent diffusion of an interconnect metal into surrounding layers
of dielectric and silicon. Some of the considerations that apply in
selecting a material for the barrier layer become apparent by using
copper for interconnect metal as an example. Although copper has a
relatively low cost and low resistivity, it has a relatively large
diffusion coefficient into silicon dioxide and silicon and is
therefore not typically used as an interconnect metal. Copper from
an interconnect may diffuse into the silicon dioxide layer causing
the dielectric to be conductive and decreasing the dielectric
strength of the silicon dioxide layer. Copper interconnects should
be encapsulated by at least one diffusion barrier to prevent
diffusion into the silicon dioxide layer. Silicon nitride is a
diffusion barrier to copper, but the prior art teaches that the
interconnects should not lie on a silicon nitride layer because it
has a high dielectric constant compared with silicon dioxide. The
high dielectric constant causes an undesired increase in
capacitance between the interconnect and the substrate.
[0108] A typical diffusion barrier layer may contain silicon
nitride, phosphosilicate glass (PSG), silicon oxynitride, aluminum,
aluminum oxide (Al.sub.xO.sub.y), tantalum, Ti/TiN or Ti/W,
nionbium, or molybdenum and is more preferably formed from TiN. The
barrier layer can also be used to improve the adhesion, of the
subsequent overlying tungsten layer.
[0109] The barrier layer is preferably between about 500 and 2000
Angstroms thick and more preferably about 300 Angstroms thick, and
can be deposited using rf sputtering.
[0110] After the creation of the barrier layer 36, a seed layer
(not shown in FIG. 7) can be blanket deposited over the surface of
the wafer. For a seed layer that is blanket deposited over the
surface of the wafer, any of the conventional metallic seed
materials can be used. The metallic seed layer can be deposited
using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a
temperature of between about 0 and 300 degrees C. and a pressure of
between about 1 and 100 mTorr, using (for instance) copper or a
copper alloy as the source (as highlighted above) at a flow rate of
between about 10 and 400 sccm and using argon as an ambient
gas.
[0111] FIG. 8 shows a cross section of the substrate after a layer
37 of photoresist has been deposited over the surface of the
barrier layer 36. The layer 37 of photoresist has been patterned
and etched, creating openings 31 in the layer 37 of photoresist.
The openings 31 partially expose the surface of the barrier layer
36. The layer 37 of photoresist is typically applied to a thickness
of between about 100 and 200 .mu.m, but more preferably to a
thickness of about 150 .mu.m.
[0112] The methods used for the deposition and development of the
layer 37 of photoresist uses conventional methods of
photolithography. Photolithography is a common approach wherein
patterned layers are formed by spinning on a layer of photoresist,
projecting light through a photomask with the desired pattern onto
the photoresist to expose the photoresist to the pattern,
developing the photoresist, washing off the undeveloped
photoresist, and plasma etching to clean out the areas where the
photoresist has been washed away. The exposed resist may be
rendered soluble (positive working) and washed away, or insoluble
(negative working) and form the pattern.
[0113] The deposited layer 37 of photoresist can, prior to
patterning and etching, be cured or pre-baked, further hardening
the surface of the layer 37 of photoresist.
[0114] The layer 37 of photoresist can be etched by applying
O.sub.2 plasma and then wet stripping by using H.sub.2SO.sub.4,
H.sub.2O.sub.2 and NH.sub.4OH solution. Sulfuric acid
(H.sub.2SO.sub.4) and mixtures of H.sub.2SO.sub.4 with other
oxidizing agents such as hydrogen peroxide (H.sub.2O.sub.2) are
widely used in stripping photoresist after the photoresist has been
stripped by other means. Wafers to be stripped can be immersed in
the mixture at a temperature between about 100 degrees C. and about
150 degrees C. for 5 to 10 minutes and then subjected to a thorough
cleaning with deionized water and dried by dry nitrogen. Inorganic
resist strippers, such as the sulfuric acid mixtures, are very
effective in the residual free removal of highly postbaked resist.
They are more effective than organic strippers and the longer the
immersion time, the cleaner and more residue-free wafer surface can
be obtained.
[0115] The photoresist layer 37 can also be partially removed using
plasma oxygen ashing and careful wet clean. The oxygen plasma
ashing is heating the photoresist in a highly oxidized environment,
such as an oxygen plasma, thereby converting the photoresist to an
easily removed ash. The oxygen plasma ashing can be followed by a
native oxide dip for 90 seconds in a 200:1 diluted solution of
hydrofluoric acid.
[0116] FIG. 9 shows a cross section of the substrate 10 after a
layer 38 of pillar metal has been deposited (electroplated) over
the surface of the layer 36 of barrier material and bounded by
openings 31 that have been created in the layer 37 of photoresist.
Over the surface of the layers 38 of metal, which will be referred
to as pillar metal in view of the role these layers play in the
completed structure of the solder bumps of the invention, layers 40
of under bump metal have been deposited using deposition methods
such as electroplating.
[0117] The layer 36 preferably comprises titanium or copper and is
preferably deposited to a thickness of between about 500 and 2000
Angstroms, and more preferably to a thickness of about 1000
Angstroms.
[0118] The layer 38 preferably comprises copper and is preferred to
be applied to a thickness of between about 10 and 100 .mu.m, but
more preferably to a thickness of about 50 .mu.m.
[0119] The layer 40 preferably comprises nickel and is preferred to
be applied to a thickness of between about 1 and 10 .mu.m, but more
preferably to a thickness of about 4 .mu.m.
[0120] FIG. 10 shows a cross section where the process of the
invention has further electroplated layers 42 of solder metal over
the surface of the layers 40 of under bump metal (UBM) and bounded
by the openings 31 that have been created in the layer 37 of
photoresist.
[0121] The layer 40 of UBM, typically of nickel and of a thickness
between about 1 and 10 .mu.m, is electroplated over the layer 38 of
pillar metal. The layer 42 of bump metal (typically solder) is
electroplated in contact with the layer 40 of UBM to a thickness of
between about 30 and 100 .mu.m, but more preferably to a thickness
of about 50 .mu.m. The layers 38, 40 and 42 of electroplated metal
are centered in the opening 31 that has been created in the layer
37 of photoresist.
[0122] In the cross section that is shown in FIG. 11, it is shown
that the patterned layer 37 of photoresist has been removed from
above the surface of the barrier layer 36. The previously
highlighted methods and processing conditions for the removal of a
layer of photoresist can be applied for the purpose of the removal
of the layer 37 that is shown in cross section in FIG. 11. The
invention further proceeds with the partial etching of the pillar
metal 38, as shown in cross section in FIG. 12, using methods of
wet chemical etching or an isotropic dry etch, selective to the
pillar metal material. It is clear that, by adjusting the etching
parameters, of which the time of etch is most beneficial, the
diameter of the pillar metal 38 can be reduced by almost any
desired amount. The limitation that is imposed on the extent to
which the diameter of the pillar metal 38 is reduced is not imposed
by the wet etching process, but by concerns of metal bump
reliability and functionality. Too small a remaining diameter of
the pillar metal 38 will affect the robustness of the solder bumps
while this may also have the effect of increasing the resistance of
the metal bump.
[0123] The final two processing steps of the invention, before the
solder metal is reflowed, are shown in the cross section of FIGS.
13 and 14 and affect the etching of the exposed surface of the
barrier layer 36. Using isotropic etching, the exposed barrier
layer 36 is completely removed as shown in FIG. 13. Using
anisotropic etching, in FIG. 14, the etching of the barrier layer,
36 is partially impeded by the presence of the columns 42 of solder
metal.
[0124] It is believed that the undercut shape of the pillar 38 will
prevent wetting of the pillar 38 and the UBM layer 40 during
subsequent solder reflow. It is also believed that exposure to air
will oxidize the sidewalls of the pillar 38 and the UBM layer 40
and therefore prevent wetting of these surfaces during subsequent
solder reflow. Optionally, the sidewalls of the pillar 38 and the
UBM layer 40 may be further oxidized by, for example, a thermal
oxidation below reflow temperature of about 240 degrees C. such as
heating in oxygen ambient at about 125 degrees C.
[0125] FIGS. 15 and 16 show the final cross section of the solder
bump of the invention after the solder metal has been reflowed.
FIG. 15 corresponds to FIG. 13 while FIG. 16 corresponds to FIG.
14, this relating to the etch in the barrier-layer 36 that has been
explained using FIGS. 13 and 14. It is noted that the etched layer
36 of barrier material that is shown in cross section in FIG. 15
corresponds to the etched layer 36 of barrier material that is
shown in FIG. 13. The same correspondence exists between FIGS. 16
and 14.
[0126] The above summarized processing steps of electroplating that
are used for the creation of a metal bump can be supplemented by
the step of curing or pre-baking of the layer of photoresist after
this layer has been deposited.
[0127] To review and summarize the invention: [0128] prior to and
in preparation for the invention, a semiconductor surface is
provided, a layer of dielectric has been deposited over the
semiconductor surface, a contact pad has been provided on the layer
of dielectric, the contact pad has an exposed surface, a layer of
passivation has been deposited over a semiconductor surface
including the surface of said contact pad, and the layer of
passivation has been patterned and etched, creating an opening in
the layer of passivation, partially exposing the surface of the
contact pad, the opening in the layer of passivation is centered
with respect to the contact pad [0129] the invention starts with a
barrier layer deposited over the surface of the layer of
passivation, making contact with the contact pad through the
opening created in the layer of passivation [0130] a layer of
photoresist is deposited over the surface of the barrier layer
[0131] the layer of photoresist is patterned and etched, creating
an opening through the layer of photoresist, wherein the opening in
the layer of photoresist aligns with and is centered with respect
to the contact pad [0132] in sequence are deposited, bounded by the
opening created in the layer of photoresist, a layer of pillar
metal, a layer of under bump metal and a layer of solder metal
[0133] the patterned layer of photoresist is removed from the
surface of the barrier layer [0134] the layer of pillar metal is
etched, reducing the diameter of the pillar metal [0135] the
barrier layer is etched, using either isotropic or anisotropic
etching [0136] the solder metal is reflowed.
[0137] The invention offers the following advantages: [0138] ball
height is a very important reliability concern; in order to prevent
thermal mismatch between overlying layers of a package (such as a
semiconductor device and an underlying printed circuit board and
the like), it is important to increase the distance between
overlying elements; the invention provides this ability, [0139] a
larger solder ball (for better thermal or reliability performance)
results in increased pitch; this is contrary to state of the art
design requirements, [0140] if small solder balls are used without
providing height, it is very difficult to underfill the small gaps,
[0141] the solder is, using the invention, relatively far removed
from the semiconductor device which means that the application of
low-alpha solder is not required (alpha-particles create soft
errors in memory products; lead is known to emit alpha-particles
when lead decays), [0142] for the pillar metal, a metal needs to be
selected that has good conductivity and good ductility, such as
copper. This is in order to provide improved thermal performance by
counteracting thermal stress, [0143] the height of the pillar of
the solder bump of the invention is important and should be between
about 10 to 100 .mu.m in order to achieve objectives of high
stand-off, and [0144] the metal that is used for the under bump
metal layer is important in that this metal must have good adhesion
with the overlying solder during solder reflow while this metal
must not solve too fast and in so doing form a barrier to the
solder; in addition, the UBM metal when exposed to air can form a
layer of protective oxide thus preventing solder wetting to the
pillar metal around the perimeter of the UBM metal during the
reflow process; nickel is therefore preferred for the UBM
metal.
[0145] Now the packaging of the invention using the solder bumps
described above will be discussed. Referring now to the cross
section that is shown in FIG. 17, there is shown a cross section of
a BGA package of the invention whereby the semiconductor device has
been encapsulated in a molding compound. The elements that are
highlighted in the cross section of FIG. 17 are the following:
[0146] 50, a semiconductor device that is mounted in the package of
the invention shown in the cross section in FIG. 17, [0147] 52, a
(BGA) substrate on the surface of which the device 50 is mounted,
[0148] 54, a pillar metal of the interface between the device 50
and the BGA substrate 52, similar to the pillar metal 38 of FIGS.
15 and 16, [0149] 56, a solder bump of the interface between the
device 50 and the BGA substrate 52, similar to the solder bump 42
of FIGS. 15 and 16, [0150] 58, contact balls that are used to
interconnect the package of the invention with surrounding
circuitry, and [0151] 60, molding compound into which the device 50
is embedded for protection against the environment.
[0152] The columns 54 of pillar metal typically have a height of
between about 10 and 100 .mu.m, and more preferably about 50
.mu.m.
[0153] The cross section that is shown in FIG. 18 is identical to
the cross section of FIG. 17, with the exception of an underfill 62
which is used instead of the molding compound 60 of FIG. 17.
[0154] The following comment applies: the creation of the pillar
metal 54 and the solder bump 56 starts using the I/O contact pads
of the device 50 (not shown in FIGS. 17 and 18) as the contact
pads; that is the I/O contact pads of the device 50 take the place
of the contact pad 32 of FIGS. 15 and 16 in the creation of the
pillar metal 54 and the solder bump 56. The process of creating the
pillar metal 54 and the solder bump 56 therefore is as follows:
[0155] a layer of dielectric is deposited over an active surface of
the device 50; the active surface of the device 50 is the surface
in which I/O contact points have been provided; this surface will
face the BGA substrate 52 after mounting of the device 50 on the
BGA substrate 52, [0156] openings are created in the layer of
dielectric, exposing the I/O contact pads of the device 50; this
brings the process of the invention to the point of the related
application where the contact pads 32 (FIGS. 15, 16) have been
created on the surface of the layer 30 of dielectric, [0157] a
layer of passivation is deposited over the surface of the layer of
dielectric, similar to the layer 34, FIGS. 15, 16, [0158] openings
are created in the layer of passivation, partially exposing the
surface of the device I/O contact pads, [0159] a barrier layer is
deposited over the surface of the layer of passivation, identical
to the layer 36, FIGS. 15, 16, [0160] the pillar metal 54 of the
solder bump is formed, identical to the layer 38, FIGS. 15, 16,
[0161] the layer of under bump (not shown in FIGS. 17, 18) is
created overlying the pillar metal 54, identical to the layer 40,
FIGS. 15, 16, [0162] the solder bump 56 is formed, identical to the
layer 42, FIGS. 15, 16, and [0163] the layer of barrier metal is
isotropically (FIG. 15) or anisotropically (FIG. 16) etched.
[0164] Referring now to FIG. 19, there is shown a top view of an
array type arrangement of I/O contact points 66 that form the
contact points of the device 50. This top view of the array type
contact points 66 is shown as one example of where the process of
creating pillar metal and solder bumps can be applied.
[0165] FIGS. 20 and 21 show two more examples of arrangements of
I/O contact pads that are provided on the surface of the device 50,
where the process of the invention can be applied. FIG. 20 shows a
peripheral I/O pad design 68 while FIG. 21 shows a center type pad
design 70.
[0166] While the peripheral I/O pad design 68 that is shown in FIG.
20 provides evenly distributed mechanical support for the device
50, this is not the case for the center pad design 70 that is shown
in FIG. 21. For this kind of design, additional mechanical support
can be provided to the device 50; this is shown in a top view in
FIG. 22. The elements highlighted as 70 in FIG. 22 are the solder
bumps that have been created on the I/O contact pads of the device
50; elements 72 are dummy solder bumps that can be provided in
order to lend mechanical support to the device 50. The symmetry of
the dummy bumps 72 as shown in FIG. 22 makes clear that the device
50 is, with the dummy bumps 72, adequately and symmetrically
supported.
[0167] In mounting semiconductor devices on the surface of a BGA
substrate, it is important from a manufacturing point of view that
solder flux, after the process of the solder flow has been
completed, can be readily removed. This requires easy access to the
surface areas of the BGA substrate where the solder flux has been
able to accumulate. In addition, the device interconnects
(consisting of pillar metal and solder bumps) must, after the
pillar metal and the solder bumps have been formed in accordance
with the related application, be readily available so that device
encapsulants can be adequately applied. More importantly, after
flip-chip assembly and solder reflow, the flux that has accumulated
in the gap between the semiconductor die and the substrate must be
cleaned. For these reasons, it is of value to apply the solder mask
not across the entire surface of the substrate (blank deposition)
but to leave open the surface areas of the substrate that are
immediately adjacent to the I/O interconnects (of pillar metal and
solder bumps). This design will create a channel though which the
cleaning solution can flow easily. This is highlighted in a top
view of FIGS. 23 and 24, where is shown: [0168] 52, the BGA
substrate on the surface of which the device 50 (not shown) is
mounted, [0169] 74, I/O contact pads provided on the surface of the
substrate 52, [0170] 76, interconnect traces provided on the
surface of the substrate 52, connected with the contact pads 74,
[0171] 79, the surface region of the substrate 52 over which no
solder mask is applied, and [0172] 80, the surface region of the
substrate 52 over which a solder mask is applied.
[0173] This is further highlighted in the cross section of the
substrate 52 that is shown in FIG. 24. It is clear that over the
region 79, which is the region where no solder mask is applied, the
metal pads 74 are readily available so that removal of solder flux
and the dispensing of encapsulants can be performed. It must be
remembered that this is possible due to the height of the combined
pillar metal 54 and the solder bump 56, which results in adequate
spacing between the device 50 and the surface of the substrate 52.
Further shown in FIG. 24 are routing traces 82 that are provided on
the surface of the substrate 52 for additional interconnect.
[0174] FIGS. 25 and 26 show how prior-art procedures and
conventions are applied to affect flux removal and encapsulant
application. In the prior-art application, the metal pads 74 are
typically surrounded by the solder mask 78, even for small pitch
I/O pad designs. Typically, the solder mask is determined by the
type of contact pad design (FIGS. 19 through 21), whereby the
contact pads 74 require about 60 .mu.m clearance for reasons of
proper alignment registration. This results in the substrate design
rule being more critical, allowing for less error and smaller
tolerance in the design parameters. In addition, the height of the
solder mask 78 is generally about 10 .mu.m larger than the height
of the contact pad 74, further forming an obstacle in applying
molding compound or in removing flux after the solder process has
been completed. These aspects of the prior art are shown in FIGS.
25 and 26, where the metal pads 74 are completely surrounded by the
solder mask 78. The present invention negates the highlighted
negative effects of the solder mask on flux cleaning and on
dispensing molding compound.
[0175] FIGS. 27a through 27f show examples of applications of the
invention, as follows:
[0176] FIG. 27a shows the application of a solder mask over the
surface that has previously been shown in FIG. 19, the solder mask
has been indicated with cross-hatched regions 90, and the regions
where no solder mask is present have been highlighted with 91.
[0177] FIGS. 27b and 27c relate to the previous FIG. 20, and the
solder mask has been highlighted as regions 90 while the regions
where no solder mask is present have been highlighted with 91. The
design that is shown in FIG. 27c is considered a "partial"
peripheral type I/O pad configuration of a semiconductor device
since the I/O pads 68 are only provided along two opposing sides of
the semiconductor device 50.
[0178] It must be noted that the designs that are shown in FIGS.
27b and 27c can further be provided with supporting dummy solder
bumps in the regions of the solder mask 90, and these supporting
dummy solder bumps have not been shown in FIGS. 27b and 27c.
[0179] FIG. 27d shows the design that has previously been shown in
FIG. 21. FIG. 27e shows a design that is similar to the design of
FIG. 27d with the exception that the contact points 70 have now
been provided in two columns. It is clear from these two drawings
that channels have been created in the solder mask 90 that are in
line with and include the contact pads. These channels allow for
easy flow of cleaning fluid and therefore allow for easy removal of
solder flux after the process of chip encapsulation and solder flow
has been completed.
[0180] FIG. 27f relates to the previously shown FIG. 22, and the
above observation relating to the creation of a channel allowing
for easy removal of the solder flux and for the easy flow of
cleaning fluid equally applies to the design which is shown in FIG.
27f.
[0181] FIGS. 28a and 28b demonstrate how the invention leads to the
ability to reduce the pitch between I/O pads.
[0182] FIG. 28a shows how in prior art applications the solder mask
90 is provided, further shown in FIG. 28a are: [0183] 94, the
circumference of the opening that is created in the solder mask 90,
[0184] 95, the circumference of the bond pad on the surface of a
semiconductor device, [0185] 92, the distance (or spacing) S
between two adjacent contact pads, and [0186] 93, the diameter D of
a contact pad.
[0187] In prior art applications as shown in FIG. 28a, the pitch
between adjacent contact pads is P=D+S+2.times.(the required
clearance between adjacent contact pads). The required clearance is
needed by the solder mask and requires that extra space is provided
between the circumference 95 of the contact pad and the
circumference 94 of the opening created in the solder mask.
[0188] With the wide channel created by the invention through the
solder mask, highlighted as a channel 91 in FIG. 28b, the
conventional clearance is not required, resulting in the ability to
reduce the pitch between adjacent contact pads 95. This leads to a
distance 92', FIG. 28b, which is smaller than the distance 92 of
FIG. 28a.
[0189] Although the invention has been described and illustrated
with reference to specific illustrative embodiments thereof, it is
not intended that the invention be limited to those illustrative
embodiments. Those skilled in the art will recognize that
variations and modifications can be made without departing from the
spirit of the invention. It is therefore intended to include within
the invention all such variations and modifications which fall
within the scope of the appended claims and equivalents
thereof.
* * * * *