U.S. patent application number 12/192742 was filed with the patent office on 2009-09-17 for semiconductor chip package having ground and power regions and manufacturing methods thereof.
Invention is credited to Chien-Wen Chen, Pao-Huei Chang Chien, Ping-Cheng Hu.
Application Number | 20090230524 12/192742 |
Document ID | / |
Family ID | 41062123 |
Filed Date | 2009-09-17 |
United States Patent
Application |
20090230524 |
Kind Code |
A1 |
Chien; Pao-Huei Chang ; et
al. |
September 17, 2009 |
SEMICONDUCTOR CHIP PACKAGE HAVING GROUND AND POWER REGIONS AND
MANUFACTURING METHODS THEREOF
Abstract
A semiconductor package and related methods are described. In
one embodiment the semiconductor package includes a die pad, a
plurality of leads, a semiconductor chip, and a package body. The
die pad includes a first part that includes a lower surface and a
first peripheral edge region comprising a ground region. The die
pad further includes a second part that is spaced apart from the
first part and that includes a lower surface and a second
peripheral edge region comprising a power region. The plurality of
leads is disposed around the die pad. The semiconductor chip is
disposed on the die pad and is electrically coupled to the ground
region, the power region, and the plurality of leads. The package
body is formed over the semiconductor chip and the plurality of
leads.
Inventors: |
Chien; Pao-Huei Chang;
(Fengshan City, TW) ; Hu; Ping-Cheng; (Kaohsiung
City, TW) ; Chen; Chien-Wen; (Kaohsiung City,
TW) |
Correspondence
Address: |
COOLEY GODWARD KRONISH LLP;ATTN: Patent Group
Suite 1100, 777 - 6th Street, NW
Washington
DC
20001
US
|
Family ID: |
41062123 |
Appl. No.: |
12/192742 |
Filed: |
August 15, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61036470 |
Mar 14, 2008 |
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Current U.S.
Class: |
257/676 ;
257/E21.51; 257/E23.037; 438/123 |
Current CPC
Class: |
H01L 2224/32257
20130101; H01L 21/4832 20130101; H01L 2924/01029 20130101; H01L
2224/49433 20130101; H01L 2224/48091 20130101; H01L 24/97 20130101;
H01L 2924/19041 20130101; H01L 2224/48247 20130101; H01L 2924/01033
20130101; H01L 2924/00014 20130101; H01L 24/48 20130101; H01L
2924/01078 20130101; H01L 2224/92247 20130101; H01L 2224/97
20130101; H01L 2224/73265 20130101; H01L 2924/181 20130101; H01L
2924/12041 20130101; H01L 2924/07802 20130101; H01L 2924/01075
20130101; H01L 23/3107 20130101; H01L 23/49582 20130101; H01L
2924/01087 20130101; H01L 2924/01079 20130101; H01L 2224/32145
20130101; H01L 2924/30105 20130101; H01L 2924/01046 20130101; H01L
2924/01013 20130101; H01L 23/49548 20130101; H01L 24/73 20130101;
H01L 2924/01082 20130101; H01L 2224/32245 20130101; H01L 2224/97
20130101; H01L 2224/85 20130101; H01L 2224/48091 20130101; H01L
2924/00014 20130101; H01L 2224/73265 20130101; H01L 2224/32145
20130101; H01L 2224/48247 20130101; H01L 2924/00012 20130101; H01L
2224/73265 20130101; H01L 2224/32245 20130101; H01L 2224/48247
20130101; H01L 2924/00012 20130101; H01L 2224/92247 20130101; H01L
2224/73265 20130101; H01L 2224/32245 20130101; H01L 2224/48247
20130101; H01L 2924/00 20130101; H01L 2224/97 20130101; H01L
2224/73265 20130101; H01L 2224/32245 20130101; H01L 2224/48247
20130101; H01L 2924/00 20130101; H01L 2924/07802 20130101; H01L
2924/00 20130101; H01L 2224/97 20130101; H01L 2224/73265 20130101;
H01L 2224/32145 20130101; H01L 2224/48247 20130101; H01L 2924/00
20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101; H01L
2924/00014 20130101; H01L 2224/45099 20130101; H01L 2924/00014
20130101; H01L 2224/45015 20130101; H01L 2924/207 20130101 |
Class at
Publication: |
257/676 ;
438/123; 257/E23.037; 257/E21.51 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 21/60 20060101 H01L021/60 |
Claims
1. A semiconductor package comprising: a die pad including: a first
part that includes: a first peripheral edge region comprising a
ground region; and a lower surface; a second part that is spaced
apart from the first part and that includes: a second peripheral
edge region comprising a power region; and a lower surface; a
plurality of leads disposed around the die pad; a first
semiconductor chip disposed on the die pad and electrically coupled
to the ground region, the power region, and the plurality of leads;
and a package body formed over the first semiconductor chip and the
plurality of leads.
2. The semiconductor package of claim 1, wherein the lower surfaces
of each of the first part and the second part have substantially
polygonal shapes.
3. The semiconductor package of claim 1, wherein: each of the
plurality of leads includes a lower surface having a first surface
area; the ground region is a ground segment; and a second surface
area of the lower surface of the first part is at least three times
greater than an average of the first surface areas of the plurality
of leads.
4. The semiconductor package of claim 1, wherein: each of the
plurality of leads includes a lower surface having a first surface
area; the power region is a power segment; and a second surface
area of the lower surface of the second part is at least three
times greater than an average of the first surface areas of the
plurality of leads.
5. The semiconductor package of claim 1, wherein the first part and
the second part are physically separated by a distance of between
0.1 millimeters and 0.3 millimeters.
6. The semiconductor package of claim 1, wherein the package body
substantially covers the die pad and the plurality of leads except
for at least the lower surfaces of the first part, the second part,
and the plurality of leads.
7. The semiconductor package of claim 1, wherein each part of the
die pad further includes: an upper surface; an upper sloped portion
disposed adjacent to the upper surface of the first part and the
second part; and a lower sloped portion disposed adjacent to the
lower surface of the first part and the second part; wherein the
package body substantially covers the upper sloped portions of the
first part and the second part, and the lower sloped portions of
the first part and the second part at least partially extend
outwardly from a lower surface of the package body.
8. The semiconductor package of claim 7, wherein a standoff
distance by which at least one part of the die pad extends
outwardly from the lower surface of the package body is between
twenty percent and fifty percent of a thickness of the at least one
part.
9. The semiconductor package of claim 7, wherein each of the
plurality of leads further includes: an upper surface; an upper
sloped portion disposed adjacent to the upper surface of the each
of the plurality of leads; and a lower sloped portion disposed
adjacent to the lower surface of the each of the plurality of
leads; wherein the package body substantially covers the upper
sloped portions of the plurality of leads, and the lower sloped
portions of the plurality of leads at least partially extend
outwardly from the lower surface of the package body.
10. The semiconductor package of claim 1, wherein: the first
peripheral edge region and the second peripheral edge region at
least partially define a cavity with a cavity bottom; and the
package body substantially fills the cavity.
11. The semiconductor package of claim 1, further comprising an
attachment layer and a second semiconductor chip coupled to an
upper surface of the first semiconductor chip by the attachment
layer, wherein the package body is formed over the second
semiconductor chip, and wherein the attachment layer includes an
adhesive layer.
12. A semiconductor package comprising: a die pad including: a base
including an upper surface and a lower surface; a protrusion
disposed adjacent to the base, wherein the protrusion includes: an
upper surface; and a lower surface; wherein at least a portion of
the protrusion is a ground region; and a first side surface
extending between the upper surface of the protrusion and the lower
surface of the protrusion, the first side surface including a first
peak; a plurality of leads disposed around the die pad, each
including a lower surface with a first surface area, and at least
one of the plurality of leads including a second side surface
including a second peak; a first power segment disposed adjacent to
the protrusion and including a lower surface with a second surface
area that is at least three times greater than an average of the
first surface areas of the plurality of leads; a semiconductor chip
disposed on the upper surface of the base and electrically coupled
to the ground region, the first power segment, and the plurality of
leads; and a package body formed over the semiconductor chip and
the plurality of leads so that the package body substantially
covers the upper surface of the base, at least a portion of the
first side surface above the first peak, and at least a portion of
the second side surface above the second peak, and so that at least
a portion of the first side surface below the first peak and at
least a portion of the second side surface below the second peak
protrude from a lower surface of the package body.
13. The semiconductor package of claim 12, wherein the ground
region surrounds the base.
14. The semiconductor package of claim 13, wherein the upper
surface of the protrusion includes a ground connection area that is
a ground ring.
15. The semiconductor package of claim 13, further comprising a
second power segment, wherein: the first power segment is adjacent
to a first side of the ground region; and the second power segment
is adjacent to a second side of the ground region.
16. The semiconductor package of claim 12, wherein a first spacing
of at least one of the plurality of leads and the ground region is
substantially equal to a second spacing of the first power segment
and the ground region.
17. The semiconductor package of claim 12, wherein: the ground
region is a ground segment; and a third surface area of the upper
surface of the protrusion is at least three times greater than the
average of the first surface areas of the plurality of leads.
18. A semiconductor package comprising: a die pad including: a base
including an upper surface and a lower surface; a protrusion
disposed adjacent to the base, wherein the protrusion includes: an
upper surface; and a lower surface with a first surface area;
wherein at least a portion of the protrusion is a ground segment;
and a first side surface extending between the upper surface of the
protrusion and the lower surface of the protrusion, the first side
surface including a first peak; a plurality of leads disposed
around the die pad, each including a lower surface with a second
surface area, and at least one of the plurality of leads including
a second side surface including a second peak, wherein the first
surface area is at least three times greater than an average of the
second surface areas of the plurality of leads; a semiconductor
chip disposed on the upper surface of the base and electrically
coupled to the ground segment and the plurality of leads; and a
package body formed over the semiconductor chip and the plurality
of leads so that the package body substantially covers the upper
surface of the base, at least a portion of the first side surface
above the first peak, and at least a portion of the second side
surface above the second peak, and so that at least a portion of
the first side surface below the first peak and at least a portion
of the second side surface below the second peak protrude from a
lower surface of the package body.
19. The semiconductor package of claim 18, wherein a standoff
distance by which the portion of the first side surface below the
first peak and the portion of the second side surface below the
second peak protrude from the lower surface of the package body is
between 0.025 millimeters and 0.0625 millimeters.
20. The semiconductor package of claim 18, further comprising a
marker lead disposed around the die pad, wherein a lower surface of
the marker lead has a different shape from the lower surfaces of
the plurality of leads.
21. A method of making a semiconductor package comprising:
providing a metal carrier plate including (1) a lower surface, (2)
an upper surface including a die receiving area, (3) a plurality of
peripheral bulges, each being disposed around the die receiving
area and having an upper surface, (4) a first metal coating formed
on the upper surfaces of the plurality of peripheral bulges, and
(5) a second metal coating formed on the lower surface of the metal
carrier plate below the plurality of peripheral bulges, a first
part of the die receiving area, and a second part of the die
receiving area; attaching a first semiconductor chip to the die
receiving area; electrically coupling the first semiconductor chip
to the plurality of peripheral bulges; forming a package body over
the first semiconductor chip and the plurality of peripheral
bulges; and etching areas on the lower surface of the metal carrier
plate without the second metal coating formed thereon such that (1)
the plurality of peripheral bulges, the first part of the die
receiving area, and the second part of the die receiving area are
separated from one another so as to form a plurality of leads, a
first part of a die pad, and a second part of the die pad that is
spaced apart from the first part, (2) each of the plurality of
leads includes a sloped etched area disposed adjacent to a lower
surface of the each of the plurality of leads, (3) each part of the
die pad includes a sloped etched area disposed adjacent to a lower
surface of the each part, and (4) the sloped etched areas of the
first part and the second part of the die pad and of the plurality
of leads at least partially extend outwardly from a lower surface
of the package body.
22. The method of claim 21, wherein: the first part of the die pad
includes a ground region; and the second part of the die pad
includes a power region.
23. The method of claim 21, wherein the first part of the die pad
and the second part of the die pad are separated by a distance of
between 0.1 millimeters and 0.3 millimeters.
24. The method of claim 21, wherein a standoff distance by which at
least one of the plurality of leads extends outwardly from the
lower surface of the package body is between twenty percent and
fifty percent of a thickness of the at least one of the plurality
of leads.
25. The method of claim 21, further comprising: attaching a second
semiconductor chip to an upper surface of the first semiconductor
chip by an attachment layer, wherein the second semiconductor chip
extends beyond a peripheral edge of the first semiconductor chip;
wherein the package body is formed over the second semiconductor
chip.
26. The method of claim 21, wherein the metal carrier plate is
formed by: providing a copper plate having an upper surface and a
lower surface; applying a first photoresist layer on the upper
surface of the copper plate and a second photoresist layer on the
lower surface of the copper plate; photoimaging and developing
predetermined portions of the first photoresist layer and the
second photoresist layer so as to create first exposed portions of
the upper surface of the copper plate and second exposed portions
of the lower surface of the copper plate; forming the first metal
coating on the first exposed portions and the second metal coating
on the second exposed portions; stripping the first photoresist
layer; etching areas on the upper surface of the copper plate
without the first metal coating formed thereon so as to form the
die receiving area and the plurality of peripheral bulges; and
stripping the second photoresist layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims the benefit of the following
commonly owned U.S. provisional patent application, which is
incorporated herein by reference in its entirety: U.S. Provisional
Patent Application No. 61/036,470, Attorney Docket No.
ASEG-001/00US, entitled "Chip Package Structure and Manufacturing
Methods Thereof," filed on Mar. 14, 2008.
FIELD OF THE INVENTION
[0002] The present invention relates generally to semiconductor
chip packages. More particularly, this invention relates to a
semiconductor chip package having ground and power regions and
manufacturing methods thereof.
BACKGROUND OF THE INVENTION
[0003] Semiconductor chips have become progressively more complex,
driven in large part by the need for increasing processing power in
a smaller chip size. In response, packaging technologies have
evolved, for example, to enable an increased lead density, which
can reduce the footprint area of a package mounted on a printed
circuit board (PCB). Some packaging technologies, such as Quad Flat
No Lead (QFN), may enable this increased lead density by providing
inner and outer rows of leads connected to a disposable portion of
a leadframe. However, manufacturing processes for such leadframes
may not be scalable beyond two rows of leads. As lead density
requirements further increase, it may be desirable to use packaging
technologies that are more scalable in terms of lead density.
[0004] As semiconductor chips become more complex, the number of
bonding pads on a chip may increase to enable additional electrical
connections. Between 25 and 30 percent of these bonding pads can be
used for ground and power connections of the chip. The ground
connections can be to an upper surface of a ground ring that
extends completely around the chip. Similarly, the power
connections can be to an upper surface of a power ring that extends
completely around the ground ring. Leads can then substantially
surround the power ring. To prevent short-circuits, the ground
ring, the power ring, and the leads are all typically physically
separated from each other by a minimum separation distance. The
combination of the ground ring, the power ring, and the separation
distance between the ground ring and the power ring can occupy, and
thus exclude leads from, a significant percentage of the footprint
area of a package. It may be desirable to reduce package size by
reducing the area requirements of the ground and power connections
of the chip.
[0005] Moreover, it may be desirable to further reduce package size
in additional ways, such as by reducing package height. At the same
time, it may be desirable to maintain sufficient mold locking of
leads to a package body. In addition, it may be desirable to
facilitate surface mounting of the package to a PCB. For example,
it may be difficult to determine how to properly orient the package
during surface mounting to the PCB. It may also be desirable to
increase the reliability of surface mounting of the package to the
PCB. For example, stress due to differential thermal expansion
between the leads and the package body may be concentrated at the
corners of the package, which can lead to cracking of solder
connections to the PCB near the corners of the package, and thus to
a decrease in the reliability of surface mounting. It may also be
desirable to formulate a packaging process designed to meet these
objectives. Current packaging solutions can meet some of these
objectives but may not be able to meet most, or all, of these
objectives.
[0006] It is against this background that a need arose to develop
the chip package and associated manufacturing methods described
herein.
SUMMARY OF THE INVENTION
[0007] In one innovative aspect, the invention relates to a
semiconductor package. In one embodiment, the semiconductor package
includes a die pad, a plurality of leads, a semiconductor chip, and
a package body. The die pad includes: (1) a first part that
includes a lower surface and a first peripheral edge region
comprising a ground region; and (2) a second part that is spaced
apart from the first part and that includes a lower surface and a
second peripheral edge region comprising a power region. The
plurality of leads is disposed around the die pad. The
semiconductor chip is disposed on the die pad and is electrically
coupled to the ground region, the power region, and the plurality
of leads. The package body is formed over the semiconductor chip
and the plurality of leads.
[0008] In another innovative aspect, the invention relates to a
semiconductor package. In one embodiment, the semiconductor package
includes a die pad, a plurality of leads, a power segment, a
semiconductor chip, and a package body. The die pad includes: (1) a
base including an upper surface and a lower surface; (2) a
protrusion disposed adjacent to the base, wherein the protrusion
includes an upper surface and a lower surface, and wherein at least
a portion of the protrusion is a ground region; and (3) a first
side surface extending between the upper surface of the protrusion
and the lower surface of the protrusion, the first side surface
including a first peak. The plurality of leads is disposed around
the die pad, each including a lower surface with a first surface
area. At least one of the plurality of leads includes a second side
surface including a second peak. The power segment is disposed
adjacent to the protrusion, and includes a lower surface with a
second surface area that is at least three times greater than an
average of the first surface areas of the plurality of leads. The
semiconductor chip is disposed on the upper surface of the base and
is electrically coupled to the ground region, the power segment,
and the plurality of leads. The package body is formed over the
semiconductor chip and the plurality of leads so that the package
body substantially covers the upper surface of the base, at least a
portion of the first side surface above the first peak, and at
least a portion of the second side surface above the second peak.
The package body is also formed over the semiconductor chip and the
plurality of leads so that at least a portion of the first side
surface below the first peak and at least a portion of the second
side surface below the second peak protrude from a lower surface of
the package body.
[0009] In a further innovative aspect, the invention relates to a
semiconductor package. In one embodiment, the semiconductor package
includes a die pad, a plurality of leads, a semiconductor chip, and
a package body. The die pad includes: (1) a base including an upper
surface and a lower surface; (2) a protrusion disposed adjacent to
the base, wherein the protrusion includes an upper surface and a
lower surface with a first surface area, and wherein at least a
portion of the protrusion is a ground segment; and (3) a first side
surface extending between the upper surface of the protrusion and
the lower surface of the protrusion, the first side surface
including a first peak. The plurality of leads is disposed around
the die pad, each including a lower surface with a second surface
area, where the first surface area is at least three times greater
than an average of the second surface areas of the plurality of
leads. At least one of the plurality of leads includes a second
side surface including a second peak. The semiconductor chip is
disposed on the upper surface of the base and is electrically
coupled to the ground segment and the plurality of leads. The
package body is formed over the semiconductor chip and the
plurality of leads so that the package body substantially covers
the upper surface of the base, at least a portion of the first side
surface above the first peak, and at least a portion of the second
side surface above the second peak. The package body is also formed
over the semiconductor chip and the plurality of leads so that at
least a portion of the first side surface below the first peak and
at least a portion of the second side surface below the second peak
protrude from a lower surface of the package body.
[0010] In a further innovative aspect, the invention relates to a
method of making a semiconductor package. In one embodiment, the
method includes providing a metal carrier plate including: (1) a
lower surface; (2) an upper surface including a die receiving area;
(3) a plurality of peripheral bulges, each being disposed around
the die receiving area and having an upper surface; (4) a first
metal coating formed on the upper surfaces of the plurality of
peripheral bulges; and (5) a second metal coating formed on the
lower surface of the metal carrier plate below the plurality of
peripheral bulges, a first part of the die receiving area, and a
second part of the die receiving area. The method further includes
attaching a semiconductor chip to the die receiving area,
electrically coupling the semiconductor chip to the plurality of
peripheral bulges, and forming a package body over the
semiconductor chip and the plurality of peripheral bulges. The
method further includes etching areas on the lower surface of the
metal carrier plate without the second metal coating formed thereon
such that: (1) the plurality of peripheral bulges, the first part
of the die receiving area, and the second part of the die receiving
area are separated from one another so as to form a plurality of
leads, a first part of a die pad, and a second part of the die pad
that is spaced apart from the first part; (2) each of the plurality
of leads includes a sloped etched area disposed adjacent to a lower
surface of the each of the plurality of leads; (3) each part of the
die pad includes a sloped etched area disposed adjacent to a lower
surface of the each part; and (4) the sloped etched areas of the
first part and the second part of the die pad and of the plurality
of leads at least partially extend outwardly from a lower surface
of the package body.
[0011] Other aspects and embodiments of the invention are also
contemplated. The foregoing summary and the following detailed
description are not meant to restrict the invention to any
particular embodiment but are merely meant to describe some
embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] For a better understanding of the nature and objects of some
embodiments of the invention, reference should be made to the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0013] FIG. 1 illustrates a cross-sectional view of a semiconductor
package, in accordance with one embodiment of the present
invention;
[0014] FIG. 2 illustrates a cross-sectional, enlarged view of a die
pad, in accordance with one embodiment of the present
invention;
[0015] FIG. 3 illustrates a cross-sectional, enlarged view of a
lead, in accordance with one embodiment of the present
invention;
[0016] FIG. 4 illustrates a top view of a portion of a metal
carrier plate, in accordance with one embodiment of the present
invention;
[0017] FIG. 5 illustrates processing operations for making a metal
carrier plate, in accordance with one embodiment of the present
invention;
[0018] FIG. 6 illustrates processing operations for making a
semiconductor package, in accordance with one embodiment of the
present invention;
[0019] FIG. 7 illustrates processing operations for making a
semiconductor package including multiple stacked dies or chips, in
accordance with one embodiment of the present invention;
[0020] FIG. 8 illustrates processing operations for making a
semiconductor package and surface mounting the semiconductor
package, in accordance with one embodiment of the present
invention;
[0021] FIG. 9 illustrates processing operations for making a
semiconductor package and surface mounting the semiconductor
package, in accordance with another embodiment of the present
invention;
[0022] FIG. 10 illustrates a top view of a portion of a metal
carrier plate including a marker bulge and enlarged peripheral
bulges, in accordance with one embodiment of the present
invention;
[0023] FIG. 11 illustrates a cross-sectional view of a
semiconductor package, in accordance with the embodiment of FIG.
10;
[0024] FIG. 12 illustrates a top view of a portion of a metal
carrier plate including a die receiving area including a peripheral
edge region, in accordance with one embodiment of the present
invention;
[0025] FIG. 13 illustrates a bottom view of the portion of the
metal carrier plate of FIG. 12, in accordance with one embodiment
of the present invention;
[0026] FIG. 14 illustrates processing operations for making a
semiconductor package including a ground region, in accordance with
one embodiment of the present invention;
[0027] FIG. 15 illustrates a top view of a portion of a metal
carrier plate including enlarged peripheral bulges and a die
receiving area including a peripheral edge region, in accordance
with one embodiment of the present invention;
[0028] FIG. 16 illustrates a bottom view of the portion of the
metal carrier plate of FIG. 15, in accordance with one embodiment
of the present invention;
[0029] FIG. 17 illustrates processing operations for making a
semiconductor package including a ground region and a power region,
in accordance with one embodiment of the present invention;
[0030] FIG. 18 illustrates a top view of a portion of a metal
carrier plate including parts of a die receiving area including
multiple parts, in accordance with one embodiment of the present
invention;
[0031] FIG. 19 illustrates a bottom view of the portion of the
metal carrier plate of FIG. 18, in accordance with one embodiment
of the present invention; and
[0032] FIG. 20 illustrates processing operations for making a
semiconductor package including a die pad with separated parts, in
accordance with one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0033] FIG. 1 illustrates a cross-sectional view of a semiconductor
package 100, in accordance with one embodiment of the present
invention. The package 100 includes a die pad 101 with a peripheral
edge region 114 that defines a cavity 111 with a cavity bottom 112.
The peripheral edge region 114 may completely surround the cavity
111, but also can partially surround the cavity 111 for certain
implementations. The cavity bottom 112 includes a central portion
112a. The cavity bottom 112 may also include a recess 112b around
the central portion 112a. The central portion 112a may be
approximately centrally located within the cavity bottom 112, but
need not be if, for example, the recess 112b is of non-uniform
width. The recess 112b may completely surround the central portion
112a, but also can partially surround the central portion 112a for
certain implementations. A chip 102 is attached to the cavity
bottom 112 by an adhesive layer (not shown). The adhesive layer may
be a conductive or a non-conductive adhesive material, such as
non-conductive epoxy. In the illustrated embodiment, the chip 102
is attached to the central portion 112a. Bonding pads 106 on the
active surface of the chip 102 are electrically coupled to leads
171 through bonding wires 104, and may also be electrically coupled
to at least part of the peripheral edge region 114 through bonding
wires 104. The leads 171 are disposed around the die pad 102, and
may completely or partially surround the die pad 101.
[0034] FIG. 2 illustrates a cross-sectional, enlarged view of the
die pad 101, in accordance with one embodiment of the present
invention. The die pad 101 includes a side surface 208, which may
completely or partially extend around a circumference of the die
pad 101. In the illustrated embodiment, the side surface 208
includes an upper sloped portion 208c disposed adjacent to an upper
surface 151 of the peripheral edge region 114 and facing away from
the cavity 111. The side surface 208 also includes a lower sloped
portion 208a disposed adjacent to the upper sloped portion 208c and
facing away from the cavity 111. The peripheral edge region 114
also includes an upper sloped portion 218 disposed adjacent to the
upper surface 151 and facing toward the cavity 111. Sloped portions
208a, 208c, and 218 may be linear or curved, and are typically
non-perpendicular to the upper surface 151 of the peripheral edge
region 114. The side surface 208 also includes a peak 208b.
[0035] FIG. 3 illustrates a cross-sectional, enlarged view of a
lead 171, in accordance with one embodiment of the present
invention. The lead 171 includes a side surface 308, which may
completely or partially extend around a circumference of the lead
171. In the illustrated embodiment, the side surface 308 includes
an upper sloped portion 308c disposed adjacent to an upper surface
155 of the lead 171. The side surface 308 also includes a lower
sloped portion 308a disposed adjacent to a lower surface 157 of the
lead 171. Sloped portions 308a and 308c may be linear or curved,
and are typically non-perpendicular to the upper surface 155 and
the lower surface 157 of the lead 171. The side surface 308 also
includes a peak 308b.
[0036] Referring back to FIG. 1 along with FIG. 2 and FIG. 3, a
package body 108 is formed over the chip 102, the die pad 101, and
the leads 171 so that the package body 108 substantially fills the
cavity 111 and substantially covers the upper sloped portions 218
of the peripheral edge region 114. The package body 108 also
substantially covers the upper sloped portions 208c of the die pad
101, and the upper sloped portions 308c of the leads 171. In this
context, the term "substantially" indicates, in part, that the
cavity 111 having the chip 102 disposed on the cavity bottom 112 is
filled by the package body 108; the term also indicates that the
package body 108 typically fills the cavity 111 to sufficiently
minimize or reduce pockets of air and moisture, and covers the chip
102, the bonding wires 104, and the upper sloped portions 208c,
218, and 308c to provide sufficient protection from oxidation,
moisture, and other environmental conditions to meet packaging
application requirements. In the illustrated embodiment, the lower
sloped portions 208a of the die pad 101 and the lower sloped
portions 308a of the leads 171 at least partially extend outwardly
from a lower surface 160 of the package body 108. Alternatively,
either the lower sloped portions 208a of the die pad 101 or the
lower sloped portions 308a of the leads 171 may at least partially
extend outwardly from the lower surface 160 of the package body
108.
[0037] The sloping of the upper sloped portions 208c, 218, and 308c
can significantly increase the area of contact, and thus the
adhesion between the package body 108 and the die pad 101, and
between the package body 108 and the leads 171. This can thereby
enhance the mold locking of the die pad 101 and the leads 171 in
the package body 108. This can also prolong the path and time for
moisture diffusion into the package 100.
[0038] In the illustrated embodiment, the upper sloped portions
208c and 308c have substantially concave profiles. In this context,
the term "substantially" is used to indicate that the upper sloped
portions 208c and 308c are generally concave, i.e. rounded inwards
toward the center of the die pad 101 and the leads 171, but that
the upper sloped portions 208c and 308c may include surface
non-uniformities or roughness in the form of small peaks, such as
asperities, that may be rounded outwards from the center of the die
pad 101 and the leads 171. For example, FIG. 3 shows that the upper
sloped portion 308c of the lead 171 has an overall shape that is
generally rounded inward toward the center of the lead 171. At the
same time, the upper sloped portion 308c is roughly textured with
numerous asperities. These asperities engage the package body 108
during molding and thereby enhance mold locking of the lead 171 in
the package body 108. These asperities can be formed through
precisely controlled etching or some other suitable process.
Similarly, the lower sloped portions 208a and 308a may have
substantially concave profiles. In this context, the term
"substantially" is used to indicate that the lower sloped portions
208a and 308a are generally concave, i.e. rounded inwards toward
the center of the die pad 101 and the leads 171. For example, FIG.
2 shows that the lower sloped portion 308c of the lead 171 has an
overall shape that is generally rounded inward toward the center of
the lead 171. Similarly, the upper sloped portions 218 may have
substantially concave profiles. In this context, the term
"substantially" is used to indicate that the upper sloped portions
218 are generally concave, i.e. rounded inwards toward the center
of the peripheral edge region 114. For example, FIG. 2 shows that
the upper sloped portion 218 of the peripheral edge region 114 has
an overall shape that is generally rounded inward toward the center
of the peripheral edge region 114.
[0039] It will be understood that the die pad 101 may be
alternatively described. For example, in FIG. 2, the die pad 101
includes a base 202 with an upper surface 212 and a lower surface
153. In one embodiment, a protrusion 213 with an upper surface 151
extends upwardly from the base 202 and is disposed adjacent to a
peripheral edge of the base 202. A side surface 208 extends between
the upper surface 151 of the protrusion 213 and the lower surface
153 of the base 202, and includes a peak 208b. Alternatively, the
protrusion 213 may be disposed adjacent to the base 202, so that
the protrusion 213 also has a lower surface 253. The side surface
208 then extends between the upper surface 151 and the lower
surface 253 of the protrusion 213, and includes the peak 208b. A
side surface 218 also extends between the upper surface 151 of the
protrusion 213 and the upper surface 212 of the base 202.
[0040] In one embodiment, the upper surface 212 of the base 202
includes a central region 212a on which the chip 102 is disposed.
The upper surface 212 may also include a recess 212b around the
central region 212a. The central region 212a may be approximately
centrally located within the upper surface 212, but need not be if,
for example, the recess 212b is of non-uniform width. The recess
212b may completely surround the central region 212a, but also can
partially surround the central region 212a for certain
implementations.
[0041] It will also be understood that the package body 108 may be
alternatively described. For example, in FIG. 1, FIG. 2, and FIG.
3, the package body 108 is formed over the chip 102, the die pad
101, and the leads 171 so that the package body 108 substantially
covers the upper surface 212 of the base 202 and the side surface
218. The package body 108 also substantially covers at least a
portion of the side surface 208 above the peak 208b, and at least a
portion of the side surface 308 above the peak 308b. In this
context, the term "substantially" indicates, in part, that the
upper surface 212 of the base 202 having the chip 102 disposed
thereon is covered by the package body 108; the term also indicates
that the package body 108 typically covers the chip 102, the
bonding wires 104, the upper surface 212 of the base 202, the side
surface 218, the portion of the side surface 208 above the peak
208b, and the portion of the side surface 308 above the peak 308b
to provide sufficient protection from oxidation, moisture, and
other environmental conditions to meet packaging application
requirements. At least a portion of the side surface 208 below the
peak 208b protrudes from the lower surface 160 of the package body
108. Similarly, at least a portion of the side surface 308 below
the peak 308b protrudes from the lower surface 160 of the package
body 108.
[0042] The package 100 may further include a metal coating 116
disposed on the upper surface 151 of the peripheral edge region 114
as shown in FIG. 1, alternatively described as disposed on the
upper surface 151 of the protrusion 213 as shown in FIG. 2. The
package 100 may also include a metal coating 117 disposed on the
lower surface 153 of the die pad 101 as shown in FIG. 1,
alternatively described as disposed on the lower surface 153 of the
base 202 as shown in FIG. 2. Alternatively, the metal coating 117
may be described as being disposed on both the lower surface 153 of
the base 202 and the lower surface 253 of the protrusion 213, as
shown in FIG. 2. The package 100 may also include a metal coating
126 disposed on the upper surfaces 155 of the leads 171 as shown in
FIG. 1, and a metal coating 127 disposed on the lower surfaces 157
of the leads 171 as shown in FIG. 1. These metal coatings can be
disposed using techniques such as electrolytic plating and
electroless plating. It is desirable that these metal coatings
adhere well to the surfaces of the die pad 101 and the leads 171,
enable effective wire bonding with bonding wires 104, and protect
the lower surfaces of the die pad 101 and the leads 171 from
oxidation and other environmental conditions. With these goals in
mind, the metal coatings can include a layer of nickel in contact
with the surfaces 151 and 153 of the die pad 101 and the surfaces
155 and 157 of the leads 171, and a layer of gold or palladium
covering the layer of nickel. Alternatively, the metal coatings may
include a layer of an alloy of nickel and either one of, or both,
gold and palladium.
[0043] Referring to FIG. 1 along with FIG. 2 and FIG. 3, a standoff
distance 148 can refer to the distance that the lower sloped
portions 208a of the die pad 101 and/or the lower sloped portions
308a of the leads 171 extend outwardly from the lower surface 160
of the package body 108, and, for certain implementations, can
include or otherwise account for a thickness of the metal coatings
117 and 127. Alternatively, the standoff distance 148 can refer to
the distance that the portion of the side surface 208 below the
peak 208b and/or the portion of the side surface 308 below the peak
308b protrude from the lower surface 160 of the package body 108.
The protrusion of the die pad 101 and/or the leads 171 from the
lower surface 160 of the package body 108 can enhance the
solderability of the die pad 101 and the leads 171 to a PCB by
exposing additional area on the die pad 101 and or the leads 171 to
which solder can attach. This can increase the reliability of
surface mounting of the package 100 to the PCB. In one embodiment,
the peak 208b is disposed closer to the lower surface 153 of the
base 202 than to the upper surface 151 of the protrusion 213, and
the peaks 308b are disposed closer to the lower surfaces 157 of the
leads 171 than to the upper surfaces 155 of the leads 171.
[0044] For certain implementations, the standoff distance 148 is
between about twenty and about fifty percent or between about
twenty-five and about forty-five percent of a thickness 142 of the
die pad 101 and/or at least one of the leads 171, although the
standoff distance 148 is not constrained to this range and, for
other implementations, may be between about five percent and about
seventy-five percent of the thickness 142. The thickness 142 of the
die pad 101 can be measured as the distance between the upper
surface 151 of the peripheral edge region 114 and the lower surface
153 of the die pad 101. If metal coatings 116 and 117 are disposed
on surfaces 151 and 153 of the die pad 101, as is typically the
case, then the thickness 142 can be measured as the distance
between the upper surface 150 of the metal coating 116 and the
lower surface 152 of the metal coating 117. Similarly, for a lead
171, if metal coatings 126 and 127 are disposed on surfaces 155 and
157 of the lead 171, as is typically the case, then the thickness
142 can be measured as the distance between the upper surface 154
of the metal coating 126 and the lower surface 156 of the metal
coating 127. As described herein, various distances can be measured
relative to the surfaces of metal coatings 116, 117, 126, and 127.
However, it will be understood that these distances can be
similarly measured relative to the surfaces 151 and 153 of the die
pad 101 or the surfaces 155 and 157 of the leads 171, if any or all
of the metal coatings 116, 117, 126, and 127 are not present.
[0045] In one embodiment, the thickness 142 of the die pad 101
including metal coatings 116 and 117 is substantially equal to that
of at least one lead 171 including metal coatings 126 and 127, and
is about 0.125 millimeters. In this case, the standoff distance 148
by which the die pad 101 and the at least one lead 171 protrudes
from the lower surface 160 of the package body 108 is between about
0.025 millimeters and about 0.0625 millimeters or between about
0.03 millimeters and about 0.05 millimeters. Also, the peak 208b of
the side surface 208 of the die pad 101 is substantially level with
the peak 308b of the side surface 308 of the at least one lead 171.
In an alternative embodiment, the thickness 142 of the die pad 101
and or the at least one lead 171 may be above or below 0.125
millimeters.
[0046] As the standoff distance 148 becomes a larger percentage of
the thickness 142 within the range of about twenty to about fifty
percent, the reliability of mold locking of the die pad 101 and/or
the leads 171 in the package body 108 typically tends to decrease,
while the reliability of surface mounting of the package 100 on a
PCB typically tends to increase. At the same time, the duration and
cost of bottom side etching (see FIG. 6) typically increases. The
choice of the standoff distance 148 as a percentage of the
thickness 142 can be a tradeoff between these factors.
[0047] A mold cap 140 can refer to the distance between an upper
surface 164 of the package body 108 and the upper surface 150 of
the metal coating 116. Similarly, for a lead 171, the mold cap 140
can be measured as the distance between the upper surface 164 of
the package body 108 and the upper surface 154 of the metal coating
126. The mold cap 140 is typically large enough so that the chip
102 and the bonding wires 104 are enclosed within the package body
108. In one embodiment, the mold cap 140 is between about 0.4
millimeters and about 1 millimeter, such as about 0.675
millimeters, although the mold cap 140 can be smaller so long as
the chip 102 and the bonding wires 104 remain sufficiently enclosed
within the package body 108. The inclusion of the cavity 111 in the
die pad 101 can enable the chip 102 to be disposed on the central
portion 112a of the cavity bottom 112 as shown in FIG. 1.
Alternatively, the chip 102 can be disposed on the central region
212a of the upper surface 212 of the base 202 as shown in FIG.
2.
[0048] In FIG. 1 and FIG. 2, distance 206 measures a depth of the
central portion 112a (or central region 212a) relative to the upper
surface 150 of the metal coating 116. Distance 204 measures a depth
of the recess 112b (or recess 212b) relative to the upper surface
150 of the metal coating 116. For certain implementations, the
distance 206 is between about fifty-five and about eighty percent
of the distance 204, although the distance 206 is not constrained
to this range. In one embodiment, the distance 206 is about 0.065
millimeters and the distance 204 is about 0.095 millimeters. Both
the distances 204 and 206 may vary above or below these values, so
long as the distances 204 and 206 remain less than the thickness
142 of the die pad 101 by some margin, such as about 0.01
millimeters. Preferably, the central portion 112a (or central
region 212a) and the recess 112b (or recess 212b) are the result of
etching (see FIG. 5), rather than plating to build up the
peripheral edge region 114 (or central protrusion 213). Plating may
be both more costly and time consuming than the etching process
subsequently described and shown in FIG. 5.
[0049] By disposing the chip 102 on the cavity bottom 112 (or upper
surface 212 of the base 202), the top surface of the chip 102 is
lower by the distance 206 relative to the upper surface 150 of the
metal coating 116, and relative to the upper surfaces 154 of the
metal coating 126 on each lead 171. As a result, the mold cap 140
can be reduced, which can make the package 100 thinner. In
addition, the lower surface of the chip 102 is closer by distance
206 to the lower surface 152 of the metal coating 117. This can
enhance heat dissipation from the chip 102 through the die pad
101.
[0050] Referring to FIG. 1 along with FIG. 2 and FIG. 3, a height
difference 146 refers to the distance between a plane 166 through
the highest point of the central portion 112a (or central region
212a) and the lower surface 160 of the package body 108. The lower
surface 160 of the package body 108 typically corresponds, at least
approximately, to the lower surface of the package body 108 within
the recess 112b (or recess 212b). For certain implementations, the
height difference 146 is between about 0.02 millimeters and about
0.04 millimeters, although the height difference 146 is not
constrained to this range. For certain implementations, the upper
surface 150 of the metal coating 116 can be disposed between about
0.05 millimeters and about 0.08 millimeters above the plane 166,
but is not constrained to this range. Also, the peak 208b of the
side surface 208 of the die pad 101 and the peak 308b of the side
surface 308 of at least one lead 171 may be disposed below the
plane 166. The height difference 146 and the positioning of the
peaks 208b and 308b relative to the plane 166 can be controlled by
etching, such as through a top side etching process (see FIG.
5).
[0051] Distance 144 refers to the minimum distance from side
surface 162 of the package body 108 to side surfaces 308 of any of
the leads 171. In the embodiment of FIG. 1, distance 144 is
illustrated as the distance from the side surface 162 to the peak
308b of the leftmost outer lead 171A. For certain implementations,
the distance 144 is between about 0.1 millimeters and about 0.3
millimeters, although the distance 144 is not constrained to this
range. The portion of the package body 108 to the left of leftmost
outer lead 171A (and similarly to the right of rightmost outer lead
171B) can prevent peeling and detachment of the outer leads 171A
and 171B during singulation (see FIG. 6) and during use of the
package 100.
[0052] Lead spacing 145, also referred to as terminal pitch, refers
to the distance between the centers of a pair of adjacent leads
171. For certain implementations, the lead spacing 145 is between
about 0.35 and about 0.55 millimeters, although the lead spacing
145 is not constrained to this range. The lead spacing 145 can be
controlled by etching, such as through a top side etching process
(see FIG. 5).
[0053] In FIG. 3, a protective layer 310 is shown substantially
covering the lower sloped portion 308a of at least one of the
plurality of leads 171. In this context, the term "substantially"
indicates that the protective layer 310 typically covers the lower
sloped portion 308a of the at least one lead 171 to sufficiently
protect the underlying metal from oxidation, moisture, and other
environmental conditions to meet packaging application
requirements. The package body substantially covers the upper
sloped portion 308c (or the portion of the side surface 308 above
the peak 308b), but does not entirely cover the lower sloped
portion 308a (or the portion of the side surface 308 below the peak
308b), or at least does not cover that part of the lower sloped
portion 308a that extends outwardly from the lower surface 160 of
the package body 108. As a result, the protective layer 310 is
included in addition to the protective metal coating 127 (see FIG.
1) on the lower surface 157 of the lead 171 to prevent or reduce
oxidation and corrosion of the underlying metal, which is typically
copper or a copper alloy. A similar protective layer may be applied
to the lower sloped portion 208a of the die pad 101 (or the portion
of the side surface 208 below the peak 208b). In FIG. 2, a
protective layer 210 is shown substantially covering the lower
sloped portion 208a of the die pad 101. The protective layer 210,
along with the protective metal coating 117 (see FIG. 1) on the
lower surface 153 of the die pad 101, sufficiently protects the
underlying metal of the die pad 101 to meet packaging application
requirements.
[0054] In one embodiment, the protective layers 210 and 310 can
include a metal coating. The metal coating may include at least one
of a layer of tin, a layer of nickel, and a layer of gold.
Alternatively, the metal coating may include a layer of an alloy of
two or more of these metals. The metal coating may be attached to
the lower sloped portions 208a and 308a using immersion,
electrolytic plating, electroless plating, or any other suitable
process.
[0055] In another embodiment, the protective layers 210 and 310 can
include a solder material. The solder material may include a solder
paste. The solder paste may be selectively disposed on the lower
sloped portions 208a and 308a, while the protective metal coatings
117 and 127 (without the solder paste) substantially cover the
lower surface 153 of the die pad 101 and the lower surface 157 of
at least one lead 171. In this context, the term "substantially"
indicates that the protective metal coatings 117 and 127 typically
cover the lower surfaces 153 and 157 to sufficiently protect the
underlying metal from oxidation, moisture, and other environmental
conditions to meet packaging application requirements. The
protective metal coatings 117 and 127 may also protect the
underlying metal during etching, as described and illustrated in
FIG. 5. Alternatively, the solder paste may be disposed on both the
lower sloped portions 208a and 308a and the lower surfaces 153 and
157. The solder paste is then dried or hardened. Alternatively, the
solder paste may be reflowed and hardened into a solder bump.
[0056] In another embodiment, the protective layers 210 and 310 can
include an organic solderability preservative (OSP) layer. The OSP
layer may be attached to the lower sloped portions 208a and 308a
using immersion or rinsing with a solution based on an organic
material, or any other suitable process. The organic material may
be an imidazole-based material. The OSP layer may be selectively
disposed on the lower sloped portions 208a and 308a, or
alternatively may be disposed on the lower sloped portions 208a and
308a, the lower surface 153 of the die pad 101, and the lower
surface 157 of at least one lead 171. If the OSP layer is disposed
on the lower surfaces 153 and 157, an additional processing
operation to remove the OSP layer may be omitted, as the OSP layer
typically evaporates at temperatures encountered when soldering the
die pad 101 and at least one lead 171 to a PCB.
[0057] The use of a solder material and/or an organic material as
part of protective layers 210 and 310 is desirable for at least two
reasons. First, typical solder materials and organic materials are
less costly than metals such as nickel, gold, and tin. Second,
solder materials and organic materials can be applied to the die
pad 101 and at least one lead 171 without using electrolytic or
electroless plating processes, which can simplify the creation of
the protective layers 210 and 310.
[0058] FIG. 4 illustrates a top view of a portion of a metal
carrier plate 400, in accordance with one embodiment of the present
invention. The metal carrier plate 400 may be formed as described
in FIG. 5. The metal carrier plate 400 includes a base 402, and the
base 402 has a central protrusion 404 extending upwardly from the
base 402. In this context, the term "central" indicates that the
protrusion 404 may be approximately centrally located within the
portion of the metal carrier plate 400 shown in FIG. 4. However,
the portion of the metal carrier plate 400 shown in FIG. 4 can be
variously located within the metal carrier plate 400, including
bordering the edge of the metal carrier plate 400. Although the
central protrusion 404 is shown as extending completely around a
circumference of the base 402 in FIG. 4, the central protrusion 404
may extend partially around the base 402 in another embodiment. A
plurality of peripheral protrusions 406 are disposed around the
base 402. Although the peripheral protrusions 406 are shown as
substantially completely surrounding the base 402 in FIG. 4, the
peripheral protrusions 406 may partially surround the base 402 in
another embodiment. A corner peripheral protrusion 408 at one of
the corners of the portion of the metal carrier plate 400 may be of
a different shape and or size from the other peripheral protrusions
406. This corner peripheral protrusion 408 may serve as a
recognition mark to facilitate the orientation, during surface
mounting, of a resulting package.
[0059] The hatched portions of the metal carrier plate 400 (404,
406, and 408) have not been etched, and therefore protrude from the
other portions of the metal carrier plate 400 (including part of
402), which have been etched from the top side (see FIG. 5). In one
embodiment, the peripheral protrusions 406 are disposed in at least
three rows on at least one side of the base 402. After bottom side
etching (see FIG. 6), the base 402 and the peripheral protrusions
406 are separated and formed into the die pad 101 and the leads
171, as previously described in FIGS. 1 through 3. Since the
peripheral protrusions 406 need not be connected to a disposable
portion of a leadframe, as is typically the case for a QFN
leadframe, the creation of multiple rows of leads 171 using the
processing operations of FIGS. 5 and 6 is significantly more
scalable to two or more such rows than is typical QFN
processing.
[0060] In one embodiment, after bottom side etching (see FIG. 6),
the central protrusion 404 may include a ground region to which a
chip (e.g., the chip 102) is electrically coupled using bonding
wires (e.g., the bonding wires 104). The ground region may
completely surround the base 402. Alternatively, the ground region
may include one or more ground segments that partially surround the
base 402. The central protrusion 404 may also include a power
region to which the chip 102 is electrically coupled, and the power
region may include one or more power segments. In one embodiment, a
ground segment may be a first portion 404a of the central
protrusion 404, and a power segment may be a second portion 404b of
the central protrusion 404. In this case, a first portion of the
base 402 connected to the ground segment 404a can be spaced apart
from a second portion of the base 402 connected to the power
segment 404b. The spacing apart may be performed using etching,
singulation, or any other suitable process to physically separate
the first portion of the base 402 from the second portion of the
base 402, such as along the dotted line 410.
[0061] It will be understood that the portion of the metal carrier
plate 400 shown in FIG. 4 may be alternatively described. For
example, the metal carrier plate 400 may include a die receiving
area 402 with a peripheral edge region 404. A plurality of
peripheral bulges 406 may be disposed around the die receiving area
402. Alternatively, the metal carrier plate 400 may include a
protrusion 404 disposed adjacent to the base 402.
[0062] FIG. 5 illustrates processing operations for making a metal
carrier plate 500, in accordance with one embodiment of the present
invention. A first photoresist layer 506 is formed on an upper
surface 502 of a copper plate 501, and a second photoresist layer
508 is formed on a lower surface 504 of the copper plate 501. The
photoresist layers 506 and 508 are formed by coating, printing, or
any other suitable technique. Predetermined or selected portions of
the photoresist layers 506 and 508 are photoimaged and developed so
as to create first exposed portions 510 and second exposed portions
512 of the copper plate 501. The photoresist layers 506 and 508 may
be photochemically defined using a photomask (not shown).
[0063] A first metal coating 514 is then formed on the exposed
portions 510, and a second metal coating 516 is formed on the
exposed portions 512. The metal coatings 514 and 516 can have the
same characteristics as previously described for metal coatings
116, 117, 126, and 127. The photoresist layers 506 and 508 are then
stripped. Areas 518 of the upper surface 502 of the copper plate
501 without the protection of the metal coating 514 are then etched
to form the metal carrier plate 500, including the previously
described central region 212a, central protrusion 213, and
peripheral protrusions 406. Alternatively, the etching may form the
previously described die receiving area 402 and peripheral bulges
406 as part of the metal carrier plate 500. This etching operation
may be referred to as top side etching.
[0064] The metal carrier plate 500 typically includes multiple
interconnected portions, such as portions 500a and 500b. Each
portion may include the previously described central region 212a,
central protrusion 213, and peripheral protrusions 406.
[0065] FIG. 6 illustrates processing operations for making the
semiconductor package 100, in accordance with one embodiment of the
present invention. A chip 102 is attached to a central region 212a
(or die receiving area 402) of each portion of a metal carrier
plate 500, such as portions 500a and 500b. Each chip 102 is
attached using an adhesive layer (not shown), as previously
described. Each chip 102 is then electrically coupled to peripheral
protrusions 406 (or peripheral bulges 406) through bonding wires
104. A package body 108 is then formed over each chip 102 and each
of the peripheral protrusions 406. The package body 108 may be
composed of a synthetic resin, and may be formed through molding
methods such as transfer molding. Areas 620 of the lower surface of
the metal carrier plate 500 without the protection of the metal
coating 516 are then etched to separate the peripheral protrusions
406 and the central protrusion 213 to form the previously described
leads 171 and die pad 101. This etching operation may be referred
to as bottom side etching. The leads 171 and the die pad 101 may be
formed in each of multiple connected packages sharing package body
108, such as connected packages 600a and 600b. Through singulation,
the connected packages 600a and 600b may be separated into packages
100a and 100b. Singulation can be carried out by, for example,
sawing, which can create substantially vertical side surfaces of
the packages 100a and 100b as shown in FIG. 6.
[0066] FIG. 7 illustrates processing operations for making a
semiconductor package 100 including multiple stacked dies or chips,
in accordance with one embodiment of the present invention. A first
chip 102a is attached to a central region 212a (or die receiving
area 402) of each portion of a metal carrier plate 500, such as
portions 500a and 500b. Each first chip 102a is attached using an
adhesive layer (not shown), as previously described. Each first
chip 102a may then be electrically coupled to at least one portion
of a central protrusion 213 (or peripheral edge region 404) through
bonding wires 104a. In another embodiment, each first chip 102a may
be electrically coupled to one or more peripheral protrusions
406.
[0067] An attachment layer 700 is then disposed on the upper
surface of each first chip 102a. A second chip 102b is then coupled
to the upper surface of each first chip 102a by the attachment
layer 700. Each second chip 102b may then be electrically coupled
to peripheral protrusions 406 through bonding wires 104b. In
another embodiment, each second chip 102b may be electrically
coupled to at least one portion of the central protrusion 213. Any
peripheral protrusion 406 or portion of the central protrusion 213
to which a second chip 102b is coupled can be electrically isolated
from any peripheral protrusion 406 or portion of the central
protrusion 213 to which a corresponding first chip 102a is
coupled.
[0068] The package body 108 is then formed over each set of stacked
chips 102a and 102b and each of the peripheral protrusions 406.
Areas 620 of the lower surface of the metal carrier plate 500
without the protection of the metal coating 516 are then etched to
separate the peripheral protrusions 406 and the central protrusion
213 to form the previously described leads 171 and die pad 101. The
leads 171 and the die pad 101 may be formed in each of multiple
connected packages sharing package body 108, such as connected
packages 600a and 600b. Through singulation, the connected packages
600a and 600b may be separated into packages 100a and 100b.
[0069] In one embodiment, the attachment layer 700 includes an
adhesive layer. The adhesive layer may be a conductive or a
non-conductive adhesive material, such as a non-conductive epoxy.
The adhesive layer may be a liquid-type adhesive layer or a
film-type adhesive layer, such as a double-sided tape. The adhesive
layer may also be a film-on-wire adhesive layer, which has similar
characteristics but is typically thicker than the film-type
adhesive layer.
[0070] In one embodiment, chip 102b extends beyond the peripheral
edge of chip 102a. One advantage of the film-on-wire adhesive layer
is that this adhesive layer can be sufficiently thick so that when
chip 102b is attached to this adhesive layer, there is still
sufficient clearance for bonding wires 104a attached to chip 102a.
If the film-on-wire adhesive layer is not used, then the attachment
layer 700 may include a spacer in addition to the liquid-type
and/or film-type adhesive layer. The purpose of the spacer is to
space apart chips 102a and 102b so that there is sufficient
clearance for bonding wires 104a attached to chip 102a.
[0071] As described previously, a resulting package 100 can be made
thinner by disposing the chip 102 on the cavity bottom 112 (or
upper surface 212 of the base 202). For a package 100 with stacked
chips such as in FIG. 7, it may be especially important to take
advantage of the additional space provided by the cavity 111 to
make the package 100 thinner. In addition, the ordering of stacking
may be important. For example, in FIG. 7, the chip 102b extends
beyond the cavity 111 and partly covers over the peripheral edge
region 114 of the die pad 101, so the chip 102b could not be
disposed on the cavity bottom 112. However, the chip 102a is sized
so that it can be disposed on the cavity bottom 112. In this case,
the chip 102b may be stacked on top of the chip 102a if the height
of the chip 102a plus the height of the attachment layer 700 is
large enough to provide sufficient clearance above the upper
surface 150 of the metal coating 116 disposed on the peripheral
edge region 114, and above the bonding wires 104a.
[0072] FIG. 8 illustrates processing operations for making a
semiconductor package 100 and surface mounting the semiconductor
package 100, in accordance with one embodiment of the present
invention. As described previously, leads 171 and die pad 101 may
be formed in each of multiple connected packages sharing a package
body 108, such as connected packages 600a and 600b. In this
embodiment, a solder paste 802 is disposed to substantially cover a
sloped etched area 308a of at least one lead 171, and a lower
surface 156 of a metal coating 127 disposed on the lower surface
157 of that lead 171. The solder paste 802 is then solidified for
defining a solder interface 802 for subsequent surface mounting.
Solder paste 800 may also be disposed to substantially cover a
sloped etched area 208a of the die pad 101, and a lower surface 152
of a metal coating 117 of the die pad 101. Through singulation, the
connected packages 600a and 600b are then separated into packages
100a and 100b.
[0073] For surface mounting the package 100a, the solder interfaces
800 and 802 may be reflowed to form liquefied solder masses 804 and
806. The liquefied solder masses 804 and 806 are then placed into
contact with a PCB 808 and hardened. The solder interfaces 800 and
802 typically contain enough solder so that upon reflow soldering
and surface mounting of the package 100a, the solder acts as a
protective layer for the sloped etched areas 208a and 308a by
substantially covering these areas.
[0074] In addition to the use of the solder as a protective layer,
another advantage of the surface mounting process of FIG. 8 is that
surface mounting of the package 100a can be achieved by reflowing
the solder interfaces 800 and 802. This removes the need for
additional solder paste on the PCB 808 as part of surface mounting
of the package 100a.
[0075] FIG. 9 illustrates processing operations for making a
semiconductor package 100 and surface mounting the semiconductor
package 100, in accordance with another embodiment of the present
invention. In this embodiment, the package 100 is provided without
solder interfaces 800 and 802 for surface mounting. A sloped etched
area 208a of a die pad 101 and a sloped etched area 308a of at
least one lead 171 may be substantially covered with a protective
layer such as an OSP layer, as described previously. Subsequently,
solder paste 900 is applied on a PCB 908 in preparation for surface
mounting of the package 100. After surface mounting of the package
100, the solder paste is reflowed and then hardened into solder
masses 902 attaching the package 100 to the PCB 908.
[0076] As described previously, enough solder paste 900 can be
applied on the PCB 908 so that upon surface mounting of the package
100 and reflow soldering, the solder acts as a protective layer for
the sloped etched areas 208a and 308a by substantially covering
those areas.
[0077] FIG. 10 illustrates a top view of a portion of a metal
carrier plate 1000 including a marker bulge 1008 and enlarged
peripheral bulges 1010, in accordance with one embodiment of the
present invention. The metal carrier plate 1000 may be formed as
described in FIG. 5. The metal carrier plate 1000 includes a die
receiving area 1002. The die receiving area 1002 may include a
peripheral edge region 1004. Although the peripheral edge region
1004 is shown as extending completely around an interior portion of
the die receiving area 1002 in FIG. 10, the peripheral edge region
1004 may extend partially around the interior portion of the die
receiving area 1002 in another embodiment. The portion of the metal
carrier plate 1000 shown in FIG. 10 can be variously located within
the metal carrier plate 1000, including bordering the edge of the
metal carrier plate 1000. A plurality of peripheral bulges 1006 are
disposed in a lead placement area 1001 around the die receiving
area 1002. Although the peripheral bulges 1006 and the lead
placement area 1001 are shown as substantially completely
surrounding the die receiving area 1002 in FIG. 10, the peripheral
bulges 1006 and the lead placement area 1001 may partially surround
the die receiving area 1002 in another embodiment. The marker bulge
1008 and the enlarged peripheral bulges 1010 may be located in
corner regions of the lead placement area 1001 as shown in FIG. 10,
or may be located elsewhere in the lead placement area 1001.
[0078] The hatched portions of the metal carrier plate 1000 (1004,
1006, 1008, and 1010) have not been etched, and therefore protrude
from the other portions of the metal carrier plate 1000 (including
part of 1002), which have been etched from the top side (see FIG.
5). As previously described in FIG. 4, the peripheral bulges 1006
are disposed in at least three rows on at least one side of the die
receiving area 1002.
[0079] FIG. 11 illustrates a cross-sectional view of a
semiconductor package 1100, in accordance with the embodiment of
FIG. 10. The cross-sectional view corresponds to cross-section A-A
shown in FIG. 10 after bottom side etching (see FIG. 6). The die
receiving area 1002, the peripheral bulges 1006, the marker bulge
1008, and the enlarged peripheral bulges 1010 are separated and
formed into the die pad 101, the leads 171, a marker lead 1108, and
enlarged leads 1110. The die pad 101 and the leads 171 are as
previously described in FIGS. 1 through 3. The marker lead 1108 and
the enlarged leads 1110 have characteristics similar to those of
the leads 171, except that the marker lead 1108 and the enlarged
leads 1110 may be of a different shape and/or size from the other
leads 171. In addition, the marker lead 1108 may be of a different
shape and/or size from the enlarged leads 1110. Because the marker
lead 1108 has a different size and/or shape from the enlarged leads
1110 and the rest of the leads 171, the marker lead 1108 may serve
as a recognition mark to facilitate the orientation, during surface
mounting, of the resulting package. Alternatively, the leads 1108
and 1110 may be similarly configured, and the semiconductor package
1100 may include a separate recognition mark, such as a mark formed
in the package body 108 or the die pad 101. The other
characteristics of the semiconductor package 1100 are as previously
described for the semiconductor package 100 in FIGS. 1 through 3.
It will be understood that multiple chips 102 may be stacked within
the semiconductor package 1100 as previously described in FIG.
7.
[0080] In one embodiment, a surface area of a lower surface 1118 of
the marker lead 1108 may be at least fifty percent greater than an
average of surface areas of a lower surface 157 of the other leads
171, such as at least 1.5 times, 2 times, or 3 times larger. Also,
an average of surface areas of lower surfaces 1120 of the enlarged
leads 1110 may be at least fifty percent greater than the average
of surface areas of the lower surface 157 of the other leads 171,
such as at least 1.5 times, 2 times, or 3 times larger. The marker
lead 1108 and the enlarged leads 1110 may be located in the corner
regions of the lead placement area 1001, as shown in FIG. 10.
During surface mounting, the enlarged surface areas of the lower
surfaces 1118 and/or 1120 provide additional area for solder to
attach the enlarged leads 1110 and/or the marker lead 1108 to a
PCB. This can strengthen the solder connections near the corners of
the semiconductor package 1100, where stress can be greatest due to
differential thermal expansion between the package body 108 and the
leads 1108 and 1110. This may reduce the likelihood of cracking of
these solder connections, and thus increase the reliability of
surface mounting.
[0081] In one embodiment, the lower surface 1118 of the marker lead
1108 may have a substantially circular shape, while the lower
surfaces 1120 of each of the enlarged leads 1110 may have a
substantially square shape. Alternatively, the lower surface 1118
of the marker lead 1108 may have a substantially square shape,
while the lower surfaces 1120 of each of the enlarged leads 1110
may have a substantially circular shape. In this context, the term
"substantially" is used to indicate that the lower surfaces 1118
and 1120 need not be perfectly square or circular. For example, the
lower surfaces 1120 of each of the enlarged leads 1110 may be
mostly square but may have a rounded corner rather than a sharp
corner. The lower surfaces 1118 and 1120 may also include surface
non-uniformities or roughness in the form of small peaks, such as
asperities, that may point outwards from the center of the leads
1108 and 1110, respectively.
[0082] It will be understood that the portion of the metal carrier
plate 1000 shown in FIG. 10 may be alternatively described. For
example, the metal carrier plate 1000 may include a base 1002 with
a protrusion 1004 disposed adjacent to the base 1002. The
protrusion 1004 may also be described as a central protrusion 1004.
A plurality of peripheral protrusions 1006, a marker protrusion
1008, and enlarged protrusions 1010 may be disposed around the base
1002.
[0083] FIG. 12 illustrates a top view of a portion of a metal
carrier plate 1200 including a die receiving area 1202 including a
peripheral edge region 1204, in accordance with one embodiment of
the present invention. Certain aspects of the metal carrier plate
1200 may be implemented similarly to embodiments previously
described herein, such as in FIGS. 4 and 10. Certain aspects of the
metal carrier plate 1200 may also be formed as previously described
herein, such as in FIG. 5. In this embodiment, the peripheral edge
region 1204 is segmented so that the peripheral edge region 1204
extends partially around an interior portion of the die receiving
area 1202. The peripheral edge region 1204 may include one or more
segmented peripheral edge regions, illustrated as segmented
peripheral edge regions 1204A-1204E.
[0084] The hatched portions of the top view of the metal carrier
plate 1200 (the segmented peripheral edge regions 1204A-1204E, the
peripheral bulges 1206, the marker bulge 1208, and the enlarged
peripheral bulges 1210) have not been etched, and therefore
protrude from the other portions of the metal carrier plate 1200
(including part of the die receiving area 1202), which have been
etched from the top side, as previously described in FIG. 5. In
this embodiment, the top side etching includes etching that removes
portions of the metal carrier plate 1200 to separate upper portions
of the segmented peripheral edge regions 1204A-1204E.
[0085] FIG. 13 illustrates a bottom view of the portion of the
metal carrier plate 1200 of FIG. 12, in accordance with one
embodiment of the present invention. The hatched portions of the
bottom view of the metal carrier plate 1200 show areas of the lower
surface of the metal carrier plate 1200 that are covered by the
metal coating 516, as previously described in FIG. 5. The metal
coating 516 protects the die receiving area 1202, the segmented
peripheral edge regions 1204A-1204E, the peripheral bulges 1206,
the marker bulge 1208, and the enlarged peripheral bulges 1210 from
bottom side etching, as previously described in FIG. 6.
[0086] FIG. 14 illustrates processing operations for making a
semiconductor package 1400 including a ground region 1470, in
accordance with one embodiment of the present invention. Certain
aspects of the semiconductor package 1400 may be made similarly to
embodiments previously described herein, such as in FIGS. 5 and 6.
Certain aspects of the semiconductor package 1400 may also be
implemented similarly to embodiments previously described herein,
such as in FIGS. 1-3 and 11. A chip 102 is attached to a die
receiving area 1402 of portions 1475a and 1475b of a metal carrier
plate 1499. The chip 102 is then electrically coupled to peripheral
bulges 1406 and a segmented peripheral edge region 1404. The metal
coating 1416 covers areas corresponding to those covered by the
metal coating 516 in FIG. 13, including portions of the lower
surface of the die receiving area 1402. These covered portions of
the lower surface of the die receiving area 1402 include the lower
surface of the segmented peripheral edge region 1404. However, the
metal coating 1416 does not cover unprotected areas 1420 of the
lower surface of the metal carrier plate 1499. The unprotected
areas 1420 include areas of the metal carrier plate 1499 that
connect lower portions of the segmented peripheral edge region 1404
to other segmented peripheral edge regions.
[0087] The unprotected areas 1420 are then etched to separate the
die receiving area 1402 (including the segmented peripheral edge
region 1404) and the peripheral bulges 1406 to form the die pad
1401 and the previously described leads 171. This etching operation
may be referred to as bottom side etching, as previously described.
Certain aspects of the die pad 1401 may be implemented similarly to
embodiments previously described herein, such as die pad 101 in
FIGS. 1-3. The die pad 1401 may include the previously described
base 202 and protrusion 213, where the protrusion 213 may be
disposed adjacent to the base 202. The protrusion 213 may include
the ground region 1470, to which the chip 102 is electrically
coupled using bonding wires 104. The ground region 1470 may include
one or more ground segments that partially surround the base 202.
For example, a ground segment 1470A may be adjacent to a first side
of the base 202, and another ground segment (not shown) may be
adjacent to a second side of the base 202.
[0088] In one embodiment, an upper surface 1471 of the ground
segment 1470A is included in the upper surface 151 of the
protrusion 213. In one embodiment, substantially the entire upper
surface 1471 is a metallic conductor and corresponds to a ground
connection area for the bonding wires 104 electrically coupled to
the chip 102.
[0089] Spacing 1496 refers to the distance between the centers of
ground region 1470 and adjacent lead 171. For certain
implementations, the spacing 1496 is between about 0.35 millimeters
and about 0.55 millimeters, although the spacing 1496 is not
constrained to this range. The spacing 1496 can be controlled by
etching, such as through a top side etching process, as previously
described in FIG. 5.
[0090] In one embodiment, a lower surface 1472 of the ground
segment 1470A corresponds to the lower surface 253 of the
protrusion 213, as the entire lower surface 253 is electrically
coupled to ground. A surface area of the lower surface 1472 may be
at least three times larger than an average of surface areas of
lower surfaces 157 of leads 171, such as at least 3 times, 5 times,
10 times, or 20 times larger.
[0091] In one embodiment, a surface area of the upper surface 151
of the protrusion 213 may be at least three times larger than an
average of surface areas of lower surfaces 157 of leads 171, such
as at least 3 times, 5 times, 10 times, or 20 times larger.
[0092] The leads 171 and the die pad 101 may be formed in each of
multiple connected packages sharing package body 108, such as
connected packages 1480a and 1480b. Through singulation, the
connected packages 1480a and 1480b may be separated into packages
1400a and 1400b, as previously described in FIG. 6. It will be
understood that multiple chips 102 may be stacked within the
semiconductor package 1400 as previously described in FIG. 7.
[0093] One advantage of ground segments over a ground ring that
extends completely around a chip is that ground segments, which
extend partially around the chip, take up less space in a package
than the ground ring. It may then be possible, for example, to
reduce the size of the package and/or to utilize the space saved to
increase the number of leads in the package.
[0094] FIG. 15 illustrates a top view of a portion of a metal
carrier plate 1500 including enlarged peripheral bulges 1505 and a
die receiving area 1502 including a peripheral edge region 1504, in
accordance with one embodiment of the present invention. Certain
aspects of the metal carrier plate 1500 may be implemented
similarly to embodiments previously described herein, such as in
FIGS. 4, 10, and 12. Certain aspects of the metal carrier plate
1500 may also be formed as previously described herein, such as in
FIG. 5. In this embodiment, the peripheral edge region 1504 extends
completely around an interior portion of the die receiving area
1502.
[0095] The hatched portions of the top view of the metal carrier
plate 1500 (the peripheral edge region 1504, the enlarged
peripheral bulges 1505, the peripheral bulges 1506, the marker
bulge 1508, and the enlarged peripheral bulges 1510) have not been
etched, and therefore protrude from the other portions of the metal
carrier plate 1500 (including part of the die receiving area 1502),
which have been etched from the top side, as previously described
in FIG. 5.
[0096] FIG. 16 illustrates a bottom view of the portion of the
metal carrier plate 1500 of FIG. 15, in accordance with one
embodiment of the present invention. The hatched portions of the
bottom view of the metal carrier plate 1500 show areas of the lower
surface of the metal carrier plate 1500 that are covered by the
metal coating 516, as previously described in FIG. 5. The metal
coating 516 protects the die receiving area 1502, the peripheral
edge region 1504, the enlarged peripheral bulges 1505, the
peripheral bulges 1506, the marker bulge 1508, and the enlarged
peripheral bulges 1510 from bottom side etching, as previously
described in FIG. 6.
[0097] FIG. 17 illustrates processing operations for making a
semiconductor package 1700 including a ground region 1770 and a
power region 1790, in accordance with one embodiment of the present
invention. Certain aspects of the semiconductor package 1700 may be
made similarly to embodiments previously described herein, such as
in FIGS. 5, 6, and 14. Certain aspects of the semiconductor package
1700 may also be implemented similarly to embodiments previously
described herein, such as in FIGS. 1-3, 11, and 14. A chip 102 is
attached to a die receiving area 1702 of portions 1775a and 1775b
of a metal carrier plate 1799. The chip 102 is then electrically
coupled to enlarged peripheral bulge 1705, peripheral bulges 1706,
and peripheral edge region 1704. The metal coating 1716 covers
areas corresponding to those covered by the metal coating 516 in
FIG. 16, and does not cover unprotected areas 1720.
[0098] The unprotected areas 1720 are then etched to separate the
die receiving area 1702 (including the peripheral edge region
1704), the enlarged peripheral bulge 1705, and the peripheral
bulges 1706 to form die pad 1701, the power region 1790, and the
previously described leads 171. This etching operation may be
referred to as bottom side etching, as previously described.
Certain aspects of the die pad 1701 may be implemented similarly to
embodiments previously described herein, such as die pad 101 in
FIGS. 1-3. The die pad 1701 may include the previously described
base 202 and protrusion 213, where the protrusion 213 may be
disposed adjacent to the base 202. The protrusion 213 may include a
ground region 1770, to which the chip 102 is electrically coupled
using bonding wires 104.
[0099] In one embodiment, the ground region 1770 completely
surrounds the base 202. The power region 1790 may include one or
more power segments that partially surround the base 202 and the
ground region 1770. For example, a power segment 1790A may be
adjacent to a first side of the ground region 1770, and another
power segment (not shown) may be adjacent to a second side of the
ground region 1770. Spacing 1794 refers to the distance between the
centers of ground region 1770 and the power region 1790, if
adjacent to the ground region 1770. Spacing 1796 refers to the
distance between the centers of ground region 1770 and adjacent
lead 171. For certain implementations, each of the spacings 1794
and 1796 is between about 0.35 millimeters and about 0.55
millimeters, although the spacings 1794 and 1796 are not
constrained to this range. The spacings 1794 and 1796 may be
substantially equal. In this context, the term "substantially"
indicates, in part, that the spacings 1794 and 1796 are equal
within a tolerance of a process used to control the spacings 1794
and 1796. The spacings 1794 and 1796 can be controlled by etching,
such as through a top side etching process, as previously described
in FIG. 5.
[0100] In one embodiment, substantially the entire upper surface
1771 of the ground region 1770 is a metallic conductor and
corresponds to a ground connection area for the bonding wires 104
electrically coupled to the chip 102. The ground connection area
may correspond to a ground ring. Similarly, in one embodiment,
substantially the entire upper surface 1791 of the power region
1790 is a metallic conductor and corresponds to a power connection
area for the bonding wires 104 electrically coupled to the chip
102. In one embodiment, a surface area of the lower surface 1792 of
the power region 1790 may be at least three times larger than an
average of surface areas of lower surfaces 157 of leads 171, such
as at least 3 times, 5 times, 10 times, or 20 times larger.
[0101] In one embodiment, the ground region 1770 and the power
region 1790 may be electrically isolated from each other.
Alternatively, the ground region 1770 and the power region 1790 may
be electrically coupled by a surface mountable device 1798. The
surface mountable device 1798 may be a decoupling capacitor used to
suppress power supply noise. The surface mountable device 1798 may
be connected to the ground region 1770 and the power region 1790
prior to the forming of the package body 108 over the metal carrier
plate 1799, as previously described in FIG. 6.
[0102] The leads 171 and the die pad 1701 may be formed in each of
multiple connected packages sharing package body 108, such as
connected packages 1780a and 1780b. Through singulation, the
connected packages 1780a and 1780b may be separated into packages
1700a and 1700b, as previously described in FIG. 6. It will be
understood that multiple chips 102 may be stacked within the
semiconductor package 1700 as previously described in FIG. 7.
[0103] One advantage of using a power segment for multiple power
connections is that a power segment can enable the same number of
power connections as multiple adjacent leads while taking up less
space in the package. If multiple leads 171 are used for power
connections instead of a power segment, a lead spacing 145
(previously described in FIGS. 1-3) between the multiple leads 171
is unusable for additional leads 171. In addition, one advantage of
power segments over a power ring that extends completely around a
chip is that power segments, which only extend partially around the
chip, take up less space in a package than the power ring. It may
then be possible, for example, to reduce the size of the package
and/or to utilize the space saved to increase the number of leads
in the package.
[0104] FIG. 18 illustrates a top view of a portion of a metal
carrier plate 1800 including parts of a die receiving area 1802
including multiple parts 1802A-1802C, in accordance with one
embodiment of the present invention. Certain aspects of the metal
carrier plate 1800 may be implemented similarly to embodiments
previously described herein, such as in FIGS. 4, 10, 12, and 15.
Certain aspects of the metal carrier plate 1800 may also be formed
as previously described herein, such as in FIG. 5. The dotted lines
1820, 1821, and 1822 show the boundaries of the multiple parts
1802A-1802C of the die receiving area 1802. The multiple parts
1802A-1802C are separated by bottom side etching, as previously
described in FIG. 6. In this embodiment, the peripheral edge region
1804 is segmented so that the peripheral edge region 1804 extends
partially around an interior portion of the die receiving area
1802. The peripheral edge region 1804 may include one or more
segmented peripheral edge regions, illustrated in this embodiment
as segmented peripheral edge regions 1804A-1804C.
[0105] The hatched portions of the top view of the metal carrier
plate 1800 (the peripheral edge region 1804, the peripheral bulges
1806, the marker bulge 1808, and the enlarged peripheral bulges
1810) have not been etched, and therefore protrude from the other
portions of the metal carrier plate 1800 (including part of the die
receiving area 1802), which have been etched from the top side, as
previously described in FIG. 5.
[0106] Alternatively, the peripheral edge region 1804 of the die
receiving area 1802 may be substantially coplanar with the die
receiving area 1802. In this context, the term "substantially"
indicates, in part, that the peripheral edge region 1804 is
coplanar with the die receiving area within a tolerance of a
process used to create the die receiving area 1802 and the
peripheral edge region 1804. The degree to which the die receiving
area 1802 and the peripheral edge region 1804 are coplanar can be
controlled by etching, such as through a top side etching process,
as previously described in FIG. 5.
[0107] FIG. 19 illustrates a bottom view of the portion of the
metal carrier plate 1800 of FIG. 18, in accordance with one
embodiment of the present invention. The hatched portions of the
bottom view of the metal carrier plate 1800 show areas of the lower
surface of the metal carrier plate 1800 that are covered by the
metal coating 516, as previously described in FIG. 5. The metal
coating 516 protects the die receiving area 1802, the peripheral
edge region 1804, the peripheral bulges 1806, the marker bulge
1808, and the enlarged peripheral bulges 1810 from bottom side
etching, as previously described in FIG. 6.
[0108] FIG. 20 illustrates processing operations for making a
semiconductor package 2000 including a die pad 2001 with separated
parts 2001A and 2001B, in accordance with one embodiment of the
present invention. Certain aspects of the semiconductor package
2000 may be made similarly to embodiments previously described
herein, such as in FIGS. 5, 6, 14, and 17. Certain aspects of the
semiconductor package 2000 may also be implemented similarly to
embodiments previously described herein, such as in FIGS. 1-3, 11,
14, and 17. A chip 102 is attached to a die receiving area 2002 of
portions 2075a and 2075b of a metal carrier plate 2099. The die
receiving area 2002 has first parts 2002A and second part 2002B
that have boundaries as previously described in FIG. 18. The first
part 2002A may include a segmented peripheral edge region 2004A,
and the second part 2002B may include a segmented peripheral edge
region 2004B. The chip 102 is then electrically coupled to the
segmented peripheral edge region 2004A, the segmented peripheral
edge region 2004B, and peripheral bulges 2006. The metal coating
2016 covers areas corresponding to those covered by the metal
coating 516 in FIG. 19, including portions of the lower surface of
the die receiving area 2002. These covered portions of the lower
surface of the die receiving area 2002 include the lower surfaces
of the segmented peripheral edge regions 2004A and 2004B. However,
the metal coating 2016 does not cover unprotected areas 2020 of the
lower surface of the metal carrier plate 2099. The unprotected
areas 2020 include areas of the metal carrier plate 2099 that
connect the first part 2002A of the die receiving area 2002 to the
second part 2002B.
[0109] The unprotected areas 2020 are then etched to separate the
first part 2002A, the second part 20023, and the peripheral bulges
2006 to form the first part 2001A of the die pad 2001, the second
part 2001B of the die pad 2001, and the previously described leads
171. This etching operation may be referred to as bottom side
etching, as previously described. In one embodiment, the lower
surfaces of each of the first part 2001A and the second part 2001B
have substantially polygonal shapes. A polygonal shape may include
at least three vertices. Polygonal shapes include but are not
limited to triangles, squares, and rectangles. The first part 2001A
and the second part 2001B may have different shapes. In this
context, the term "substantially" is used to indicate that the
lower surfaces of each of the first part 2001A and the second part
2001B need not be perfectly polygonal. For example, the lower
surfaces of each of the first part 2001A and the second part 2001B
may include surface non-uniformities or roughness in the form of
small peaks, such as asperities, that may point outwards from the
center of the first part 2001A and the second part 2001B,
respectively.
[0110] Certain aspects of the die pad 2001 may be implemented
similarly to embodiments previously described herein, such as die
pad 101 in FIGS. 1-3. Each part of the die pad 2001 may include the
previously described base 202 and protrusion 213, where the
protrusion 213 may be disposed adjacent to the base 202. In one
embodiment, the protrusion 213A of the first part 2001A may include
a ground region 2070, to which the chip 102 is electrically coupled
using bonding wires 104. The ground region 2070 extends partially
around the base 202A. The protrusion 213B of the second part 2001B
may include a power region 2090, to which the chip 102 is
electrically coupled using bonding wires 104. The power region 2090
extends partially around the base 202B.
[0111] Distance 2095 refers to the distance separating the first
part 2001A from the second part 2001B. For certain implementations,
the distance 2095 is between about 0.1 and about 0.3 millimeters,
although the distance 2095 is not constrained to this range. The
distance 2095 can be controlled by etching, such as through a top
side etching process, as previously described in FIG. 5.
[0112] In one embodiment, a surface area of a lower surface 2072 of
the ground region 2070 may be at least three times larger than an
average of surface areas of the lower surfaces 157 of leads 171,
such as at least 3 times, 5 times, 10 times, or 20 times larger.
Similarly, a surface area of the lower surface 2092 of the power
region 2090 may be at least three times larger than an average of
surface areas of the lower surfaces 157 of leads 171, such as at
least 3 times, 5 times, 10 times, or 20 times larger.
[0113] In one embodiment, a surface area of a lower surface 2011 of
the first part 2001A may be at least three times larger than an
average of surface areas of the lower surfaces 157 of leads 171,
such as at least 3 times, 5 times, 10 times, or 20 times larger.
Similarly, a surface area of a lower surface 2012 of the second
part 2001B may be at least three times larger than an average of
surface areas of the lower surfaces 157 of leads 171, such as at
least 3 times, 5 times, 10 times, or 20 times larger.
[0114] In one embodiment, the ground region 2070 and the power
region 2090 may be electrically isolated from each other.
Alternatively, the ground region 2070 and the power region 2090 may
be electrically coupled by a surface mountable device 2098, as
previously described in FIG. 17.
[0115] The leads 171 and the die pad 2001 may be formed in each of
multiple connected packages sharing package body 108, such as
connected packages 2080a and 2080b. Through singulation, the
connected packages 2080a and 2080b may be separated into packages
2000a and 2000b, as previously described in FIG. 6. It will be
understood that multiple chips 102 may be stacked within the
semiconductor package 2000 as previously described in FIG. 7.
[0116] One advantage of separating a die pad into at least a first
part that serves as a ground region and a second part that serves
as a power region is that both ground and power connections are
made available to a chip in approximately the same amount of space
needed for a around ring. It may then be possible, for example, to
reduce the size of the package and/or to utilize the space saved to
increase the number of leads in the package. In addition, the die
pad can be separated into multiple parts that serve as ground
regions and/or multiple parts that serve as power regions to
enhance electrical performance for certain package designs.
[0117] It will be understood that the metal carrier plates shown in
FIGS. 12-20 may be alternatively described. For example, the metal
carrier plate 1200 of FIG. 12 may include a base 1202 with a
protrusion 1204 disposed adjacent to the base 1202. The protrusion
1204 may also be described as a central protrusion 1204. A
plurality of peripheral protrusions 1206, a marker protrusion 1208,
and enlarged protrusions 1210 may be disposed around the base
1202.
[0118] While the methods disclosed herein have been described with
reference to particular operations performed in a particular order,
it will be understood that these operations may be combined,
sub-divided, or re-ordered to form an equivalent method without
departing from the teachings of the invention. Accordingly, unless
specifically indicated herein, the order and grouping of the
operations are not limitations of the invention.
[0119] The foregoing description, for purposes of explanation, used
specific nomenclature to provide a thorough understanding of the
invention. However, it will be apparent to one skilled in the art
that specific details are not required in order to practice the
invention. Thus, the foregoing descriptions of specific embodiments
of the invention are presented for purposes of illustration and
description. They are not intended to be exhaustive or to limit the
invention to the precise forms disclosed; many modifications and
variations are possible in view of the above teachings. The
embodiments were chosen and described in order to best explain the
principles of the invention and its practical applications, they
thereby enable others skilled in the art to best utilize the
invention and various embodiments with various modifications as are
suited to the particular use contemplated. It is intended that the
following claims and their equivalents define the scope of the
invention.
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