U.S. patent application number 12/430107 was filed with the patent office on 2009-08-20 for method of trimming a hard mask layer, method for fabricating a gate in a mos transistor, and a stack for fabricating a gate in a mos transistor.
Invention is credited to Yi-Hsing Chen, Jiunn-Hsiung Liao, Meng-Jun Wang, Min-Chieh Yang.
Application Number | 20090206403 12/430107 |
Document ID | / |
Family ID | 39593517 |
Filed Date | 2009-08-20 |
United States Patent
Application |
20090206403 |
Kind Code |
A1 |
Wang; Meng-Jun ; et
al. |
August 20, 2009 |
METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE
IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS
TRANSISTOR
Abstract
A stack structure for forming a gate of a MOS transistor
includes a substrate including a plurality of shallow trench
isolations therein; a dielectric layer, a conductive layer and a
hard mask layer formed on the substrate in sequence; and a
tri-layer stack comprising a top photo resist layer, a
silicon-containing photo resist layer and a bottom anti-reflective
coating (BARC) on the hard mask layer, wherein the
silicon-containing photo resist layer comprises 10-30% silicon and
the hard mask layer has a high etching selectivity ratio to the
conductive layer.
Inventors: |
Wang; Meng-Jun; (Taichung
County, TW) ; Chen; Yi-Hsing; (Changhua County,
TW) ; Yang; Min-Chieh; (Kao-Hsiung City, TW) ;
Liao; Jiunn-Hsiung; (Tainan Hsien, TW) |
Correspondence
Address: |
NORTH AMERICA INTELLECTUAL PROPERTY CORPORATION
P.O. BOX 506
MERRIFIELD
VA
22116
US
|
Family ID: |
39593517 |
Appl. No.: |
12/430107 |
Filed: |
April 27, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11620028 |
Jan 4, 2007 |
|
|
|
12430107 |
|
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Current U.S.
Class: |
257/347 ;
257/E29.02 |
Current CPC
Class: |
H01L 21/0332 20130101;
H01L 21/28123 20130101; Y10S 438/95 20130101; H01L 21/32139
20130101; Y10S 438/947 20130101; H01L 29/6659 20130101; H01L
21/31116 20130101; H01L 21/7624 20130101; H01L 21/0271 20130101;
H01L 21/31138 20130101; H01L 29/7833 20130101; H01L 21/0338
20130101 |
Class at
Publication: |
257/347 ;
257/E29.02 |
International
Class: |
H01L 29/06 20060101
H01L029/06 |
Claims
1. A stack structure for forming a gate of a MOS transistor,
comprising: a substrate comprising a plurality of shallow trench
isolations therein; a dielectric layer, a conductive layer and a
hard mask layer formed on said substrate in sequence; a multi-layer
stack comprising a top photo resist layer, a silicon-containing
photo resist layer and a bottom anti-reflective coating (BARC) on
said hard mask layer, wherein said silicon-containing photo resist
layer comprises 10-30% silicon and said hard mask layer has a high
etching selectivity ratio to said conductive layer.
2. The stack structure of claim 1 wherein said substrate comprises
single crystal Si and silicon on insulator (SOI).
3. The stack structure of claim 1 wherein said bottom
anti-reflective coating comprises a 365 nm photo resist layer.
4. The stack structure of claim 1 wherein said hard mask layer is
an oxide layer.
5. The stack structure of claim 4 wherein said hard mask layer
comprises SiON, SixNy, SiO.sub.2, TEOS or a combination thereof.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This patent application is a continuation application of and
claims priority to U.S. patent application Ser. No. 11/620,028,
filed on Jan. 4, 2007, and entitled "METHOD OF TRIMMING A HARD MASK
LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A
STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR" the entire
contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a method for trimming a
hard mask layer. More particularly, the present invention relates
to a stack structure for forming a gate of a MOS transistor.
[0004] 2. Description of the Prior Art
[0005] With the advancing technology of the semiconductor industry,
integrated circuits are being developed to increase the current
computing and storage capability. As predicted by Moore's law, the
number of transistors doubles every 18 months. The process of
semiconductor evolves from 0.18 .mu.m of 1999, 0.13 .mu.m of 2001,
90 nm (0.09 .mu.m) of 2003 to 65 nm (0.065 .mu.m) of 2005 and is
approaching 45 nm.
[0006] During the process of manufacturing metal oxide
semiconductor transistors (MOS transistors), the formation of a
conductive gate plays an important role. In order to meet the
demand of miniaturization of the semiconductor industry, the
current channel length under the gate must meet the standard of 45
nm. To meet the 45 nm channel length requirement, it is crucial to
control the critical dimension (CD) during the process of exposure
of the gate so as to control the line width of the conductive layer
(poly-Si layer for example) after the etching process. Because the
current lithographic tool techniques are incapable of obtaining the
ideal CD, trimming methods are employed in some prior art methods
to reduce the size of gate line width. However, most photo resist
layers useful in the current gate exposure process are 193 nm photo
resist layers which are intrinsically less resistant to the etching
condition than 365 nm photo resist layers are on account of acrylic
and cycloalkenyl polymer composition in contrast to 365 nm photo
resist layers composed of aryl moiety. Furthermore, the thickness
of 193 nm photo resist layers reduces as the exposure wavelength
shortens. Under the dual disadvantages of poor etching resistance
and less and less thickness, it is hard for 193 nm photo resist
layers to meet the minimum requirement of 30 nm owing to the
available thickness being 10 nm or less during the trimming process
on 193 nm photo resist layers.
[0007] In order to overcome the problem, the current techniques
deals with the problems by transferring the pattern on the photo
resist layer to the hard mask beneath the photo resist layer. After
being patterned, the hard mask is ready for the trimming process to
reduce the gate line width. In addition, the hard mask must have
high etching selectivity to the conductive layer used in forming
gate layer. Accordingly, the trimmed hard mask is ready to be the
template for etching transfer process to define the line width of
gate layer.
[0008] Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3
illustrate the perspective view of the process of trimming a hard
mask of the prior art. Please refer to FIG. 1. There are several
shallow trench isolations (STI) in substrate 100. A dielectric
layer 104, a conductive layer 106 and a hard mask layer 108
composed of oxide materials are formed on the substrate 100
sequentially. Following that, a bottom anti-reflective coating
(BARC) 110 and an imaging layer 112 are formed on hard mask layer
108 sequentially by spin coating technique. Both the bottom
anti-reflective coating (BARC) 110 and imaging layer 112 together
serve as a double photo resist layer 114. The reason of using
double photo resist layer 114 in stead of single-layer is to
increase the resolution of lithography. For the current technology,
the BARC 110 is usually a 365 nm photo resist layer and the imaging
layer 112 may be a 193 nm photo resist layer. In addition, the
imaging layer 112 is formed by spin-coating which solves the
problem of uneven thickness of the imaging layer 112. Moreover, the
double photo resist layer 114 allows a thinner imaging layer 112,
and a thinner imaging layer 112 may improve the focus latitude in
lithography and effectively control CD. That is why the double
photo resist layer 114 is so popular.
[0009] Please refer to FIG. 2. The imaging layer 112 is patterned
by a photolithographic process. Then the BARC 110 is patterned by
using the patterned imaging layer 112 as an etching mask. Because
the imaging layer 112 is less resistant to etching than an
aryl-composed 365 nm photo resist layer is due to the imaging layer
112 being a 193 nm photo resist layer which is composed of acrylic
and cycloalkenyl polymers, some thickness of the imaging layer 112
is depleted when the BARC 110 is patterned. After the BARC 110 is
patterned, the patterned imaging layer 112 thereon may be
optionally removed. Later, an etching procedure is performed to
pattern the hard mask layer 108 and to form the desired pattern of
openings 200.
[0010] Please refer to FIG. 3. Now a trimming procedure is
performed. The trimming procedure is a plasma etching procedure
using CF4 and CHF3 as etching gases whose ratio (CF4/CF3) is 80/15
to widen openings 200 and to narrow the width of the hard mask
layer 108 for trimming.
[0011] However, because the BARC 110 is etched away faster than the
hard mask layer 108 is by CF4 and CHF3, the hard mask layer 108
gets twisted, and part of the hard mask layer 108 which is close to
the BARC 110 etched away more than that which is close to the
conductive layer 106. Using the flawed hard mask layer 108 as an
etching mask for etching conductive layer 106 is doomed to produce
a flawed gate structure. Moreover, the BARC 110 is prone to line
collapse during the trimming procedure and the following etching on
conductive layer, which would destroy the entire process or the
results.
[0012] Accordingly, it is important to develop a better method for
trimming hard masks to form the gate of CMOS transistors with ideal
gate length.
SUMMARY OF THE INVENTION
[0013] The present invention provides a method for trimming hard
mask layers using a tri-layer photo resist layer for improving the
trimming of hard mask layers to form the gate of MOS transistors.
The present invention solves the aforesaid problems.
[0014] One preferred embodiment of the present invention provides a
method for trimming a hard mask layer, comprising providing a
substrate and a hard mask layer on the substrate; forming a
tri-layer stack comprising a top photo resist layer, a silicon
photo resist layer and a bottom photo resist layer on the hard mask
layer; patterning the top photo resist layer; etching the silicon
photo resist layer by using the patterned top photo resist layer as
an etching mask to pattern the silicon photo resist layer to form a
first opening of a first width on the bottom thereof; removing the
top photo resist layer; etching the bottom photo resist layer by
using the patterned silicon photo resist layer as an etching mask;
etching the hard mask layer by using the patterned bottom photo
resist layer as an etching mask to form a second opening of the
first width; and performing a trimming procedure to make the second
opening with a second width larger than the first width.
[0015] Another preferred embodiment of the present invention
provides a method for forming a gate of a MOS transistor,
comprising providing a substrate with several shallow trench
isolations (STI) therein; forming a dielectric layer, a conductive
layer and a hard mask layer on the substrate sequentially; forming
a tri-layer stack comprising a top photo resist layer, a silicon
photo resist layer, and a bottom photo resist layer on the hard
mask layer; patterning the top photo resist layer; etching the
silicon photo resist layer by using the patterned top photo resist
layer as an etching mask to pattern the silicon photo resist layer
to form a first opening of a first width on the bottom thereof;
removing the top photo resist layer; etching the bottom photo
resist layer by using the patterned silicon photo resist layer as
an etching mask; etching the hard mask layer by using the patterned
bottom photo resist layer as an etching mask to form a second
opening of the first width; performing a trimming procedure to make
the second opening with a second width larger than the first width;
and etching the conductive layer by using the hard mask layer with
the second openings as an etching mask to form a gate.
[0016] Still another preferred embodiment of the present invention
provides a stack structure for forming a gate of a MOS transistor,
comprising a substrate comprising a plurality of shallow trench
isolations therein; a dielectric layer, a conductive layer and a
hard mask layer formed on the substrate in sequence; and a
tri-layer stack comprising a top photo resist layer, a
silicon-containing photo resist layer and a bottom anti-reflective
coating (BARC) on the hard mask layer, wherein the
silicon-containing photo resist layer comprises 10-30% silicon and
the hard mask layer has a high etching selectivity ratio to the
conductive layer.
[0017] Because the lithographic procedure of the present invention
is performed with a photo resist layer of a tri-layer stack, the
exposure procedure may accomplish a better CD. Besides, because the
silicon-containing photo resist layer is completely depleted during
the etching procedure on patterning the bottom anti-reflective
coating (BARC), the silicon-containing photo resist layer does not
interfere with the following procedure of patterning the hard mask
layer. Furthermore, the BARC is not apt to line collapse during the
following trimming procedure or the etching procedure on the
conductive layer to form the gate because the BARC is thinner than
that of the prior art due to the improved photo resist layer of
tri-layer stack structure of the present invention in lithography,
plus the thickness of the BARC is greatly depleted when the hard
mask layer is patterned by using the BARC as an etching mask.
Accordingly, the present invention provides a desirable method for
trimming hard mask layers to form the gate of MOS transistors with
ideal gate length.
[0018] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 to FIG. 3 illustrate the perspective view of the
process of trimming a hard mask of the prior art.
[0020] FIG. 4 to FIG. 10 illustrate the perspective view of the
process for forming the gate of MOS transistors of the present
invention.
DETAILED DESCRIPTION
[0021] Please refer to FIG. 4 to FIG. 10. FIG. 4 to FIG. 10
illustrate the perspective views of the process for forming the
gate of MOS transistors of the present invention. Please refer to
FIG. 4. First a substrate 400 is provided. The substrate 400 is
usually a single-Si, or maybe silicon on insulation (SOI), or other
applicable materials, such as strained silicon, strained
silicon-on-insulator, silicon-germanium, strained
silicon-germanium, silicon-germanium on insulator, germanium,
strained germanium, germanium on insulator (GeOI), strained
germanium on insulator, strained semiconductor, compound
semiconductor, compound semiconductor, and multi-layers
semiconductor.
[0022] The substrate 400 comprises an isolation structure
comprising several shallow trench isolations (STI) 401 composed of
dielectric materials such as SiO2 or low-k dielectric materials, or
field oxide. Later a dielectric layer 402 and a conductive layer
404 are formed on the substrate 400 sequentially. Generally
speaking, the dielectric layer 402 may be formed by oxidation,
chemical vapor deposition (CVD), or plasma enhanced chemical vapor
deposition (PECVD). The material may be oxide, oxy-nitride,
nitrogen-containing dielectric materials or a combination thereof,
and a multi-layer structure. In this embodiment, the dielectric
layer 402 is a silicon oxide layer made from thermo-oxidation on
the substrate 400. The conductive layer 404 may also be formed by
chemical vapor deposition (CVD) or plasma enhanced chemical vapor
deposition (PECVD). In this embodiment, the conductive layer 404 is
made from poly-Si.
[0023] After the conductive layer 404 is formed, a hard mask layer
406 is formed on the conductive layer 404. In this embodiment, the
hard mask layer 406 is an oxide layer. Generally speaking, the hard
mask layer 406 may also be made of any one of SiON, SixNy,
SiO.sub.2, TEOS or a combination thereof. Please notice that the
hard mask layer 406 must have high etching selectivity ratio to the
conductive layer 404 used for forming the gate.
[0024] Then a multi-layer stack structure layer such as a tri-layer
stack layer 414 is formed on the hard mask layer 406. From top to
bottom, the tri-layer stack layer 414 may comprises a 193 nm photo
resist layer 412, a silicon-containing photo resist layer 410 as
silicon photo resist layer and a bottom anti-reflective coating
(BARC) 408 as a bottom photo resist layer on the hard mask layer
406 sequentially. In this embodiment, the BARC 408 is a 365 nm
(I-line) photo resist layer. The silicon-containing photo resist
layer 410 comprises 10-30% silicon. Please notice that the
thickness of both the 193 nm photo resist layer 412 and the BARC
408 required in the tri-layer stack layer 414 is thinner. A thinner
193 nm photo resist layer 412 may improve focus latitude in
lithography, and control CD effectively. In addition, a thinner 193
nm photo resist layer 412 may avoid line collapse.
[0025] The tri-layer stack layer 414 is formed on the conductive
layer 404, then followed by a photolithographic process to pattern
the 193 nm photo resist layer 412 as shown in FIG. 4.
[0026] Please refer to FIG. 5. A dry development or etching
procedure is performed using the patterned 193 nm photo resist
layer as an etching mask. In this embodiment the silicon-containing
photo resist layer 410 is patterned by an etching procedure.
Because the silicon-containing photo resist layer 410 comprises
10-30% silicon, the patterned silicon-containing photo resist layer
410 after etching has openings 502, and the sidewalls of openings
502 are all tapered (taper 504). In other words, the width W1 of
the bottom of the openings 502 is smaller than that of the top.
Please notice that the bottom of the openings 502 doesn't expose
the BARC 408, i.e. the procedure which patterns the
silicon-containing photo resist layer 410 using the patterned 193
nm photo resist layer 412 as an etching mask does not etch through
the entire silicon-containing photo resist layer 410, which helps
to keep the structural integrity of the BARC 408. Later, the
remaining 193 nm photo resist layer 112 is removed.
[0027] Please refer to FIG. 6. The silicon-containing photo resist
layer 410 is etched using the patterned silicon-containing photo
resist layer 410 as an etching mask to expose the BARC 408. In this
etching procedure the thickness of the silicon-containing photo
resist layer 410 is entirely reduced. In this procedure the etched
width is the width W1 of the bottom of the openings 202 as a
reference. Afterwards, the BARC 408 is etched using the
etched-through silicon-containing photo resist layer 410 as an
etching mask to expose the hard mask layer 406 and to pattern the
BARC 408. In patterning the BARC 408 the etching procedure will
certainly deplete some of the remaining silicon-containing photo
resist layer 410. Generally, the silicon-containing photo resist
layer 410 would be completely depleted without any remainder. In
case the silicon-containing photo resist layer 410 is not
completely depleted, it can be removed by a further etching
procedure or a washing procedure. If the silicon-containing photo
resist layer 410 is completely depleted anyhow, no remaining
silicon-containing photo resist layer 410 would interfere with the
following etching procedure.
[0028] Please refer to FIG. 7. The hard mask layer 406 is etched by
using the patterned BARC 408 as an etching mask to pattern the hard
mask layer 406 and to form openings 702 of the width W1. Because
the hard mask layer 406 is defined by using the patterned BARC 408
as an etching mask, the thickness of the BARC 408 would more or
less be depleted.
[0029] Please refer to FIG. 8, which shows the patterned hard mask
layer 406 and the BARC 408 on the conductive layer 404. Between two
patterned hard mask layer 406 and BARC 408 stack structures are
openings 702 of the width W1. Now a trimming process, i.e. trim
down etching process, is performed. The trimming process may be a
plasma etching process. For example, CF.sub.4 and CHF.sub.3 may be
used as etching gases whose ratio (CF4/CHF3) is 50/45. In this
stage the trimming process is focused on both the patterned hard
mask layer 406 and the BARC 408 in order to accomplish a better
result of line edge shortage than if the hard mask layer 406 is
trimmed alone. After the trimming process is completed, the width
W1 of the openings 702 between two patterned hard mask layer 406
and BARC 408 stack structures widens to W2. Additionally, because
the thickness of the BARC 408 is depleted when the hard mask layer
406 is patterned, the BARC 408 is not liable to line collapse in
the trimming process.
[0030] Please refer to FIG. 9. Because the hard mask layer 406 has
a high etching selectivity ratio to the conductive layer 404, the
BARC 408 and the hard mask layer 406 after the trimming process are
used as the templates for an etching transfer step to define and to
etch the pattern of the gate 902 in the conductive layer 404.
Afterwards, the dielectric layer 402 is etched to form a gate
dielectric layer 904. Following this, the BARC 408 and the hard
mask layer 406 are removed.
[0031] Please refer to FIG. 10. Now followed by an ion
implantation, a lightly doped drain (LDD) 906 is formed in the
substrate 400 of the both sides of the gate 902 and the gate
dielectric layer 904. Later a dielectric layer (not shown) is
deposited on the substrate 400 and the gate 902, and a back-etching
process is performed to form spacers 908 surrounding the gate 902
and the gate dielectric layer 904. Then an ion implantation is
performed by using the gate 902 and the spacers 908 as a mask to
form a source/drain 910 in the substrate 400 at both sides of the
gate 902, the gate dielectric layer 904 and the spacers 908 and to
form CMOS transistors 912. If necessary, a self-aligned silicide
process may be optionally performed or a contact etch stop layer
(CESL) with a specific stress condition may be optionally formed to
manufacture a strained silicon channel CMOS transistor depending on
the product specification or functional requirements. An interlayer
dielectric layer (ILD) and the desired metal interconnect may be
formed to complete the process.
[0032] Because the lithographic procedure of the present invention
is performed with a photo resist layer of a tri-layer stack, the
exposure procedure may accomplish a better CD. Besides, because the
silicon-containing photo resist layer is completely depleted during
the etching procedure on patterning the bottom anti-reflective
coating (BARC), the silicon-containing photo resist layer does not
interfere with the following procedure of patterning the hard mask
layer. Furthermore, the BARC is not apt to line collapse during the
following trimming procedure or the etching procedure on the
conductive layer to form the gate because the BARC is thinner than
that of the prior art due to the improved photo resist layer of
tri-layer stack structure of the present invention in lithography,
plus the thickness of the BARC is greatly depleted when the hard
mask layer is patterned by using the BARC as an etching mask.
Accordingly, the present invention provides a desirable method for
trimming the hard mask layers to form the gate of MOS transistors
with ideal gate length.
[0033] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *