U.S. patent application number 12/417844 was filed with the patent office on 2009-07-30 for semiconductor package and a method for manufacturing the same.
Invention is credited to Kwon Whan HAN.
Application Number | 20090189281 12/417844 |
Document ID | / |
Family ID | 39649531 |
Filed Date | 2009-07-30 |
United States Patent
Application |
20090189281 |
Kind Code |
A1 |
HAN; Kwon Whan |
July 30, 2009 |
SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME
Abstract
A semiconductor package and a method for manufacturing the same
capable of supplying power easily without an increase in the number
of pads for power supply. The semiconductor package includes a
semiconductor chip having a plurality of pads including pads for
power supply disposed in a center portion and an internal wiring
disposed to be exposed to outside; an insulating film formed on the
semiconductor to expose the pads for power supply and the internal
wirings; and re-distribution lines formed on the insulating film to
connect between the exposed portions of the pads for power supply
and the internal wiring.
Inventors: |
HAN; Kwon Whan; (Seoul,
KR) |
Correspondence
Address: |
LADAS & PARRY LLP
224 SOUTH MICHIGAN AVENUE, SUITE 1600
CHICAGO
IL
60604
US
|
Family ID: |
39649531 |
Appl. No.: |
12/417844 |
Filed: |
April 3, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11777407 |
Jul 13, 2007 |
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12417844 |
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Current U.S.
Class: |
257/741 ;
257/E23.01 |
Current CPC
Class: |
H01L 2924/01033
20130101; H01L 2924/01006 20130101; H01L 24/06 20130101; H01L
2924/01029 20130101; H01L 2924/01078 20130101; H01L 23/3114
20130101; H01L 23/5286 20130101; H01L 2924/01075 20130101; H01L
23/525 20130101; H01L 2224/023 20130101; H01L 2924/01079 20130101;
H01L 2924/014 20130101; H01L 2924/01004 20130101; H01L 2924/01082
20130101; H01L 2924/01028 20130101; H01L 2224/04042 20130101; H01L
2924/181 20130101; H01L 2924/181 20130101; H01L 2924/00 20130101;
H01L 2224/023 20130101; H01L 2924/0001 20130101 |
Class at
Publication: |
257/741 ;
257/E23.01 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 20, 2007 |
KR |
10-2007-0060261 |
Claims
1. A semiconductor package comprising: a semiconductor chip having
a plurality of pads including pads for power supply disposed in a
center portion and an internal wiring exposed to the outside of the
semiconductor chip; an insulating film formed on the semiconductor
chip to expose the pads for power supply and the internal wirings;
and re-distribution lines formed on the insulating film to connect
the exposed portions of the pads for power supply and the exposed
internal wiring.
2. The semiconductor package according to claim 1, wherein the
number of the pads for power supply is at least two and the exposed
internal wirings is at least one.
3. The semiconductor package according to claim 2, wherein the
exposed internal wirings and the re-distribution lines of at least
one are all connected with each other.
4. The semiconductor package according to claim 1, wherein the
re-distribution line is composed of a metal film.
5. The semiconductor package according to claim 4, wherein the
metal film is formed with a film of Au or any one alloy film of
Cu/Ni/Au, Cu/Au and Ni/Au with Au formed thereon.
6. The semiconductor package according to claim 1, further
comprising a capping film formed on the insulating film to expose
one portion of the re-distribution line and to expose the pads for
power supply.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to Korean patent
application number 10-2007-00 filed on Jun. 20, 2007, which is
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a semiconductor package,
and more particularly to a semiconductor package and a method for
manufacturing the same which, can easily supply power without an
increase in the number of pads required for the power supply.
[0003] The latest semiconductor device, e.g., Dynamic Random Access
Memory (DRAM) has been manufactured to have high density and
velocity. Chips of higher velocity and performance require
operational characteristics of low voltage to reduce the amount of
power used and heat generated due to the amount of power used.
[0004] However, in order to satisfy such characteristics, a larger
number of the pads are required for power supply. The ability to
increase the number of pads within the chip is limited and it makes
total size of the chip greater, which results in increasing a
product cost.
[0005] The latest semiconductor chip of higher velocity and
performance requires a larger number of the pads for power supply,
and such pads must be formed only on specific locations that enable
wire bonding in an assembly process. However, the size of the chip
must be necessarily increased in order accommodate a larger number
of pads in the specific locations. This causes an increase in the
product cost.
[0006] Moreover, in the typical DRAM device the pads are arranged
in a center portion to be manufactured as package of a Board On
Chip (BOC) type using a substrate with a window. It is difficult to
supply sufficient power because the power is supplied to edge
portions of the chip via a metal wire connected to the pads in the
center portion.
[0007] In addition, since the semiconductor chip is manufactured
using fine processes, proposals for the size, the number and the
pitch of the pad are very limited. A pitch for a lead frame or
substrate used for packaging the semiconductor chip is very great
due to limitation of the process. Therefore, although a sufficient
number of pads is formed on the semiconductor chip to supply the
power, it is possible to connect all of the pads via the wire due
to a difference between the pitch of the pad and the pitch of the
lead frame.
[0008] Moreover, a lot of the time and cost is involved because the
whole semiconductor chip must be redesigned or additional metal
wiring must be formed via a Fab process in order to prepare
additional power or signal wiring.
SUMMARY OF THE INVENTION
[0009] Embodiments of the present invention are directed to a
semiconductor package, which can achieve low voltage
characteristics without an increase in a chip size.
[0010] Further, embodiments of the present invention are directed
to a semiconductor package capable of supplying sufficient
power.
[0011] Moreover, embodiments of the present invention provide a
semiconductor package capable of reducing production time and cost
despite securing the low voltage characteristics.
[0012] According to one embodiment of the present invention, a
semiconductor package may comprise a semiconductor package
comprises a semiconductor chip having a plurality of pads including
pads for power supply disposed in a center portion and an internal
wiring disposed to be exposed to outside; an insulating film formed
on the semiconductor to expose the pads for power supply and the
internal wirings; and re-distribution lines formed on the
insulating film to connect between the exposed portions of the pads
for power supply and the internal wiring.
[0013] The number of the pads for power supply is at least two and
the exposed internal wirings is at least one.
[0014] The internal wirings and the re-distribution lines of which
at least one is exposed respectively are all connected with each
other.
[0015] The re-distribution line is composed of a metal film, and
the metal film is formed with a layer of Au or any one alloy layer
of Cu/Ni/Au, Cu/Au and Ni/Au with Au formed thereon.
[0016] The semiconductor package further comprises a capping film
formed on the insulating film and the re-distribution lines to
expose one portion of the re-distribution line and the power supply
bonding pads.
[0017] According to another embodiment of the present invention, a
method for manufacturing a semiconductor package comprising steps
of forming an insulating film on a semiconductor chip having a
plurality of pads including pads for power supply disposed in a
center portion and an internal wiring disposed to be exposed to
outside; exposing the pads for power supply and one portion of the
internal wirings by etching the insulating film; and forming
re-distribution lines on the insulating film to connect between the
exposed pads for power supply and the exposed portion of the
internal wirings.
[0018] The number of the pads for power supply and the exposed
internal wirings connected via the re-distribution lines is at
least one each.
[0019] The re-distribution lines are formed in such a way to
connect between the exposed internal wirings and the
re-distribution lines of which the number is at least one
respectively.
[0020] The step of forming the re-distribution lines is carried out
via an electrolysis plating process.
[0021] The step of forming the re-distribution lines using the
electrolysis plating process comprises steps of forming a seed
metal film on a passivation film including the exposed pads for
power supply and the exposed portion of the internal wirings;
forming a mask pattern on the seed metal film to expose a
re-distribution line forming area selectively; plating the metal
film on the seed metal film exposed; and eliminating the mask
pattern and one portion of the seed metal film beneath the mask
pattern.
[0022] The mask pattern forms a photosensitive film pattern.
[0023] The metal film is formed with Au or any one alloy layer of
Cu/Ni/Au, Cu/Au and Ni/Au with Au formed thereon.
[0024] The method for manufacturing the semiconductor package
further comprises a step of forming a capping film formed on the
insulating film including the re-distribution lines to expose each
of one portion of the re-distribution lines and the power supply
bonding pads.
[0025] The method for manufacturing the semiconductor package
further comprises a step of back-grinding a back surface of the
semiconductor chip after forming the capping film.
[0026] The method for manufacturing the semiconductor package
performs the step of forming the insulating film through the step
of back-grinding the back surface of the semiconductor chip at
wafer level.
[0027] The method for manufacturing the semiconductor package
further comprises a step of sawing at chip level after
back-grinding the back surface of the semiconductor at wafer
level.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIG. 1 is a plan view illustrating a semiconductor package
in accordance with one embodiment of the present invention.
[0029] FIGS. 2A through 2E are cross-sectional views illustrating
the process steps of a method for manufacturing the semiconductor
package in accordance with an embodiment of the present
invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0030] According to a preferred embodiment of the present
invention, one portion of internal wirings formed on a
semiconductor chip is exposed, re-distribution lines to connect the
exposed internal wiring and pads for power supply to each other are
formed through a re-distribution line process at a wafer level, and
thereafter a known packaging process can proceed.
[0031] Since the power can be directly supplied to the internal
wiring via the re-distribution lines, it is not necessary to
increase the number of the pads for power supply. Therefore,
according to the present invention the semiconductor chip can be of
high speed and high performance and have low voltage
characteristics without an increasing the chip size caused by
increasing the number of the pads for the power supply.
[0032] Further, since the present invention allows the power to be
supplied to the internal wirings in edge portions via the
re-distribution lines, and not to the metal wire, it becomes
possible to supply sufficient power.
[0033] In addition, the power can be easily supplied because the
present invention does not require a size of an exposed portion of
the internal wiring to be limited differently from when the bonding
pad used for bonding the wire is formed.
[0034] In addition, with the present invention it is possible to
prevent an increase in production time and cost because it does not
require redesign of the whole semiconductor chip or the formation
of a separate metal wiring via a Fab process for supplying the
power.
[0035] FIG. 1 is a plan view illustrating a semiconductor package
according to an embodiment of the present invention. The
semiconductor package will be specifically described referring to
FIG. 1.
[0036] As shown in FIG. 1, the semiconductor chip 100 includes a
plurality of bonding pads 102 including pads for power supply 102a
and wirings 104. The plurality of bonding pads 102 including the
pads for power supply 102a is arranged in one row or 2 rows at a
center portion of the semiconductor chip 100. The number of the
pads for power supply 102a is at least two. The wirings 104 is
formed to be arranged in, for example, an edge portion within the
semiconductor chip 100 in chip production process, and the number
of the wirings is at least one.
[0037] The semiconductor chip 100 has a passivation film 106 formed
on a surface thereof, and the passivation film is formed to expose
the bonding pads 102 including the pads for power supply 102a
together with the internal wirings 104.
[0038] An insulating film 110 is formed on the passivation film 106
of the semiconductor chip 100 to expose the plurality of bonding
pads 102 including pads for power supply 102a and one portion of
the internal wirings 104.
[0039] Further, re-distribution lines 120 are formed on the
insulating film 110 to connect the exposed portion of the internal
wirings 104 and the pads for power supply 102a with each other. The
re-distribution lines 120 are formed through an electrolysis
plating process, and are responsible for transferring the power
applied via the pads for power supply 102a to the internal wiring
104. Such re-distribution lines 120 are formed to connect between
the internal wirings 104 and the pads for power supply 102a of
which the number is at least one respectively. The re-distribution
lines composed of a metal film, for example, a film of Au or any
one alloy film of Cu/Ni/Au, Cu/Au and Ni/Au with Au disposed
thereon.
[0040] Although not shown, a capping film is formed on the
insulating film 110 with the re-distribution lines 120 formed
thereon to protect the re-distribution lines 120. The capping film
is formed to expose the bonding pads 102 including the pad for
power supply 102a and one portion of the re-distribution lines
120.
[0041] Further, the semiconductor chip 100 as mentioned above is
attached on, for example, a substrate with circuit pattern
including electrode terminals and ball lands, the electrode
terminal of the substrate and the bonding pads 102 including the
pads for power supply 102a are bonded via the metal wire, a top
surface of the semiconductor chip 100 including the metal wire is
sealed with molding material, and solder balls are attached to the
ball lands on a bottom surface of the substrate to function as an
external connection terminal, thereby making a semiconductor
package.
[0042] The semiconductor package according to an embodiment of the
present invention can allow the power to be supplied more easily to
the semiconductor chip without an increase in the number of the
pads for power supply by connecting the pads for power supply with
the internal wiring via the re-distribution lines, thereby
manufacturing the semiconductor chip with low voltage
characteristics.
[0043] Hereinafter, a method for manufacturing the semiconductor
package according to an embodiment of the present invention
mentioned above will be described referring to FIG. 2A through
2E.
[0044] Referring to FIG. 2A, there is provided a semiconductor chip
100 which has a plurality of bonding pads including pads for power
supply 102a disposed in a center portion thereof and internal
wirings 104 disposed in internal edges, and has a passivation film
106 formed on a surface thereof so as to expose the power supply
bonding pads 102a. The internal wirings 104 are exposed by etching
the passivation film 106 on the surface of the semiconductor chip
100.
[0045] Referring to FIG. 2B, after forming an insulating film 110
on the passivation film 106 of the semiconductor chip 100, the
plurality of bonding pads including the pad for power supply 102a,
as well as the internal wirings 104 are allowed to be exposed by
etching the insulating film 110.
[0046] Referring to FIG. 2C, a seed metal film 122 is formed on the
passivation film 106 of the semiconductor chip 100 including the
exposed power supply bonding pads 102a and the internal wirings 104
to be used for an electrolysis plating. Thereafter, a mask pattern
124 is formed on the seed metal film 122 so as to expose only
re-distribution line forming areas selectively. The mask pattern
124 is preferably a photosensitive film pattern formed via a
photolisography process.
[0047] Referring to FIG. 2D, a metal film 126 is plated on exposed
portion of the seed metal film 122 via an electrolysis plating
process. The metal film 126 is formed with a single film of Au or
any one alloy film of Cu/Ni/Au, Cu/Au and Ni/Au with Au formed on
uppermost layer.
[0048] Referring to FIG. 2E, the re-distribution lines 120 are
formed to connect all of the pads for power supply 102a and the
internal wirings 104 with each other, by eliminating the mask
pattern and one portion of the seed metal 122 beneath the mask
pattern. Thereafter, the capping film (not shown) is formed to
expose the pads for power supply 102a and one portion of the
re-distribution line 120 on the insulating film 110.
[0049] Subsequently, although not shown, the thickness of the
semiconductor chip 100 is lowered by back-grinding a back surface
of the semiconductor chip 100 formed with the capping film 130.
Then, the semiconductor chip will be attached to the substrate. The
electrode terminal of the substrate and the plurality of bonding
pads 102 including the pads for power supply 102a are connected
with each other via the metal wire. And then, a top surface of the
semiconductor chip 100 including the metal wire is filled with
molding materials, and solder balls are attached on the bottom
surface of the substrate so as to function as the external
connection terminal, thereby to complete manufacturing the
semiconductor package.
[0050] All of the steps of exposing the internal wirings, the step
of forming the insulating film, and a step of back-grinding the
back surface of the semiconductor chip are performed at wafer
level. Then a step of sawing after back-grinding the back surface
of the semiconductor chip at wafer level is performed at chip
level.
[0051] Since the present invention performs subsequent packaging
processes in a state that the re-distribution line is formed to
connect between the bonding pads and the internal wirings via the
wafer-level process for the manufactured semiconductor chip, it is
possible to easily provide the semiconductor package having low
voltage characteristics.
[0052] Moreover, because the present invention can supply the power
directly to the internal wiring via the re-distribution line, it is
possible to prevent an increase in the chip size.
[0053] Moreover, the present invention can supply sufficient power
since the power can be directly supplied to the internal
wirings.
[0054] In addition, the whole semiconductor chip, does not need to
be redesigned or does a separate metal wiring need to be formed via
a Fab process for the purpose of supplying the power, thereby
preventing increase in product time and cost for the semiconductor
chip.
[0055] Although a specific embodiments of the present invention has
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
the spirit of the invention as disclosed in the accompanying
claims.
* * * * *