U.S. patent application number 12/009188 was filed with the patent office on 2009-07-23 for conductive line structure and the method of forming the same.
This patent application is currently assigned to Advanced Chip Engineering Technology Inc.. Invention is credited to Ming-Chih Chen, Dyi-Chung Hu, Yu-Shan Hu.
Application Number | 20090184425 12/009188 |
Document ID | / |
Family ID | 40875818 |
Filed Date | 2009-07-23 |
United States Patent
Application |
20090184425 |
Kind Code |
A1 |
Hu; Yu-Shan ; et
al. |
July 23, 2009 |
Conductive line structure and the method of forming the same
Abstract
The conductive line structure of a semiconductor device
including a base; at least one patterned conductive layer formed
over the base; a conductive line formed over the at least one
patterned conductive layer; a protection layer that encompasses the
top surface and sidewall of the conductive line to prevent undercut
generated by etching. The structure further comprises an underlying
layer under the conductive line. The underlying layer includes Ni,
Cu or Pt. The conductive line includes gold or copper. The at least
one patterned conductive layer includes at least Ti/Cu. The
protection layer includes electro-less plating Sn, Au, Ag or
Ni.
Inventors: |
Hu; Yu-Shan; (Yangmei
Township, TW) ; Chen; Ming-Chih; (Hsinchu City,
TW) ; Hu; Dyi-Chung; (Chutung, TW) |
Correspondence
Address: |
KUSNER & JAFFE;HIGHLAND PLACE SUITE 310
6151 WILSON MILLS ROAD
HIGHLAND HEIGHTS
OH
44143
US
|
Assignee: |
Advanced Chip Engineering
Technology Inc.
|
Family ID: |
40875818 |
Appl. No.: |
12/009188 |
Filed: |
January 17, 2008 |
Current U.S.
Class: |
257/762 ;
257/E21.575; 257/E23.017; 257/E29.146; 438/648 |
Current CPC
Class: |
H01L 23/53252 20130101;
H01L 2924/0002 20130101; H01L 23/53238 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/762 ;
438/648; 257/E23.017; 257/E29.146; 257/E21.575 |
International
Class: |
H01L 23/482 20060101
H01L023/482; H01L 21/768 20060101 H01L021/768 |
Claims
1. A conductive line structure of a semiconductor device,
comprising: a base; at least one patterned conductive layer formed
over said base; a conductive line formed over said at least one
patterned conductive layer; and a protection layer encompassing the
top surface and sidewall of said conductive line to prevent
undercut generated by etching.
2. The structure of claim 1, further comprising an underlying layer
under said conductive line.
3. The structure of claim 2, wherein said underlying layer includes
Ni, Au or Pt.
4. The structure of claim 1, wherein said conductive line includes
gold.
5. The structure of claim 1, wherein said conductive line includes
copper.
6. The structure of claim 1, wherein said at least one patterned
conductive layer includes at least Ti/Cu.
7. The structure of claim 1, wherein said protection layer includes
electro-less plating Sn.
8. The structure of claim 1, wherein said protection layer includes
electro-less plating Au.
9. The structure of claim 1, wherein said protection layer includes
electro-less plating Ag.
10. The structure of claim 1, wherein said protection layer
includes electro-less plating Ni.
11. A method of forming conductive line structure of semiconductor
device, comprising: providing a base; forming at least one
conductive layer over said base; patterning a photo-resist pattern
over said at least one conductive layer to expose a top layer of
said at least one conductive layer; etching said top layer of said
at least one conductive layer; forming an underlying layer over
said etched at least one conductive layer; forming a conductive
line over said underlying layer; stripping said photo-resist
pattern; forming a protection layer to encompass the top surface
and sidewall of said conductive line to prevent undercut generated
by etching.
12. The method of claim 11, wherein said underlying layer includes
Ni, Au or Pt.
13. The method of claim 11, wherein said conductive line includes
gold.
14. The method of claim 11, wherein said conductive line includes
copper.
15. The method of claim 11, wherein said conductive line is formed
by electroplating.
16. The method of claim 11, wherein said at least one patterned
conductive layer includes Ti/Cu/Ti.
17. The method of claim 12, wherein said at least one patterned
conductive layer is formed by sputter.
18. The method of claim 11, wherein said protection layer is formed
by electro-less plating Sn.
19. The method of claim 11, wherein said protection layer is formed
by electro-less plating Au.
20. The method of claim 11, wherein said protection layer is formed
by electro-less plating Ag.
21. The method of claim 11, wherein said protection layer is formed
by electro-less plating Ni.
Description
FIELD OF THE INVENTION
[0001] This invention relates to a structure of conductive line,
and more particularly to a conductive line with protection scheme
and the method of forming the same.
[0002] 1. Background of the Invention
[0003] 2. Description of the Prior Art
[0004] Typically in the electronic component world, integrated
circuits (ICs) are fabricated on a semiconductor substrate, known
as a chip, and most commonly are made of silicon. The silicon chip
is typically assembled into a larger package which serves to
provide effective enlargement of the distance or pitch between
input/output contacts of the silicon making it suitable for
attachment to a printed circuit board, and to protect the IC from
mechanical and environmental damage. With the trend moving to more
and more features packed into decreasing product envelopes,
utilizing ever smaller electronic components to improve upon size
and feature densification a constant and formidable challenge is
presented to manufacturers of consumer and related articles. Chip
scale packages (CSP) were developed to provide an alternative
solution to directly attached flip chips devices. These packages
(CSP) represent a new miniature type of semiconductor packaging
used to address the issues of size, weight, and performance in
electronic products, especially those for consumer products such as
mobile telephones, pagers, portable computers, video cameras, etc.
Standards have not yet been formalized for CSP, and as a result,
many variations exist, and several of which are described in "Chip
Scale Package," cited above. In general, the chip is the dominant
constituent of a CSP with the area of the package, being no more
than 20% greater than the area of the chip itself, but the package
has supporting features which make it more robust than direct
attachment of a flip chip.
[0005] A conductive film or wiring are widely used during the
manufacture of the above mentioned semiconductor chips. The wiring
is obtained after a conductive film is subjected to patterning
processes. If wiring material Cu diffuses into an interlayer
insulating film, the wiring material Cu has a harmful influence on
electric characteristics. A barrier layer is provided in order to
prevent penetration of Cu into an undesired area. A compound
obtained by doping nitride of a high-melting point metal with
silicon or boron are being examined as the material of the
diffusion preventing film. Examples thereof include Ta, TaN, TaSiN,
TiN, TiSiN, W, WN, WSiN, and WBN. On the diffusion preventing film,
a thin copper seed layer is formed by directional sputtering. The
copper seed layer receives copper plating by electroplating, which
is advantageous when the aspect ratio is high. Typically, the
barrier layer is formed of a film containing nitrogen, such as
tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride
(WN).
[0006] One of the prior art structures is described in U.S. Pat.
No. 7,102,231, in which a conventional barrier structure is
provided and the structure contains Ti, a conductive barrier film
containing TiN, and Cu wiring, which are laminated in order from a
substrate side, and an insulating barrier film containing SiN is
provided for covering the Cu wiring. In this case, patterning is
performed to the conductive film containing Ti and the conductive
barrier film containing TiN at the same time, the Cu wiring is
formed, and the insulating barrier film containing SiN is
thereafter formed. A second embodiment can be found in FIG. 11B of
the patent, wherein it discloses a structure in which a conductive
barrier film containing TiN and an insulating barrier film
containing SiN are provided and conductive films of the wiring are
laminated. In comparison with the above case, Al is provided
between the Ti and TiN. A further case is also shown in FIG. 11C of
this patent, wherein the TiN is replaced by the TaN, and the
laminate structure is constructed as Ti/TaN/Cu/SiN from the
substrate side. A wiring structure shown in FIG. 11D has a
structure in which a conductive barrier film containing WN and an
insulating barrier film containing SiNO are provided. In the case,
TiN is replaced by WN and the SiN is also changed to SiNO.
[0007] In order to improve the speed of the device operation, some
suggestions to achieve the purpose are the usage of the gold or
copper to act as the wiring material. Typically, the copper is
formed by electroplating method. One drawback of the electroplating
is observed, wherein undercut may be generated after the etching
processes, seriously, as shown in FIG. 3. A further consideration
is that the cycle time is too long and consequently, the throughput
is degraded seriously.
[0008] In view of the aforementioned drawbacks, what is required is
an improved method to overcome the undercut issue and increase the
cycle time for the wiring formation.
SUMMARY OF THE INVENTION
[0009] In view of the drawbacks of prior art, the present invention
provides a new wiring formation method and structure to solve the
undercut issue and improve cycle time.
[0010] One aspect of the present invention is to form the wiring
structure by means of chemical reaction to replace the
electroplating gold, thereby removing the electroplating process,
and the chemical Sn is formed by an immersion step, only to protect
the wiring. The dimension and line width is controllable and the
sidewall of the wiring will not be eroded by the etching
solution.
[0011] According to the above-mentioned purpose, there is thus a
need for a new wiring (conductive line) structure to promote device
reliability and enhance the performance of the device.
[0012] The conductive line structure of a semiconductor device
comprises a base; at least one patterned conductive layer formed
over the base; a conductive line formed over the at least one
patterned conductive layer; and a protection layer that encompasses
the top surface and sidewall of the conductive line to prevent the
undercut issue generated by etching.
[0013] The structure further comprises an underlying layer under
the conductive line. The underlying layer includes Ni, Au or Pt.
The conductive line includes gold or copper. The at least one
patterned conductive layer includes at least Ti/Cu. The protection
layer includes electro-less plating Sn, Au, Ag or Ni.
[0014] Another aspect of the present invention is a method of
forming a conductive line structure of a semiconductor device,
comprising the steps of: providing a base; forming at least one
conductive layer over the base; followed by patterning a
photo-resist pattern over the at least one conductive layer to
expose a top layer of the at least one conductive layer; and then
etching the top layer. Subsequently, an underlying layer is formed
over the etched at least one conductive layer, and then forming a
conductive line over the underlying layer. Thereafter, the
photo-resist pattern is stripped. Next, a protection layer is
formed to encompass the top surface and sidewall of the conductive
line to prevent the undercut issue generated by etching. The
conductive line is formed by electroplating. The at least one
patterned conductive layer is formed by sputter.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above objects, and other features and advantages of the
present invention will become more apparent after reading the
following detailed description when taken in conjunction with the
drawings, in which:
[0016] FIG. 1 is a schematic diagram of a conductive line structure
according to the prior art.
[0017] FIG. 2A-2E is the process flow according to the present
invention.
[0018] FIG. 3 is an SEM diagram showing the undercut issue of the
prior art.
[0019] FIG. 4 is an SEM diagram showing the gold wire of the prior
art.
[0020] FIG. 4A is an SEM diagram illustrating the structure,
without gold wire and undercut, of the present invention.
[0021] FIG. 5 is an SEM diagram illustrating the purpose thickness
control of the present invention.
[0022] FIG. 6 is an SEM diagram illustrating the purpose sidewall
control of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0023] The present invention discloses an under bump metallurgy
structure of a package and method of the same. It can apply to a
wafer level package. Some sample embodiments of the invention will
now be described in greater detail. Nevertheless, it should be
recognized that the present invention can be practiced in a wide
range of other embodiments besides those explicitly described, and
the scope of the present invention is expressly not limited expect
as specified in the accompanying claims.
[0024] Referring to FIG. 1, the wiring (conductive line) structure
includes at least one patterned metal layer 210, 212, 214, formed
on a base 100 (substrate or layer). An underlying layer 218 is then
formed on the multiple layers. A conductive line 219 is
subsequently formed on the underlying layer 218. A protection layer
130 encompasses the top surface and the sidewall of the conductive
line. In one embodiment, the base 100 is semiconductor substrate or
any underlying layer formed of isolation material. The material of
metal layers 210, 212, 214 comprises Ti, Cu. The underlying layer
218 includes Ni, Au, Pt. One aspect of the present invention is
that the protection layer comprise Sn, Au, Ag or Ni and is formed
by an electro-less-plating process.
[0025] One example process of forming the FIG. 1 structure is shown
in FIG. 2A. A semiconductor substrate 100 is provided. Multi-metal
layers 210, 212, 214 are subsequently formed over the substrate
100. In one embodiment, the multi-metal layers are constructed by
sandwich structure Ti/Cu/Ti 210, 212, 214. Electroplating is one of
the choices to form the multi-metal layers 210, 212, 214.
Preferably, the multi-metal layers 210, 212, 214 are formed by a
sputter technique. Subsequently, photoresist (PR) 216 is formed
over the multi-metal layers 210, 212, 214, followed by patterning
the PR 216 by a lithography process to obtain the pre-determined
pattern.
[0026] The upper Ti 214 that is exposed by the PR 216 is then
etched to expose the Cu 212, followed by to form the conductive
line 219 through Ni/Cu plating or Au/Cu plating to form the
bi-layers structure having layer 218 and 219, as shown in FIG. 2B.
The PR 216 is next stripped as shown in FIG. 2C to expose the
remaining upper Ti 214.
[0027] The protection layer 130 is then formed to encompass the top
surface and the sidewall of the conductive line including 218 and
219. Alternatively, the layer 218 could be Ni, Au, Pt. In one
embodiment, the protection layer 130 comprise Sn, Au, Ag or Ni and
is formed free of an electro-plating process. In one example, the
substrate is immersed into the chemical solution containing the
above material, such as Sn. The chemical solution will be reactive
with the Cu and thereby form the protection layer. From above, the
present invention is an e-plating free process (or electro-less
plating), as shown in FIG. 2D. Next, referring to FIG. 2E, the
Ti/Cu/Ti exposed by the wiring structure with protection layer is
stripped by wet etching by means of Cu(NH.sub.3).sub.4Cl.sub.2 or
hyposulfite of soda Na.sub.2S.sub.2O.sub.3 solution.
[0028] The present invention may control the thickness of the
copper. The thickness of the wiring is controllable by the plating.
Referring to FIG. 5, it indicates the prior thickness can be
controlled by the present invention. The sidewall erosion issue of
the prior art can be also eliminated by the protection layer.
Please refer to FIGS. 5 and 6. FIG. 4A shows the structure without
gold wire and undercut according to the present invention.
[0029] The present invention has the following advantages: high
reliability, avoiding the tin infiltration, the wiring structure is
formed by means of chemical electro-free plating to replace the
electroplating, thereby removing the electroplating process, and
the electro-free plating Sn is formed by an immersion step to
protect the wiring. The dimension and line width is controllable
and the sidewall of the wiring will not be eroded by the etching
solution.
[0030] If the protection layer is Au or Ag high conductivity, it is
suitable for a high frequency RF product. The cost reduction is due
to the employment of electro-free plating. The process is
compatible with the current facility, and no additional equipment
is needed. The process may be widely used for the semiconductor
industry and assembly to meet future demands.
[0031] As described herein, various methods and structures have
been provided which make advantageous use of an electro-less
process to create wiring of various shapes and dimensions. Various
structures that can be made through the use of these methods have
also been provided. The methods disclosed herein can be used to
create conductive lines that are found to improve some of the
characteristics. These various features, taken alone or in
combination, are found to have profound, beneficial effects on
package reliability and lifetime.
[0032] The above description of the invention is illustrative, and
is not intended to be limiting. It will thus be appreciated that
various additions, substitutions and modifications may be made to
the above described embodiments without departing from the scope of
the present invention. Accordingly, the scope of the present
invention should be construed in reference to the appended
claims.
* * * * *