U.S. patent application number 11/971524 was filed with the patent office on 2009-07-09 for semiconductor die packages having overlapping dice, system using the same, and methods of making the same.
Invention is credited to Scott Irving, Yong Liu, Qiuxiao Qian.
Application Number | 20090174047 11/971524 |
Document ID | / |
Family ID | 40843902 |
Filed Date | 2009-07-09 |
United States Patent
Application |
20090174047 |
Kind Code |
A1 |
Irving; Scott ; et
al. |
July 9, 2009 |
Semiconductor Die Packages Having Overlapping Dice, System Using
the Same, and Methods of Making the Same
Abstract
Disclosed are semiconductor die packages having overlapping
dice, systems that use such packages, and methods of making such
packages. An exemplary die package comprises a leadframe, a first
semiconductor die, and a second semiconductor die that has a
recessed portion in one of its surfaces. The first die is disposed
over a first portion of the leadframe, and the second die is
disposed over a second portion of the leadframe with its recess
portion overlying at least a portion of the first die. Another
exemplary die package comprises a leadframe with a recessed area, a
first semiconductor die disposed in the recessed area, and a second
semiconductor die overlying at least a portion of the first die.
Preferably, electrically conductive regions of both dice are
electrically coupled to a conductive region of the leadframe to
provide an interconnection between dice that has very low parasitic
capacitance and inductance.
Inventors: |
Irving; Scott; (Cape
Elizabeth, ME) ; Liu; Yong; (Scarborough, ME)
; Qian; Qiuxiao; (Suzhou, CN) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER, EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Family ID: |
40843902 |
Appl. No.: |
11/971524 |
Filed: |
January 9, 2008 |
Current U.S.
Class: |
257/676 ;
257/E21.506; 257/E23.031; 438/109 |
Current CPC
Class: |
H01L 2924/01029
20130101; H01L 23/49575 20130101; H01L 24/73 20130101; H01L 24/16
20130101; H01L 2924/00014 20130101; H01L 2924/01033 20130101; H01L
2924/30107 20130101; H01L 24/29 20130101; H01L 2924/01046 20130101;
H01L 2924/30105 20130101; H01L 2924/01006 20130101; H01L 2924/01079
20130101; H01L 2924/01082 20130101; H01L 24/81 20130101; H01L
2224/05573 20130101; H01L 23/49548 20130101; H01L 24/32 20130101;
H01L 2224/05571 20130101; H01L 2924/13091 20130101; H01L 24/13
20130101; H01L 2224/732 20130101; H01L 2224/06131 20130101; H01L
2924/19041 20130101; H01L 2924/19042 20130101; H01L 23/49562
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101 |
Class at
Publication: |
257/676 ;
438/109; 257/E23.031; 257/E21.506 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 21/60 20060101 H01L021/60 |
Claims
1. A semiconductor die package comprising: a leadframe having at
least one electrically conductive region; a first semiconductor die
having a first surface, a second surface, and at least one
electrically conductive region disposed at one of its surfaces; a
second semiconductor die having a first surface, a second surface,
a recessed portion at its second surface, and at least one
electrically conductive region disposed at one of its surfaces;
wherein at least a portion of the second surface of the first
semiconductor die and at least a portion of the recessed portion of
the second semiconductor die face each other; and wherein at least
one electrically conductive region of one of the semiconductor dice
is electrically coupled to the at least one electrically conductive
region of the leadframe.
2. The semiconductor die package of claim 1 wherein the at least
one electrically conductive region of the first semiconductor die
is disposed on the first surface of the semiconductor die, wherein
the first semiconductor die is disposed such that its at least one
electrically conductive region is electrically coupled to the at
least one electrically conductive region of the leadframe.
3. The semiconductor die package of claim 2 wherein the at least
one electrically conductive region of the second semiconductor die
is disposed on the second surface of the semiconductor die, wherein
the second semiconductor die is disposed such that its at least one
electrically conductive region is electrically coupled to a
conductive region of the leadframe.
4. The semiconductor die package of claim 1 wherein the at least
one electrically conductive region of the second semiconductor die
is disposed on the second surface of the semiconductor die, wherein
the second semiconductor die is disposed such that its at least one
electrically conductive region is electrically coupled to the at
least one electrically conductive region of the leadframe.
5. The semiconductor die package of claim 1 wherein a body of
electrically insulating material is disposed between the second
surface of the second semiconductor die and the second surface of
the first semiconductor die.
6. The semiconductor die package of claim 1 wherein the leadframe
has a recess, and wherein the first and second dice are disposed
within the recess.
7. The semiconductor die package of claim 1 wherein the first
semiconductor die has a power dissipation that is lower than that
of the second semiconductor die.
8. The semiconductor die package of claim 1 wherein the lead frame
further comprises frame bumps disposed on at least a portion that
is adjacent to the second semiconductor die.
9. A system comprising a substrate and the semiconductor die
package of claim 1 attached to the substrate.
10. The system of claim 9 further comprising a buck power
converter, wherein switching power transistors of the buck power
converter are disposed within the semiconductor die package.
11. A semiconductor die package comprising: a leadframe having a
first surface, a second surface, a recessed area disposed at the
first surface, and at least one electrically conductive region
disposed at the first surface; a first semiconductor die having a
first surface, a second surface, and at least one electrically
conductive region disposed at one of its surfaces, the first
semiconductor die being disposed in the recessed area of the
leadframe; a second semiconductor die having a first surface, a
second surface, and at least one electrically conductive region
disposed at one of its surfaces, the second semiconductor die being
disposed over at least a portion of the recessed area of the
leadframe, and over at least a portion of the first semiconductor
die; wherein at least one electrically conductive region of one of
the semiconductor dice is electrically coupled to the at least one
electrically conductive region of the leadframe.
12. The semiconductor die package of claim 11 wherein the at least
one electrically conductive region of the first semiconductor die
is disposed on the first surface of the semiconductor die, wherein
the first semiconductor die is disposed such that its at least one
electrically conductive region is electrically coupled to the at
least one electrically conductive region of the leadframe.
13. The semiconductor die package of claim 12 wherein the at least
one electrically conductive region of the second semiconductor die
is disposed on the second surface of the semiconductor die, wherein
the second semiconductor die is disposed such that its at least one
electrically conductive region is electrically coupled to a
conductive region of the leadframe.
14. The semiconductor die package of claim 11 wherein the at least
one electrically conductive region of the second semiconductor die
is disposed on the second surface of the semiconductor die, wherein
the second semiconductor die is disposed such that its at least one
electrically conductive region is electrically coupled to the at
least one electrically conductive region of the leadframe.
15. The semiconductor die package of claim 11 wherein a body of
electrically insulating material is disposed over at least a
portion of the second surface of the first semiconductor die and at
least a portion of the leadframe's recessed area.
16. The semiconductor die package of claim 11 wherein the leadframe
further comprises a second recessed area, and wherein the second
semiconductor die is disposed within the second recessed area.
17. The semiconductor die package of claim 11 wherein the first
semiconductor die has a power dissipation that is lower than that
of the second semiconductor die.
18. The semiconductor die package of claim 11 wherein the lead
frame further comprises frame bumps disposed on at least a portion
that is adjacent to the second semiconductor die.
19. A system comprising a substrate and the semiconductor die
package of claim 11 attached to the substrate.
20. The system of claim 19 further comprising a buck power
converter, wherein switching power transistors of the buck power
converter are disposed within the semiconductor die package.
21. A method of assembling a semiconductor die package, the
semiconductor die package having a leadframe, a first semiconductor
die, and a second semiconductor die, the leadframe having at least
one conductive region, the first semiconductor die having a first
surface, a second surface, and at least one electrically conductive
region disposed at one of its surfaces, the second semiconductor
die having a first surface, a second surface, a recessed portion at
its second surface, and at least one electrically conductive region
disposed at one of its surfaces, the method comprising: assembling
the leadframe, the first semiconductor die, and the second
semiconductor die together with at least a portion of the second
surface of the first semiconductor die and at least a portion of
the recessed portion of the second semiconductor die facing one
another, and with at least one electrically conductive region of
one of the semiconductor dice electrically coupled to the at least
one electrically conductive region of the leadframe.
22. The method of claim 21 wherein assembling the leadframe, first
semiconductor die, and the second semiconductor die together
comprises: disposing the first semiconductor die over a first
portion of the leadframe; disposing the second semiconductor die
over a second portion of the leadframe with at least a portion of
the second semiconductor die's recessed portion overlying at least
a portion of the first semiconductor die.
23. The method of claim 22 wherein the first portion of the
leadframe is located over the leadframe's at least one conductive
region, and wherein disposing the first semiconductor die comprises
disposing a first body of solder material on one or both of the
first portion of the leadframe and the at least one electrically
conductive region of the first semiconductor die, placing the at
least one electrically conductive region of the first semiconductor
die over the first portion of the leadframe, and reflowing the
first body solder material.
24. The method of claim 23 wherein the second portion of the
leadframe is located over the leadframe's at least one conductive
region, and wherein disposing the second semiconductor die
comprises disposing a second body solder material on one or both of
the second portion of the leadframe and the at least one
electrically conductive region of the second semiconductor die,
placing the at least one electrically conductive region of the
second semiconductor die over the second portion of the leadframe,
and reflowing the second body of solder material.
25. The method of claim 24 wherein the first and second bodies of
solder material are simultaneously reflowed.
26. The method of claim 22 wherein the second portion of the
leadframe is located over the leadframe's at least one conductive
region, wherein disposing the second semiconductor die comprises
disposing a body solder material on one or both of the second
portion of the leadframe and the at least one electrically
conductive region of the second semiconductor die, placing the at
least one electrically conductive region of the second
semiconductor die over the second portion of the leadframe, and
reflowing the body of solder material.
27. A method of assembling a semiconductor die package, the
semiconductor die package having a leadframe, a first semiconductor
die, and a second semiconductor die, the leadframe having a first
surface, a second surface, a recessed area disposed at the first
surface, and at least one conductive region, the first
semiconductor die having a first surface, a second surface, and at
least one electrically conductive region disposed at one of its
surfaces, the second semiconductor die having a first surface, a
second surface, and at least one electrically conductive region
disposed at one of its surfaces, the method comprising: assembling
the leadframe, the first semiconductor die, and the second
semiconductor die together with the first semiconductor die
disposed within the recessed area of the leadframe, with at least a
portion of the second surface of the first semiconductor die and at
least a portion of the second surface of the second semiconductor
die facing one another, and with at least one electrically
conductive region of one of the semiconductor dice electrically
coupled to the at least one electrically conductive region of the
leadframe.
28. The method of claim 27 wherein assembling the leadframe, first
semiconductor die, and the second semiconductor die together
comprises: disposing the first semiconductor die into the recessed
area of the leadframe; disposing the second semiconductor die onto
the first surface of the leadframe with at least a portion of its
second surface overlying at least a portion of the first
semiconductor die.
29. The method of claim 28 wherein the leadframe's at least one
electrically conductive region has a first portion located within
the leadframe's recessed area, and wherein disposing the first
semiconductor die comprises disposing a first body of solder
material on one or both of a portion of the first area and the at
least one electrically conductive region of the first semiconductor
die, placing the at least one electrically conductive region of the
first semiconductor die over the portion of the first area, and
reflowing the first body solder material.
30. The method of claim 29 wherein the leadframe's at least one
electrically conductive region further has a second portion located
outside of the leadframe's recessed area, and wherein disposing the
second semiconductor die comprises disposing a second body solder
material on one or both of a portion of the second area of the
leadframe and the at least one electrically conductive region of
the second semiconductor die, placing the at least one electrically
conductive region of the second semiconductor die over the portion
of the first area, and reflowing the second body of solder
material.
31. The method of claim 30 wherein the first and second bodies of
solder material are simultaneously reflowed.
32. The method of claim 28 wherein the leadframe's at least one
electrically conductive region has a first portion located outside
of the leadframe's recessed area, and wherein disposing the second
semiconductor die comprises disposing a body solder material on one
or both of the first portion of the leadframe's at least one
electrically conductive region and the at least one electrically
conductive region of the second semiconductor die, placing the at
least one electrically conductive region of the second
semiconductor die over the first portion of the leadframe's at
least one electrically conductive region, and reflowing the second
body of solder material.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] NOT APPLICABLE
BACKGROUND OF THE INVENTION
[0002] Semiconductor die packages are currently used in power
supplies for computers. Because these die packages dissipate large
amounts of heat for these applications, one semiconductor device is
generally provided in each package so as to allow for a dedicated
heat sink for each device. A recent trend in the industry has been
to use a system of distributed power supplies in computers, server
systems, and other electronic devices and the like, where several
smaller buck converters supply individual components instead of a
single power converter, such as a forward converter. In the
distributed buck-converter configuration, the input AC power can be
converted by an AC-to-DC converter to an intermediate DC voltage
that is unregulated, or lightly-regulated, typically in the range
of 5 to 50 volts, and a plurality of distributed DC-to-DC buck
converters convert the intermediate DC voltage to regulated levels
in the range of .+-.2 volts to .+-.12 volts for specific components
of the system. This configuration enables the control feedback
control loop of the AC-to-DC converter to be optimized for good
power-factor-correction (PFC) performance since it does not have to
precisely control the final output voltages to the components. The
configuration also enables the buck converters to better isolate
the current demands of the system's components from one another.
While this configuration has many advantages, it has a disadvantage
of requiring additional components and additional board space.
BRIEF SUMMARY OF THE INVENTION
[0003] As part of making their invention, the inventors have
recognized that the above-distributed two-stage power-conversion
topology suffers from a lower overall power-conversion efficiency
due, in part, to parasitic capacitances and inductances in the
interconnect wires that electrically interconnect the converter's
switching transistors. The inventors have further recognized that
the buck converters used in the above-described configuration
typically have duty-cycles substantially less than 50%, and
therefore the size of the high-side power device (i.e., the device
that charges the buck inductor from the intermediate DC voltage)
may be significantly smaller than the low-side power device (i.e.,
the device that provides the synchronous free-wheeling rectifier).
Because of the size difference and low duty cycle, the dice for the
high-side and low-side devices may be incorporated into a single
semiconductor die package. In addition, the inventors have further
discovered that the parasitic capacitances and inductances
associated with the power transistors can be substantially reduced
by disposing the dice of the devices in an overlapping relationship
in the package, and by using a lead frame to interconnect the dice.
The reduction of the parasitic capacitances and inductances reduces
the switching losses of the buck converter, and enables the use of
higher switching frequencies, which further reduces losses and
improves power-conversion efficiency. Moreover, the inventors have
further discovered that power-dissipation of the high-side device
does not pose a significant additional burden on the heat sink for
the package because of the low duty cycle, and because of the
reduction in switching losses provided by reduction of parasitic
capacitances and inductances.
[0004] Accordingly, a first general embodiment of the invention is
directed to a semiconductor die package comprising a leadframe
having at least one electrically conductive region, a first
semiconductor die having a first surface, a second surface, and at
least one electrically conductive region disposed at one of its
surfaces, and a second semiconductor die having a first surface, a
second surface, a recessed portion disposed at its second surface,
and at least one electrically conductive region disposed at one of
its surfaces. At least a portion of the second surface of the first
semiconductor die and at least a portion of the recessed portion of
the second semiconductor die face each other. Also, at least one
electrically conductive region of one of the semiconductor dice is
electrically coupled to the at least one electrically conductive
region of the leadframe. In preferred embodiments, electrically
conductive regions of both semiconductor dice are electrically
coupled to the at least one electrically conductive region of the
leadframe to provide an interconnection between dice that has very
low parasitic capacitance and parasitic inductance.
[0005] A second general embodiment of the invention is directed to
a semiconductor die package comprising a leadframe, a first
semiconductor die, and a second semiconductor die. The leadframe
has a first surface, a second surface, a recessed area disposed at
the first surface, and at least one electrically conductive region
disposed at the first surface. The first semiconductor die has a
first surface, a second surface, and at least one electrically
conductive region disposed at one of its surfaces, with the first
semiconductor die being disposed in the recessed area of the
leadframe. The second semiconductor die has a first surface, a
second surface, and at least one electrically conductive region
disposed at one of its surfaces, with the second semiconductor die
being disposed over at least a portion of the recessed area of the
leadframe, and over at least a portion of the first semiconductor
die. Also, at least one electrically conductive region of one of
the semiconductor dice is electrically coupled to the at least one
electrically conductive region of the leadframe. In preferred
embodiments, electrically conductive regions of both semiconductor
dice are electrically coupled to the at least one electrically
conductive region of the leadframe to provide an interconnection
between dice that has very low parasitic capacitance and parasitic
inductance.
[0006] Another general embodiment of the invention is directed to a
method for forming a semiconductor die package representative of
the above-described first general embodiment. The general
embodiment comprises assembling the leadframe, the first
semiconductor die, and the second semiconductor die together with
at least a portion of the second surface of the first semiconductor
die and at least a portion of the recessed portion of the second
semiconductor die facing one another, and with at least one
electrically conductive region of one of the semiconductor dice
electrically coupled to the at least one electrically conductive
region of the leadframe.
[0007] Another general embodiment of the invention is directed to a
method for forming a semiconductor die package representative of
the above-described second general embodiment. The general
embodiment comprises assembling the leadframe, the first
semiconductor die, and the second semiconductor die together with
the first semiconductor die disposed within the recessed area of
the leadframe, with at least a portion of the second surface of the
first semiconductor die and at least a portion of the second
surface of the second semiconductor die facing one another, and
with at least one electrically conductive region of one of the
semiconductor dice electrically coupled to the at least one
electrically conductive region of the leadframe.
[0008] The present invention also encompasses systems that include
packages according to the present invention, each such system
having an interconnect substrate and a semiconductor die package
according to the present invention attached to the interconnect
substrate, with electrical connections made therewith.
[0009] Accordingly, it is an objective of the present invention to
provide inexpensive semiconductor die packages for buck power
converters, other power converters, and other electronic
circuits.
[0010] Accordingly, it is another objective of the present
invention to provide compact semiconductor die packages for buck
power converters, other power converters, and other electronic
circuits.
[0011] These and other embodiments of the invention are described
in detail in the Detailed Description with reference to the
Figures. In the Figures, like numerals may reference like elements
and descriptions of some elements may not be repeated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIGS. 1 and 3 are expanded perspective views of portions of
a first exemplary semiconductor die package according to the
present invention, and
[0013] FIGS. 2 and 4 are the partially assembled perspective views
thereof, respectively.
[0014] FIG. 5 is a perspective view of the first exemplary
semiconductor die package according to the present invention as
assembled in a core form, and to which an electrically insulated
heat sink may be coupled.
[0015] FIG. 6 shows a perspective view of an exemplary
semiconductor wafer from which an exemplary die for the first
exemplary semiconductor package may be taken.
[0016] FIG. 7 is an expanded perspective view of a portion of a
second exemplary semiconductor die package according to the present
invention.
[0017] FIG. 8 is a top plan view, and FIG. 9 is a perspective view,
of a portion of the second exemplary semiconductor die package
according to the present invention.
[0018] FIG. 10 is a further expanded perspective view of a portion
of a second exemplary semiconductor die package according to the
present invention.
[0019] FIG. 11 is a perspective view of the second exemplary
semiconductor die package according to the present invention as
assembled in a core form, and to which an electrically insulated
heat sink may be coupled.
[0020] FIG. 12 is a schematic diagram of an exemplary buck-type
power converter using an exemplary semiconductor die package
according to the present invention.
[0021] FIG. 13 is a perspective view of an exemplary system using
an exemplary semiconductor die package according to the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0022] FIG. 1 shows a partial expanded perspective view of a first
exemplary semiconductor die package 10 according to the present
invention. Semiconductor die package 10 comprises a leadframe 20, a
first semiconductor die 30, and a second semiconductor die 40
(shown in FIGS. 3 and 4). Leadframe 20 has a top surface 21, a
bottom surface 22 opposite its top surface 21, a recess 23 disposed
in top surface 21 to receive semiconductor dice, and a rim 24
disposed around at least a portion of recess 23. Leadframe 20 is
partitioned into at least three conductive regions 26-28 (e.g.,
three leads). In an exemplary implementation, first semiconductor
die 30 is electrically coupled to conductive regions 26-28, and
second semiconductor die 40 is electrically coupled to second
conductive region 27 (as illustrated in FIG. 3 and described
below). A plurality of bumps 25 are disposed on rim 24 to
facilitate electrical interconnections between leadframe 20 and an
external substrate. There is at least one bump 25 for each of
conductive regions 26-28. Bumps 25 may comprise the same material
as leadframe 20, may comprise solder material alone, or may
comprise solder material coated over smaller bumps of leadframe
material. The leads, rim, recess, and bumps of leadframe 20 can be
readily manufactured by conventional leadframe manufacturing steps,
which include pattern stamping, pattern cutting, and pattern
etching. Leadframe 20 may comprise a base layer of copper (Cu) that
is coated or alloyed with the following order of metal sub-layers:
nickel (Ni), palladium (Pd), and gold (Au). Not shown is an outer
ring that initially holds leadframe 20, which includes conductive
regions 36-38, together; after the dice are assembled onto
leadframe 20, the ring may be cut away.
[0023] Referring to FIG. 1, first semiconductor die 30 comprises a
first surface 31, a second surface 32 opposite to first surface 31,
a first conductive region 36 disposed on first surface 31, a
plurality of second conductive regions 37 disposed on first surface
31, and a plurality of third conductive regions 38 disposed on
first surface 31. First semiconductor die 30 may comprise a solder
mask 39 disposed over first surface 31 except in the locations of
conductive regions 36-38. In an exemplary implementation, first
semiconductor die 30 comprises a planar power device, preferably a
power MOSFET device, having a modulation terminal (gate) at first
conductive region 36, a first conduction terminal (source) at
second conductive regions 37, and a second conduction terminal
(drain) at third conductive regions 38. A plurality of
solder-material bodies 12, such as in the form of reflowed solder
bumps, may be disposed on conductive regions 36-38; and a plurality
of solder-material bodies 14, such as in the form of solder paste,
may be disposed on conductive regions 26-28. Leadframe 20 and first
semiconductor die 30 are aligned together, with conductive regions
26-28 disposed opposite to conductive regions 36-38, respectively,
and the solder is reflowed to electrically couple these regions
together. The resulting assembly is shown in FIG. 2, with
conductive regions 26-28 being electrically coupled to conductive
regions 36-38, respectively. Leadframe 20 may comprise a solder
mask 29 disposed over top surface 21 except in the locations of
solder-material bodies 14, bumps 25, and a location 29' where
second semiconductor die 40 will be attached. If bumps 25 do not
comprise solder material, or if solder material will not disposed
on the bumps in a later step, then solder mask 29 need slot be
disposed over the top surface of rim 24. The other reference
numbers shown in the figure were previously described with respect
to FIG. 1.
[0024] FIG. 3 shows a further partial expanded perspective view of
semiconductor die package 10 as second semiconductor die 40 is
being assembled onto leadframe 20. Second semiconductor die 40 has
a first surface 41, second surface 42 opposite to first surface 41,
a recessed portion 43 disposed at second surface 42, a first
conductive region 46 disposed on first surface 41 (shown in FIG.
4), a plurality of second conductive regions 47 (shown in FIG. 4)
disposed on first surface 41, and a third conductive region 48
disposed on second surface 42 in the area that is not recessed.
Respective solder bumps 45 may be disposed on conductive regions 46
and 47. Recessed portion 43 may also be called a step portion, an
indented portion, and the like. A body 16 of solder material, such
as in the form of a layer of solder paste, is disposed on location
29' of leadframe 20. Second semiconductor die 40 is then disposed
within recess 23 of leadframe 20 such that portions of its recessed
portion 43 and the second surface 32 of die 30 face one another,
and such that its third conductive region 48 contacts
solder-material body 16. Next, solder-material body 16 is reflowed
to provide an electrical coupling between third conductive region
48 and second conductive region 27 of leadframe 20 in the area of
location 29'. The resulting structure is shown in FIG. 4, where it
can be seen that the first surface 41 of second die 40 is
substantially flush with the top of the leadframe's rim 24. While
the above embodiment has been illustrated with solder-material
bodies 12-16 being reflowed in separate steps, they can be reflowed
simultaneously in a common reflow step. In an exemplary
implementation, second semiconductor die 40 comprises a vertical
power device, preferably a power MOSFET device, having a modulation
terminal (gate) at first conductive region 46, a first conduction
terminal (source) at second conductive regions 47, and a second
conduction terminal (drain) at third conductive region 48.
[0025] Package 10 can thereby provide two semiconductor die in the
space of one, and thus provide the same functionality in a more
compact package. In addition, both die are coupled to leadframe 20,
which in turn may be coupled to an electrically insulated
heat-sink. In this regard, when die 40 is used as a synchronous
rectifier of a buck converter, the die having the need for the
greatest power dissipation (e.g., die 40) can have the greater
amount of thermal conductivity to leadframe 20 since conductive
region 48 can be made very large. In one exemplary implementation,
first semiconductor die 30 has a thickness of about 100 microns,
and second semiconductor die 40 has a thickness of about 300
microns, with its recessed portion 43 being about 200 microns deep.
In typical implementations, the second surface 32 and 42 of the
dice are not electrically coupled together, and a gap 18 is present
between them. However, for other implementations, they may be
attached and/or electrically coupled to one another. In these other
implementations, an electrical coupling of surface 32 and 42 may
provide a body potential for die 30 when die 30 comprises a planar
power device, or may provide a coupling between conduction
terminals of dice 30 and 40 when dice 30 comprises a vertical power
device.
[0026] Referring to FIG. 5, a body 50 of an electrically insulating
material is disposed within the unfilled portions of recess 23, and
optionally within gap 18, if present. The material of body 50 may
comprise an underfill material or an injectable molding material.
Body 50 provides mechanical support to dice 30 and 40 in addition
to that provided by solder material bodies 12-16. Also, as an
optional step, a plurality of solder bumps 55 may be formed on the
leadframes bumps 25, as illustrated with a set of four bumps in the
figure. Additional molding material (not shown in FIG. 5) may be
disposed around the sides of package 10. Package 10 may be mounted
to a system substrate at first surface 21 of leadframe 20, and an
electrically insulated heat sink may be coupled to second surface
22 of leadframe 20. If a heat sink is not needed for a particular
application, additional molding material (not shown in FIG. 5) may
be disposed on second surface 22.
[0027] Referring to FIG. 6, the recessed portion 43 of die 40 may
be made using a backside etching process while the die is still
part of a semiconductor wafer, which is shown at 60. Several
instances of second semiconductor die 40 may be manufactured on
wafer 60 in a plurality of rows, and before the instances are diced
from the wafer, a patterned backside etch may be performed along
edges of the rows to define the recessed portions 43 of all the
instances. For silicon devices, a so-called "hot KOH" etch may be
used, along with a suitable mask material.
[0028] FIG. 7 shows a partial expanded perspective view of a second
exemplary semiconductor die package 100 according to the present
invention. Semiconductor die package 100 comprises a leadframe 120,
a first semiconductor die 30 as previously described, and a second
semiconductor die 40' (shown in FIGS. 10 and 11). Like leadframe
20, leadframe 120 has a top surface 21, a bottom surface 22
opposite top surface 21, a recess 23 disposed in top surface 21 to
receive semiconductor dice, and a rim 24 disposed around at least a
portion of recess 23. Leadframe 120 is also partitioned into at
least three conductive regions 26-28 (e.g., three leads), and has a
plurality of bumps 25 disposed on rim 24 to facilitate electrical
interconnections between leadframe 120 and an external substrate.
There is at least one bump 25 for each of conductive regions 26-28.
Unlike leadframe 20, leadframe 120 further comprises a second
recess 123 disposed in top surface 21, and a rim 124 disposed
around at least a portion of recess 123. A major portion of recess
123 lies within the extent of recess 23, and preferably all of
recess 123 lies within the extent of recess 23. In an exemplary
implementation, first semiconductor die 30 is disposed within
second recess 123 with its conductive regions 36-38 electrically
coupled to conductive regions 26-28 with solder-material bodies
12-14, as previously described above, and second semiconductor die
40' is disposed within recess 23 and electrically coupled to second
conductive region 27 (as illustrated in FIG. 11 and described
below). FIG. 8 shows a top plan view of package 100 after leadframe
120 and first die 30 have been assembled together. The leads, rims,
recesses, and bumps of leadframe 120 can be readily manufactured by
conventional leadframe manufacturing steps, which include pattern
stamping, pattern cutting, and pattern etching. Leadframe 120 may
comprise a base layer of copper (Cu) that is coated or alloyed with
the following order of metal sub-layers: nickel (Ni), palladium
(Pd), and gold (Au). Not shown is an outer ring that initially
holds leadframe 120, which includes conductive regions 36-38,
together; after the dice are assembled onto leadframe 120, the ring
may be cut away. The other reference numbers shown in FIG. 8 have
been previously described above.
[0029] Referring to FIG. 9, after first semiconductor die 30 and
leadframe 120 are assembled, a body 150 of an electrically
insulating material may be disposed over die 30 and within the
unfilled portions of recess 123. The material of body 150 may
comprise an underfill material or an injectable molding material.
Body 150 provides mechanical support to die 30 in addition to that
provided by solder bodies 12-14, and can provide electrical
insulation between dice 30 and 40', if needed. The other reference
numbers shown in FIG. 9 have been previously described above.
[0030] FIG. 10 shows a further partial expanded perspective view of
semiconductor die package 100 as second semiconductor die 40' is
being assembled onto leadframe 120. Second semiconductor die 40'
has a first surface 41, second surface 42 opposite to first surface
41, a first conductive region 46 disposed on first surface 41, a
plurality of second conductive regions 47 disposed on first surface
41, and a third conductive region 48 (not shown) disposed on second
surface 42 in at least the same way as for die 40 shown in FIG. 3
(and the reader may refer to FIG. 3 for an implementation of third
conductive region 48). Second surface 42 may be planar, without a
recess, and third conductive region 48 may be disposed over a major
portion, or substantially all, of second surface 42. Respective
solder bumps 45 may be disposed on conductive regions 46 and 47. A
body 16 of solder material, such as in the form of a layer of
solder paste, may be disposed on location 29' of leadframe 120, and
optionally on adjacent portions electrically insulating body 150
and portions of solder mask 29 that cover conductive regions 26 and
28. Second semiconductor die 40' is then disposed within recess 23
of leadframe 120 such that its third conductive region 48 contacts
solder-material body 16. Next, solder-material body 16 is reflowed
to provide an electrical coupling between third conductive region
48 and second conductive region 27 of leadframe 120 in the area of
location 29'. The portions of body 16 initially disposed on body
150 and solder mask 29 are typically drawn by capillary action
toward area 29' during the reflow step, and small gaps may be
formed between second surface 42 of die 40' and each of
electrically insulating body 150 and conductive regions 26 and 28.
The resulting structure is shown in FIG. 11, where it can be seen
that the first surface 41 of second die 40' is substantially flush
with the top of the leadframe's rim 24. While the above embodiment
has been illustrated with solder-material bodies 12-16 being
reflowed in separate steps, they can be reflowed simultaneously in
a common reflow step. In an exemplary implementation, second
semiconductor die 40' comprises a vertical power device, preferably
a power MOSFET device, having a modulation terminal (gate) at first
conductive region 46, a first conduction terminal (source) at
second conductive regions 47, and a second conduction terminal
(drain) at third conductive region 48. The other reference numbers
shown in FIG. 11 have been previously described above.
[0031] Package 100 can thereby provide two semiconductor dice in
the space of one, and thus provide the same functionality in a more
compact package. In addition, both dice are coupled to leadframe
120, which in turn may be coupled to an electrically insulated
heat-sink. In this regard, when die 40' is used as a synchronous
rectifier of a buck converter, the die having the need for the
greatest power dissipation (e.g., die 40') can have the greater
amount of thermal conductivity to leadframe 120 since conductive
region 48 can be made very large. In one exemplary implementation,
first semiconductor die 30 has a thickness of about 100 microns,
and second semiconductor die 40 has a thickness of about 200
microns, recess 23 has a depth of about 200 microns, and recess 123
has a depth of about 200 microns, as measured from the bottom of
recess 23. In typical implementations, the second surface 32 and 42
of the dice are not electrically coupled together, and electrically
insulating body 150 is disposed between them. However, for other
implementations, they may be attached and/or electrically coupled
to one another. In these other implementations, an electrical
coupling of surface 32 and 42 may provide a body potential for die
30 when die 30 comprises a planar power device, or may provide a
coupling between conduction terminals of dice 30 and 40' when dice
30 comprises a vertical power device.
[0032] Thus, it may be appreciated that the above description
illustrates a method of assembling a semiconductor die package that
comprises assembling the leadframe, the first semiconductor die,
and the second semiconductor die together with the first
semiconductor die disposed within the recessed area of the
leadframe, with at least a portion of the second surface of the
first semiconductor die and at least a portion of the second
surface of the second semiconductor die facing one another, and
with at least one electrically conductive region of one of the
semiconductor dice electrically coupled to the at least one
electrically conductive region of the leadframe.
[0033] FIG. 12 shows an exemplary buck converter using either of
exemplary packages 10 and 100 according to the present invention.
The exemplary buck converter comprises a power input port Vin, a
power output port Vout, an instance of package 10 or 100, a buck
inductor L, a storage capacitor C, a controller, a switch node N1,
and output node N2, and a ground node N0 that is common to both
input port Vin and output port Vout. Package 10 (or 100) is coupled
to input port Vin such that the free conduction terminal 38 (e.g.,
drain) of first die 30 is coupled to the positive terminal of the
input power port via conductive region (lead) 28, and such that the
free conduction terminal 47 (e.g., source) of second die 40 (or
40') is coupled to the negative terminal of the input power port.
The switching node N1 is provided by conductive region (lead) 27 of
package 10 (or 100), which advantageously has very low parasitic
capacitance and parasitic inductance, as previously described. The
buck inductor L is coupled between nodes N1 and N2, and the storage
capacitor C is coupled between nodes N2 and N0. The transistor of
die 30 selectively couples buck inductor L to the input supply to
increase the current flow and magnetic storage in the inductor,
while the transistor of die 40 selectively couples the inductor to
ground to provide a reset voltage and freewheeling path for the
buck inductor (which prevents the inductor's magnetic core from
saturating). For this application, die 40 (or 40') preferably has a
freewheeling diode D integrated with the transistor. The controller
measures the value of the output voltage at output port Vout, and
adjusts the switching of the power transistors of dice 30 and 40 to
regulate the output voltage to a desired level. The transistors of
dice 30 and 40 are switched on and off in an alternating manner,
with one transistor being off while the other is on. A cycle of
fixed time duration is generally used, but the controller may vary
the cycle time. In either event, the relative duty cycle of the
transistor of die 30 is varied to regulate the output voltage.
[0034] FIG. 13 shows a perspective view of a system 200 that
incorporates an exemplary package, either or both of packages 10
and 100, according to the present invention. System 200 comprises
an interconnect substrate 201, a plurality of interconnect pads 202
to which components are attached, a plurality of interconnect
traces 203 (only a few of which are shown for the sake of visual
clarity), an instance of package 10 (or 100), a buck inductor L, a
storage capacitor C, and a controller. The electrical components
may be configured as described above with reference to FIG. 12, and
a plurality of solder bumps may be used to electrically couple the
electrical components to interconnect substrate 201. Pads for
Vin(+), Vin(-), Vout(+), Vout(-) may be provided, or system 200 may
have a larger interconnect substrate 201 where the input and output
voltage are brought in by traces. An electrically insulating body
90 may be formed around package 10 (100), and a heat sink 220 may
be thermally coupled to the exposed surface of the package.
[0035] The semiconductor die packages described above can be used
in electrical assemblies including circuit boards with the packages
mounted thereon. They may also be used in systems such as phones,
computers, etc.
[0036] Some of the examples described above are directed to
"leadless" type packages such as MLP-type packages (microleadframe
packages) where the terminal ends of the leads do not extend past
the lateral edges of the molding material. Embodiments of the
invention may also include leaded packages where the leads extend
past the lateral surfaces of the molding material.
[0037] Any recitation of "a", "an", and "the" is intended to mean
one or more unless specifically indicated to the contrary.
[0038] The terms and expressions which have been employed herein
are used as terms of description and not of limitation, and there
is no intention in the use of such terms and expressions of
excluding equivalents of the features shown and described, it being
recognized that various modifications are possible within the scope
of the invention claimed.
[0039] Moreover, one or more features of one or more embodiments of
the invention may be combined with one or more features of other
embodiments of the invention without departing from the scope of
the invention.
[0040] While the present invention has been particularly described
with respect to the illustrated embodiments, it will be appreciated
that various alterations, modifications, adaptations, and
equivalent arrangements may be made based on the present
disclosure, and are intended to be within the scope of the
invention and the appended claims.
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