U.S. patent application number 11/954749 was filed with the patent office on 2009-06-18 for high-k/metal gate stack using capping layer methods, ic and related transistors.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Michael P. Chudzik, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri.
Application Number | 20090152636 11/954749 |
Document ID | / |
Family ID | 40752068 |
Filed Date | 2009-06-18 |
United States Patent
Application |
20090152636 |
Kind Code |
A1 |
Chudzik; Michael P. ; et
al. |
June 18, 2009 |
HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED
TRANSISTORS
Abstract
Methods, IC and related transistors using capping layer with
high-k/metal gate stacks are disclosed. In one embodiment, the IC
includes a first type transistor having a gate electrode including
a first metal, a second metal and a first dielectric layer, the
first dielectric layer including oxygen; a second type transistor
separated from the first type transistor by an isolation region,
the second type transistor having a gate electrode including the
second metal having a work function appropriate for the second type
transistor and the first dielectric layer; and wherein the gate
electrode of the first type transistor includes a rare earth metal
between the first metal and the second metal and the gate electrode
of the second type transistor includes a second dielectric layer
made of an oxide of the rare earth metal.
Inventors: |
Chudzik; Michael P.;
(Danbury, CT) ; Moumen; Naim; (Walden, NY)
; Narayanan; Vijay; (New York, NY) ; Park;
Dae-Gyu; (Poughquaq, NY) ; Paruchuri; Vamsi K.;
(New York, NY) |
Correspondence
Address: |
HOFFMAN WARNICK LLC
75 STATE ST, 14TH FL
ALBANY
NY
12207
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
40752068 |
Appl. No.: |
11/954749 |
Filed: |
December 12, 2007 |
Current U.S.
Class: |
257/369 ;
257/411; 257/E21.632; 257/E27.062; 257/E29.255; 438/216 |
Current CPC
Class: |
H01L 21/823842 20130101;
H01L 21/823857 20130101; H01L 29/517 20130101; H01L 29/4966
20130101; H01L 29/4975 20130101 |
Class at
Publication: |
257/369 ;
438/216; 257/411; 257/E21.632; 257/E27.062; 257/E29.255 |
International
Class: |
H01L 21/336 20060101
H01L021/336; H01L 27/092 20060101 H01L027/092; H01L 29/78 20060101
H01L029/78 |
Claims
1. A method comprising: providing an implanted substrate with a
n-type metal oxide semiconductor (NMOS) region and a p-type metal
oxide semiconductor (PMOS) region; depositing a high dielectric
constant (high-k) dielectric layer over the implanted substrate;
forming a first metal having a work function commensurate with a
first one of the NMOS region and the PMOS region over the first one
of the NMOS and the PMOS regions only, leaving the high-k
dielectric layer exposed over a second one of the NMOS and PMOS
regions; depositing a second metal having a work function
commensurate with the second one of the NMOS region and the PMOS
region over the implanted substrate; depositing a polysilicon over
the implanted substrate; and patterning to form a first gate stack
over the NMOS region and a second gate stack over the PMOS region
on the implanted substrate.
2. The method of claim 1, further comprising depositing a capping
layer over the implanted substrate prior to depositing the second
metal.
3. The method of claim 2, wherein the capping layer includes a
dielectric.
4. The method of claim 3, wherein the capping layer is selected
from the group consisting of: lanthanum oxide (La.sub.2O.sub.3),
dysprosium oxide (DyO), yttrium oxide (Y.sub.2O.sub.3), barium
oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium
oxide (CeO), praseodymium oxide (PrO), neodymium (NdO), gadolinium
oxide (GdO), erbium oxide (ErO).
5. The method of claim 2, wherein the capping layer includes a
metal.
6. The method of claim 5, wherein the capping layer is selected
from the group consisting of: lanthanum (La), dysprosium (Dy),
yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium
(Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), erbium
(Er).
7. The method of claim 2, wherein the high-k dielectric layer
includes oxygen and the capping layer includes a rare earth metal
that reacts with the high-k dielectric over the first one of the
NMOS region and the PMOS region to form a dielectric, and remains
metallic over the second one of the NMOS region and the PMOS
region.
8. The method of claim 7, wherein the capping layer is selected
from the group consisting of: ytterbium (Yb), dysprosium (Dy),
lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium
(Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium
(Gd) and erbium (Er).
9. The method of claim 1, wherein the high-k dielectric layer is
selected from the group consisting of: hafnium oxide (HfO.sub.2),
aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide
(La.sub.2O.sub.3), hafnium silicon oxide (HfSiO.sub.x), hafnium
aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon
oxide (ZrSiO), yttrium oxide (Y.sub.2O.sub.3), strontium oxide
(SrO) and strontium titanium oxide (SrTiO).
10. The method of claim 1, wherein the first one of the NMOS and
PMOS region is the PMOS region, and the first metal is selected
from the group consisting of: titanium nitride (TiN), ruthenium
(Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium
carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten
(W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel
silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium
(V) and aluminum (Al).
11. The method of claim 1, wherein the second one of the NMOS and
PMOS region is the NMOS region, and the second metal is selected
from the group consisting of: titanium nitride (TiN), ruthenium
(Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium
carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten
(W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel
silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium
(V) and aluminum (Al).
12. An integrated circuit comprising: a first type transistor
having a gate electrode including a first metal, a second metal and
a first dielectric layer, the first dielectric layer including
oxygen; a second type transistor separated from the first type
transistor by an isolation region, the second type transistor
having a gate electrode including the second metal having a work
function appropriate for the second type transistor and the first
dielectric layer; and wherein the gate electrode of the first type
transistor includes a rare earth metal between the first metal and
the second metal and the gate electrode of the second type
transistor includes a second dielectric layer made of an oxide of
the rare earth metal.
13. The IC of claim 12, wherein the first dielectric layer is under
the first metal in the gate electrode in the first type
transistor.
14. The IC of claim 12, wherein the second dielectric layer
contacts the first dielectric layer in the second type
transistor.
15. The IC of claim 12, wherein the first type transistor includes
an p-type field effect transistor (PFET) and the second type
transistor includes a n-type field effect transistor (NFET).
16. The IC of claim 12, wherein each gate electrode further
includes a polysilicon portion.
17. The IC of claim 12, wherein the second metal in the first type
transistor and the second type transistor are electrically
coupled.
18. The IC of claim 12, wherein the rare earth metal is selected
from the group consisting of: ytterbium (Yb), dysprosium (Dy),
lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium
(Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium
(Gd) and erbium (Er).
19. A transistor comprising: a gate stack including: a high
dielectric constant (high-k) dielectric layer over a substrate, a
capping layer including an oxide of a rare earth metal over the
high-k dielectric layer, a metal over the oxide of the rare earth
metal, the metal having a work function commensurate with a well in
the substrate, and a polysilicon over the metal.
20. The transistor of claim 19, wherein the rare earth metal is
selected from the group consisting of: ytterbium (Yb), dysprosium
(Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc),
barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd),
gadolinium (Gd) and erbium (Er).
21. The transistor of claim 19, wherein the high-k dielectric layer
is selected from the group consisting of: hafnium oxide
(HfO.sub.2), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide
(La.sub.2O.sub.3), hafnium silicon oxide (HfSiO.sub.x), hafnium
aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon
oxide (ZrSiO), yttrium oxide (Y.sub.2O.sub.3), strontium oxide
(SrO) and strontium titanium oxide (SrTiO).
22. A transistor comprising: a gate stack including: a high
dielectric constant (high-k) dielectric layer over a substrate, the
high-k dielectric layer including oxygen, a first metal having a
work function commensurate with a well in the substrate, a capping
layer including a rare earth metal over the first metal, a second
metal over the capping layer, the second metal having a work
function incompatible with the well in the substrate, and a
polysilicon over the second metal.
23. The transistor of claim 22, wherein the rare earth metal is
selected from the group consisting of: ytterbium (Yb), dysprosium
(Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc),
barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd),
gadolinium (Gd) and erbium (Er).
24. The transistor of claim 22, wherein the high-k dielectric layer
is selected from the group consisting of: hafnium oxide
(HfO.sub.2), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide
(La.sub.2O.sub.3), hafnium silicon oxide (HfSiO.sub.x), hafnium
aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon
oxide (ZrSiO), yttrium oxide (Y.sub.2O.sub.3), strontium oxide
(SrO) and strontium titanium oxide (SrTiO).
25. The transistor of claim 22, wherein the well is a p-type well.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The disclosure relates generally to integrated circuit (IC)
fabrication, and more particularly, to forming of high dielectric
constant (high-k) and metal gate stacks using a capping layer.
[0003] 2. Background Art
[0004] In the integrated circuit (IC) fabrication industry, metal
gate electrodes are being pursued for, for example, the 45
nanometer (nm) and 32 nm technology nodes as a replacement for
doped polysilicon (poly-Si) gate electrodes for a number of
reasons. Metal gate electrodes include a high dielectric constant
(high-k) dielectric within a metal gate stack. The best known self
aligned process flows for complementary metal oxide semiconductor
(CMOS) fabrication with the high-k dielectrics and metal gate stack
use a dual field effect transistor (FET) threshold voltage (Vt)
work function tuning layers scheme to tune the threshold voltage of
adjacent n-type metal oxide semiconductor (NMOS) region (for NFETs)
and p-type metal oxide semiconductor (PMOS) region (for PFETs).
That is, dual metal/dual dielectric gate stacks. One challenge for
this technology is that the continual reduction in device
dimensions that define, for example, the 45 nm and 32 nm technology
nodes, impose an ever reducing distance between the different
active regions, e.g., approximately 102 nm for the 45 nm node and
approximately 72 nm for the 32 nm node. The reduction in device
dimensions presents a problem because tuning layers for NMOS and
PMOS regions are not interchangeable. As a result, in order to
accommodate formation of the appropriate gate stack for each
region, gate stack layers particular to each region must be formed
in both regions and then the opposing NMOS and PMOS region's stack
must be completely removed, which is costly and induces process
variations. Since the distance between active regions is so small,
etching the gate stacks and continuing to meet ground rule
restrictions is currently unachievable for the 45 nm and 32 nm CMOS
technology nodes, and beyond. In particular, the ability to form
material layers such that they are thin enough to fill a gap
between partially formed gate stacks and such that the materials
can be removed from the gap to ultimately form the gate stacks in
the NMOS and PMOS regions is currently unfeasible. Butted junctions
are also not available using current practices because of the
removal of layers between the different NMOS and PMOS gate
stacks.
SUMMARY
[0005] Methods, IC and related transistors using capping layer with
high-k/metal gate stacks are disclosed. In one embodiment, the IC
includes a first type transistor having a gate electrode including
a first metal, a second metal and a first dielectric layer, the
first dielectric layer including oxygen; a second type transistor
separated from the first type transistor by an isolation region,
the second type transistor having a gate electrode including the
second metal having a work function appropriate for the second type
transistor and the first dielectric layer; and wherein the gate
electrode of the first type transistor includes a rare earth metal
between the first metal and the second metal and the gate electrode
of the second type transistor includes a second dielectric layer
made of an oxide of the rare earth metal.
[0006] A first aspect of the disclosure provides a method
comprising: providing an implanted substrate with a n-type metal
oxide semiconductor (NMOS) region and a p-type metal oxide
semiconductor (PMOS) region; depositing a high dielectric constant
(high-k) dielectric layer over the implanted substrate; forming a
first metal having a work function commensurate with a first one of
the NMOS region and the PMOS region over the first one of the NMOS
and the PMOS regions only, leaving the high-k dielectric layer
exposed over a second one of the NMOS and PMOS regions; depositing
a second metal having a work function commensurate with the second
one of the NMOS region and the PMOS region over the implanted
substrate; depositing a polysilicon over the implanted substrate;
and patterning to form a first gate stack over the NMOS region and
a second gate stack over the PMOS region on the implanted
substrate.
[0007] A second aspect of the disclosure provides an integrated
circuit comprising: a first type transistor having a gate electrode
including a first metal, a second metal and a first dielectric
layer, the first dielectric layer including oxygen; a second type
transistor separated from the first type transistor by an isolation
region, the second type transistor having a gate electrode
including the second metal having a work function appropriate for
the second type transistor and the first dielectric layer; and
wherein the gate electrode of the first type transistor includes a
rare earth metal between the first metal and the second metal and
the gate electrode of the second type transistor includes a second
dielectric layer made of an oxide of the rare earth metal.
[0008] A third aspect of the disclosure provides a transistor
comprising: a gate stack including: a high dielectric constant
(high-k) dielectric layer over a substrate, a capping layer
including an oxide of a rare earth metal over the high-k dielectric
layer, a metal over the oxide of the rare earth metal, the metal
having a work function commensurate with a well in the substrate,
and a polysilicon over the metal.
[0009] A fourth aspect of the disclosure provides a transistor
comprising: a gate stack including: a high dielectric constant
(high-k) dielectric layer over a substrate, the high-k dielectric
layer including oxygen, a first metal having a work function
commensurate with a well in the substrate, a capping layer
including a rare earth metal over the first metal, a second metal
over the capping layer, the second metal having a work function
incompatible with the well in the substrate, and a polysilicon over
the second metal.
[0010] The illustrative aspects of the present disclosure are
designed to solve the problems herein described and/or other
problems not discussed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] These and other features of this disclosure will be more
readily understood from the following detailed description of the
various aspects of the disclosure taken in conjunction with the
accompanying drawings that depict various embodiments of the
disclosure, in which:
[0012] FIGS. 1-6 show embodiments of a method according to the
disclosure, with FIG. 6 showing embodiments of an integrated
circuit (IC) and related transistors according to the
disclosure.
[0013] It is noted that the drawings of the disclosure are not to
scale. The drawings are intended to depict only typical aspects of
the disclosure, and therefore should not be considered as limiting
the scope of the disclosure. In the drawings, like numbering
represents like elements between the drawings.
DETAILED DESCRIPTION
[0014] Referring to the drawings, embodiments of a method according
to the disclosure are shown in FIGS. 1-6. FIG. 1 shows providing an
implanted substrate 120 including an n-type metal oxide
semiconductor (NMOS) region 116 and a p-type metal oxide
semiconductor (PMOS) region 118. In particular, NMOS region 116 and
PMOS region 118 may include a doped N-well 122 and doped P-well
124, respectively, separated by an isolation region 126, e.g., a
shallow trench isolation (STI) of silicon oxide. N-type and p-type
dopants may be any appropriate dopants now known or later
developed. Implanted substrate 120 may include but is not limited
to silicon, germanium, silicon germanium, silicon carbide, and
those consisting essentially of one or more III-V compound
semiconductors having a composition defined by the formula
Al.sub.X1Ga.sub.X2In.sub.X3As.sub.Y1P.sub.Y2N.sub.Y3Sb.sub.Y4,
where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative
proportions, each greater than or equal to zero and
X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity).
Other suitable substrates include II-VI compound semiconductors
having a composition Zn.sub.A1Cd.sub.A2Se.sub.B1Te.sub.B2, where
A1, A2, B1, and B2 are relative proportions each greater than or
equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity).
Furthermore, a portion or entire semiconductor substrate 120 may be
strained. Implanted substrate 120 may be formed using any now known
or later developed processes, e.g., deposition, masking, ion
implantation, etc.
[0015] FIG. 1 also shows depositing a high dielectric constant
(high-k) dielectric layer 130 over implanted substrate 120. In one
embodiment, high-k dielectric layer 130 may include any dielectric
including oxygen and having dielectric constant greater than that
of the vacuum level (K>1). High-k dielectric 130 may include,
but is not limited to: hafnium oxide (HfO.sub.2), aluminum oxide
(Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), hafnium
silicon oxide (HfSiO.sub.x), hafnium aluminum oxide (HfAlO),
zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium
oxide (Y.sub.2O.sub.3), strontium oxide (SrO) and strontium
titanium oxide (SrTiO). "Depositing," as used herein, may include
any now known or later developed techniques appropriate for the
material to be deposited including but are not limited to, for
example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD),
plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high
density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high
vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD),
metalorganic CVD (MOCVD), sputtering deposition, ion beam
deposition, electron beam deposition, laser assisted deposition,
thermal oxidation, thermal nitridation, spin-on methods, physical
vapor deposition (PVD), atomic layer deposition (ALD), chemical
oxidation, molecular beam epitaxy (MBE), plating, evaporation.
[0016] FIGS. 1-2 show forming of a first metal 140 (e.g., deposited
or grown (FIG. 1)) having a work function commensurate with a first
one of NMOS region 116 and PMOS region 118 over the first one of
NMOS and PMOS regions 116, 118 only. As used herein, "commensurate
with" indicates that the metal is commensurate with a doping of the
region 116, 118 in question, i.e., it's work function enhances
performance of devices built in that particular region. As
illustrated, first metal 140 is formed over PMOS region 118, and
thus first metal 140 would be commensurate with PMOS region 118.
For example, first metal 140 would have a work function that would
cause a threshold voltage to a band edge for a PFET 200 (FIG. 6) to
be formed over PMOS region 118. First metal 140 may be deposited,
as shown in FIG. 1, and then patterned and etched off of a second
one of NMOS and PMOS regions 116, 118, as shown in FIG. 2, leaving
high-k dielectric layer 130 exposed over the second one of NMOS and
PMOS regions 116, 118. In this case, high-k dielectric layer 130 of
NMOS region 116 is exposed. This is in contrast to conventional
techniques that would remove high-k dielectric layer 130 from NMOS
region 116. First metal 140 may be removed using any now known or
later developed technique, e.g., depositing a photoresist,
patterning and etching the photoresist and etching first metal 140
using the photoresist. It is emphasized that first metal 140 may be
for either NMOS region 116 or PMOS region 118, i.e., the order of
which region is generated first may switch without departing from
the scope of the disclosure. Where first metal 140 is over PMOS
region 118, first metal 140 may include, but is not limited to:
titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN),
tantalum carbide (TaC), titanium carbide (TiC), titanium
oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon
nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium
silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
[0017] FIG. 3 shows depositing a second metal 150 having a work
function commensurate with the second one of NMOS and PMOS regions
116, 118 over implanted substrate 120. In the illustrative case,
the second one is the NMOS region 116. Where second metal 150 is
over NMOS region 116, second metal 150 may include, but is not
limited to: titanium nitride (TiN}, ruthenium (Ru), tantalum
nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC),
titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum
silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi),
iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum
(Al). It is understood that the metal over NMOS may be also
selected from this list when it is the first metal deposited,
rather than the second as illustrated. Similarly, it is understood
that the metal over PMOS may be selected from the above-described
list therefor when it is the second metal deposited, rather than
the first as illustrated.
[0018] FIG. 4 shows an optional process that includes depositing a
capping layer 160 over implanted substrate 120 prior to depositing
second metal 150, then depositing second metal 150. Capping layer
160 can take a variety of forms. In one embodiment, capping layer
160 includes but is not limited to a dielectric such as: lanthanum
oxide (La.sub.2O.sub.3), dysprosium oxide (DyO), yttrium oxide
(Y.sub.2O.sub.3), barium oxide (BaO), strontium oxide (SrO),
scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO),
neodymium (NdO), gadolinium oxide (GdO), erbium oxide (ErO). In
this case, capping layer 160 may provide extra threshold voltage
(Vt) shift--here NFET capping layer. In another embodiment, capping
layer 160 may include a metal such as, but not limited to:
lanthanum (La), dysprosium (Dy), yttrium (Y), strontium (Sr),
scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr),
neodymium (Nd), gadolinium (Gd), erbium (Er). In another
embodiment, as shown in FIG. 5, capping layer 160 includes a metal,
typically a rare earth metal, that reacts with high-k dielectric
layer 130 over the first one of the NMOS and PMOS regions (i.e.,
NMOS region 116 as illustrated) to form a dielectric 180, but
remains metallic 190 over the second one of the NMOS and PMOS
regions 116, 118 (i.e., PMOS region 116 as illustrated). The rare
earth metal may include a multilayer composite of metals (known as
a bilayer). In terms of dielectric 180, rare earth metal reacts
with the oxygen in high-k dielectric layer 130 to form an oxide
that is formed from the rare earth metal. Where rare earth metal
190 remains metallic it is sealed between first metal 140 and
second metal 150, and thus is sealed against reaction with the
atmosphere. Capping layer 160 may include a rare earth metal such
as, but not limited to: ytterbium (Yb), dysprosium (Dy), lanthanum
(La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba),
cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and
erbium (Er).
[0019] FIG. 5 shows depositing a polysilicon 170 over implanted
substrate 120 based on the FIG. 4 embodiment. FIG. 6 shows
patterning to form a first gate stack 194 over NMOS region 116 and
a second gate stack 196 over PMOS region 118 on implanted substrate
120. As understood, each gate stack 194, 196 eventually becomes a
gate electrode 194, 196 for an n-type field effect transistor
(NFET) 202 and a p-type field effect transistor (PFET) 200,
respectively. An integrated circuit 210 including PFET 200 and NFET
202 thus includes a first type transistor (i.e., PFET 200 as
illustrated) having gate electrode 194 including a first metal 140,
a second metal 150 having a work function commensurate with the
second type transistor (i.e., NFET 202 as illustrated) and a first
dielectric layer 130 including oxygen. IC 210 also includes a
second type transistor (i.e., NFET 202 as illustrated) separated
from first type transistor (PFET) 200 by an isolation region 126.
The second type transistor (NFET) 202 includes gate electrode 196
including second metal 150 and first dielectric layer 130. Gate
electrode 194 of first type transistor (PFET) 200 also includes a
rare earth metal 190 between first metal 140 and second metal 150,
and gate electrode 196 of second type transistor (NFET) 202
includes a second dielectric layer 180 made of an oxide of the rare
earth metal. First dielectric layer 130 is under first metal 140 in
PFET 200 so as to act as a gate dielectric for gate electrode 194.
Similarly, second dielectric layer 180 contacts first dielectric
layer 130 in first type transistor (NFET) 202, and thus
collectively act as a gate dielectric for gate electrode 196. Each
gate electrode 194, 196 further includes a polysilicon portion 170.
In one embodiment, second metal 150 in first type transistor (PFET)
200 and second type transistor (NFET) 202 are electrically coupled,
which is impossible with conventional processing due to the gap
that forms between devices during the patterning and removal
process.
[0020] As also shown in FIG. 6, a transistor 200 includes gate
stack 194 including high-k dielectric layer 130 over substrate 120,
first metal 140 having a work function commensurate with a well 124
in the substrate, capping layer 160 including a rare earth metal
190 over first metal 140, a second metal 150 over capping layer
160, and a polysilicon 170 over second metal 150. In this case,
second metal 150 has a work function incompatible with well 124
(p-well) in substrate 120, i.e., it is harmful to threshold voltage
(Vt) if allowed to impact operation. Transistor (NFET) 202 includes
a gate stack 196 including high-k dielectric layer 130 over
substrate 120, capping layer 160 including an oxide 180 of a rare
earth metal over high-k dielectric layer 130, a metal 150 over the
oxide of the rare earth metal, the metal having a work function
commensurate with a well 122 (n-well) in substrate 120, and a
polysilicon 170 over the metal 150.
[0021] The above-described methods, IC and transistors incorporate
a capping layer in the form of an rare earth metal to intermix with
high-k dielectric layer 130 (and not the metal 150) to shift the
work function of the NMOS region 116 to band-edge, but when
interposed in the metals 140, 150 they do not cause a threshold
voltage shift in the PMOS region 118. In addition, the methods
allow for meeting of ground rules, and do not require removal of
both NMOS and PMOS region metals form the opposing region. The
methods also allow for butted junctions with the NFET 202 always
self-aligned to PFET 200 since only one metal layer is removed over
isolation region 126, i.e., second metal 150.
[0022] The method as described above is used in the fabrication of
integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0023] The foregoing description of various aspects of the
disclosure has been presented for purposes of illustration and
description. It is not intended to be exhaustive or to limit the
disclosure to the precise form disclosed, and obviously, many
modifications and variations are possible. Such modifications and
variations that may be apparent to a person skilled in the art are
intended to be included within the scope of the disclosure as
defined by the accompanying claims.
* * * * *