U.S. patent application number 12/236401 was filed with the patent office on 2009-03-26 for wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Hung-Mo Yang.
Application Number | 20090081566 12/236401 |
Document ID | / |
Family ID | 37854243 |
Filed Date | 2009-03-26 |
United States Patent
Application |
20090081566 |
Kind Code |
A1 |
Yang; Hung-Mo |
March 26, 2009 |
WAFER HAVING SCRIBE LANES SUITABLE FOR SAWING PROCESS, RETICLE USED
IN MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING THE SAME
Abstract
A wafer that is less susceptible to chipping or peeling during a
sawing process is disclosed. The wafer includes a plurality of
chips, scribe lanes formed between the plurality of chips, and a
passivation film, which is formed on the plurality of chips and the
scribe lanes and has a plurality of perforations, e.g. slit
patterns engraved on each scribe lane. A photolithography reticle
and method of manufacturing the wafer are also provided.
Inventors: |
Yang; Hung-Mo; (Gyeonggi-do,
KR) |
Correspondence
Address: |
MARGER JOHNSON & MCCOLLOM, P.C.
210 SW MORRISON STREET, SUITE 400
PORTLAND
OR
97204
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
Gyeonggi-do
KR
|
Family ID: |
37854243 |
Appl. No.: |
12/236401 |
Filed: |
September 23, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11530568 |
Sep 11, 2006 |
7436047 |
|
|
12236401 |
|
|
|
|
Current U.S.
Class: |
430/5 ;
257/E21.599; 438/462 |
Current CPC
Class: |
H01L 21/78 20130101;
G03F 1/44 20130101; H01L 23/544 20130101; H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 23/562 20130101; H01L 2223/54453
20130101; H01L 2924/00 20130101; H01L 23/5256 20130101 |
Class at
Publication: |
430/5 ; 438/462;
257/E21.599 |
International
Class: |
G03F 1/00 20060101
G03F001/00; H01L 21/00 20060101 H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 13, 2005 |
KR |
2005-0085294 |
Claims
1. A reticle comprising: a substrate including a plurality of chip
areas and scribe lane areas, the substrate being transparent
against exposure light; and a light-shielding pattern formed on the
substrate and having a plurality of transparent portions in the
scribe lane areas, the transparent portions corresponding to a
plurality of slit patterns to be engraved on a passivation film
formed on a wafer.
2. The reticle of claim 1, wherein the ends of the plurality of
transparent portions corresponding to the plurality of slit
patterns are not aligned with one another.
3. The reticle of claim 1, wherein the plurality of transparent
portions corresponding to the plurality of slit patterns are
alternately arranged so that end portions thereof are staggered
along the length of the scribe lane.
4. The reticle of claim 1, wherein the scribe lane areas include
areas not having monitoring patterns formed thereon and areas
having monitoring patterns formed thereon, and the light-shielding
pattern shields light in the areas having monitoring patterns
formed thereon.
5. The reticle of claim 1, wherein the light-shielding pattern in
the chip areas includes transparent portions corresponding to fuse
openings.
6. The reticle of claim 5, wherein the light-shielding pattern in
the chip areas further includes transparent portions corresponding
to pad openings.
7. The reticle of claim 1, wherein the width of an opening
corresponding to a slit pattern at the central portion of each
scribe lane area is larger than that at other portions of each
scribe lane area.
8. The reticle of claim 1, wherein the width of openings
corresponding to slit patterns near a central area of each scribe
lane are gradually larger than the width of an opening
corresponding to a slit pattern at an edge area of each scribe
lane.
9. A method of manufacturing a wafer, the method comprising:
forming a passivation film on a wafer, which includes scribe lanes
formed between a plurality of chips; and engraving a plurality of
slit patterns on the passivation film, the slit patterns being
formed on the scribe lanes.
10. The method of claim 9, wherein the passivation film on the
scribe lanes includes an enclosure pattern provided with bridges
that connect together a plurality of passivation line patterns.
11. The method of claim 9, wherein the ends of the plurality of
slit patterns are not aligned with one another.
12. The method of claim 9, wherein the plurality of slit patterns
are alternately arranged.
13. The method of claim 9, wherein each of the scribe lanes
includes first areas not having monitoring patterns formed thereon
and second areas having monitoring patterns formed thereon, and the
first areas having monitoring patterns formed thereon do not
include the engraved slit patterns and are covered with the
passivation film.
14. The method of claim 9, wherein engraving the plurality of slit
patterns includes simultaneously forming fuse openings on the
passivation film.
15. The method of claim 14, wherein engraving the plurality of slit
patterns includes simultaneously forming pad openings on the
passivation film.
16. The method of claim 9, wherein engraving the plurality of slit
patterns includes engraving the slit patterns such that the width
of a slit pattern at the central portion of each scribe lane is
larger than the width of a slit pattern at other portions of each
scribe lane.
17. A method of manufacturing a wafer comprising: forming a
passivation film on the wafer, the wafer including a scribe lane
formed between adjacent chips thereon; selectively perforating the
passivation film in a region overlying the scribe lane.
18. The method of claim 17, wherein the perforating of the
passivation film forms a perforation that extends substantially
entirely over the scribe lane.
19. The method of claim 17 wherein the perforating is performed by
engraving a plurality of slit patterns on the passivation film, the
slit patterns extending lengthwise over the scribe lane.
20. The method of claim 19, wherein the slit patterns are
substantially coextensive in two dimensions with the scribe lanes.
Description
CROSS-REFERENCE TO RELATED PATENT APPLICATION
[0001] This application is a Divisional of U.S. Ser. No.
11/530,568, filed on Sep. 11, 2006, now pending, which claims
priority from Korean Patent Application No. 10-2005-0085294 filed
on Sep. 13, 2005, all of which are hereby incorporated by reference
in their entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] The disclosure relates to a wafer having scribe lanes
suitable for a sawing process, a reticle used in manufacturing the
wafer, and a method of manufacturing the wafer.
[0004] 2. Description of the Related Art
[0005] Generally, after a plurality of chips are formed on a wafer,
a sawing process is performed. In the sawing process, a diamond
blade rotating at high speed cuts the wafer along scribe lanes to
separate the chips from one another.
[0006] However, in the conventional sawing process, chipping occurs
in each chip due to mechanical stress caused by the blade, and
worse, cracks occur in a passivation film and an interlayer
insulating film of the chip, thereby causing defects in the
chip.
[0007] On the other hand, when the passivation film is completely
opened along the scribe lanes in order to prevent the mechanical
stress from being transmitted through a hard passivation film,
peeling occurs. The peeling is a defect where a part of a metal
layer forming alignment marks or a part of a metal layer of a pad
window connected to a test element group is peeled off from the
metal layer in the sawing process. In particular, the undesirable
peeling may cause short circuiting of wires in a multi-chip
package.
SUMMARY
[0008] According to one embodiment, a wafer includes a plurality of
chips, scribe lanes formed between the plurality of chips, and a
passivation film, which is formed on the plurality of chips and the
scribe lanes and has a plurality of slit patterns engraved on each
scribe lane.
[0009] According to another embodiment, a reticle includes a
substrate having a plurality of chip areas and scribe lane areas,
the substrate being transparent against exposure light, and a
light-shielding pattern formed on the transparent substrate and
having a plurality of transparent portions in the scribe lane
areas. The transparent portions correspond to a plurality of slit
patterns to be engraved on a passivation film formed on a
wafer.
[0010] According to still another embodiment, a method of
manufacturing a wafer includes forming a passivation film on a
wafer, which includes scribe lanes formed between a plurality of
chips, and engraving a plurality of slit patterns on the
passivation film, which is formed on the scribe lanes.
[0011] Providing a plurality of openings such as slits in the
scribe lane areas minimizes chipping and peeling during a sawing
process as compared to the conventional process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The above and other features and advantages of the invention
will become more apparent by describing in detail exemplary
embodiments thereof with reference to the attached drawings in
which:
[0013] FIG. 1 is a perspective view of a wafer in which
manufacturing processes and an electrical die sorting process have
been completed;
[0014] FIG. 2 is an enlarged plan view of a part of an area 60
shown in FIG. 1;
[0015] FIG. 3A is an enlarged plan view of an area A shown in FIG.
2, and FIG. 3B is an enlarged plan view of an area B shown in FIG.
2;
[0016] FIG. 4 is an enlarged perspective view showing a part of the
area A shown in FIG. 2;
[0017] FIG. 5 is a cross-sectional view taken along line V-V' shown
in FIG. 2;
[0018] FIG. 6 is a plan view showing a scribe lane of a wafer
according to some embodiments;
[0019] FIG. 7 is a plan view showing a scribe lane of a wafer
according to other embodiments;
[0020] FIGS. 8 to 12 are views illustrating exemplary methods of
manufacturing wafers according to some embodiments;
[0021] FIG. 13A is an image of a sample wafer according to some
embodiments; and
[0022] FIG. 13B is an image of a comparative sample wafer.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0023] Advantages and features of the invention and methods of
accomplishing the same may be understood more readily by reference
to the following detailed description of preferred embodiments and
the accompanying drawings. The invention may, however, be embodied
in many different forms and should not be construed as being
limited to the embodiments set forth herein. Rather, these
embodiments are provided so that this disclosure will be thorough
and complete and will convey the concept of the invention to those
skilled in the art. Accordingly, processes, element structures, and
technologies known in some embodiments are not specifically
described to avoid ambiguity. Like reference numerals refer to like
elements throughout the specification.
[0024] Terms used in the present specification are used to describe
embodiments, and do not limit the invention. Terms `comprise`
and/or `comprising` used in the present specification are used so
as not to exclude that described components, processes, operations,
and/or elements are present in or added to one or more other
components, processes, operations, and/or elements. A term `and/or`
is used to include each of described items and one or more
combinations of the items.
[0025] A wafer, in which chipping and peeling does not occur in a
sawing process, having scribe lanes suitable for the sawing process
will be described with reference to some embodiments. According to
the embodiments, a passivation film on the scribe lanes includes a
plurality of engraved slit patterns, and effectively prevents
mechanical stress from being transmitted in the sawing process.
Therefore, chipping does not occur. In addition, since slit
patterns are not formed in areas having monitoring patterns such as
alignment marks formed thereon, the peeling does not occur.
[0026] Hereinafter, a wafer according to some embodiments will be
described in detail with reference to FIGS. 1 to 5.
[0027] FIG. 1 is a perspective view of a wafer 10 in which
manufacturing processes and an EDS (electrical die sorting) process
have been completed. The wafer 10 includes a plurality of chips 20
and scribe lanes 30. Each of the chips has a large scale integrated
circuit formed thereon, and the scribe lanes are used to separate
the plurality of chips 20 from one another by means of, for
example, a diamond blade 40. The plurality of chips 20 are formed
by several exposure processes performed in every shot unit 50.
[0028] FIG. 2 is an enlarged partial plan view showing a portion of
an area 60 shown in FIG. 1, FIG. 3A is an enlarged plan view of an
area A shown in FIG. 2, FIG. 3B is an enlarged plan view of an area
B shown in FIG. 2, FIG. 4 is an enlarged perspective view showing a
part of the area A shown in FIG. 2, and FIG. 5 is a cross-sectional
view taken along line V-V' shown in FIG. 2.
[0029] First, referring to FIGS. 2 to 4, the wafer 10 includes the
chips 20 and the scribe lanes 30. Each of the scribe lanes 30
includes areas A not having monitoring patterns formed thereon, and
areas B having a plurality of monitoring patterns formed thereon.
Each of the monitoring patterns includes a measuring pattern used
to discriminate whether a formed film actually has a required
thickness and size, an alignment pattern used to exactly align a
stepper with the wafer in a photo process, and a TEG (test element
group) used to measure electrical characteristics of the formed
element. A local opening is formed to include a plurality of
perforations that in accordance with one embodiment of the
invention are substantially coextensive in two dimensions with, and
overlay (are congruent with) the scribe lane. In accordance with
the illustrated embodiment of the invention, the plurality of
perforations take the form of plural elongated parallel slit
patterns 132 engraved in a passivation film 129 formed in each
scribe lane area A, which does not have monitoring patterns formed
thereon. Specifically, the local opening includes a box-shaped
enclosure pattern in which each of a plurality of passivation line
patterns or strips 134 is connected to an adjacent one of the
plurality of passivation line patterns 134 by a plurality of webs
or bridges 133. Since adjacent ones of the plurality of passivation
line patterns 134 are connected to one another, it is possible to
prevent the passivation line patterns or strips 134 from falling
down and to effectively prevent the passivation line patterns 134
from being lifted. Thus, a contiguous but perforated passivation
region is formed coextensive with the scribe lane to absorb stress
such as vibration and shock during wafer scribing and to prevent
peeling.
[0030] The slit patterns 132 can be arranged at a predetermined
pitch. The width W, the length L, and the space S of each slit
pattern 132 are set in consideration of the width of each scribe
lane 30 and falling down of the passivation line patterns 134.
Furthermore, the slit patterns 132 are arranged from the edge of
the chip 20 at constant intervals. When the width of each scribe
lane 30 is not an integer multiple of the width W and space S of
the slit pattern 132, the width of a central slit pattern 136 may
be set larger than that of each of the other slit patterns 132 in
order to more effectively prevent the chipping. In this case, the
central slit pattern 136 is formed in a central area of each scribe
lane 30 on which the diamond blade 40 passes. Although not shown in
the drawings, the slit patterns may be configured such that the
width of each slit pattern near the central area of each scribe
lane is gradually larger than that of each slit pattern near the
outside areas thereof.
[0031] Meanwhile, when the webs or bridges 133 are not aligned with
one another (but instead are offset from one another, i.e.
dispersed, along the length of the passivation layer region
overlaying the scribe lanes, as shown in FIGS. 3A and 7), it is
possible to even further reduce the stress transmitted to the chips
20. Accordingly, it may be preferable that the ends of the engraved
slit patterns 132 adjacent to each other are not aligned with each
other. For instance, the ends of the slit patterns 132 may be
staggered. Those of skill in the art will appreciate, however, that
any perforation pattern in the passivation layer region overlying
the scribe lane is effective in absorbing the stress imparted by
scribing, and thus is contemplated as being within the spirit and
scope of the invention.
[0032] According to some embodiments, the stress occurring in the
sawing process using the diamond blade 40 is dispersed or
distributed, and the plurality of passivation line patterns 134
serves as barriers against the stress to be laterally transmitted.
Accordingly, it is possible for less chipping to occur.
Furthermore, the slit patterns are not formed in each scribe lane
area B having the monitoring pattern formed thereon, and the
passivation film 129 remains in each scribe lane area B. Therefore,
the peeling does not occur on the monitoring patterns in the sawing
process.
[0033] Hereinafter, a cross-sectional structure of the wafer 10
according to some embodiments will be described in detail with
reference to FIG. 5.
[0034] Each of the chips 20 includes a minute electronic element
area (not shown), a fuse area, and a pad area. The fuse area has
conductive lines 112a and 112b, which are formed by extending bit
lines of the microelectronic device area on a substrate 100 having
minute electronic elements such as transistors (not shown) thereon.
The conductive line 112a provided below a fuse pattern 122a may be
a buffer pattern film for absorbing an impact occurring when the
fuse pattern 122a is cut, for example, by a laser. The conductive
lines 112b may be electrically connected to the fuse pattern 122a
through vias 120. The conductive line 116a provided below the fuse
pattern 122a also serves as a buffer pattern film, and conductive
lines 116b may be electrically connected to a guard ring pattern
128a thorough vias 126. The conductive lines 116a and 116b may be
composed of a conductive layer that forms upper electrodes of a
capacitor in case of a DRAM device. However, the conductive lines
116a and 116b are not limited to this, and may be omitted.
Furthermore, although the fuse pattern 122a is composed of a single
metal layer in FIG. 5, the fuse pattern 122a may be composed of a
conductive layer that forms bit lines.
[0035] The pad area includes a pad electrode, i.e., a bond pad,
which has a first metal pattern 122b composed of a single metal
layer similar to the fuse pattern 122a and a second metal pattern
128b in contact with the first metal pattern 122b.
[0036] If the engraved slit patterns 132 defining the passivation
line patterns 134 constituting the local opening 130 of the scribe
lane, and a fuse opening 150 are formed at the same time, the
process of manufacturing the wafer can be simplified. Accordingly,
the depth of each engraved slit pattern 132 may be substantially
equal to that of the fuse opening 150. For example, the depth of
each slit pattern 132 may be in the range of 2.2 to 2.7 .mu.m in
the case of a DRAM device in which the fuse pattern 122a is
composed of a single metal layer as shown in FIG. 5. In addition,
although not shown in FIG. 5, the depth of each slit pattern 132
may be in the range of 4 to 4.5 .mu.m in case of a DRAM device in
which the fuse pattern is composed of a conductive layer that forms
bit lines. However, the depth of each slit pattern 132 may be
variously modified depending on what composes the fuse pattern in
accordance with the kind of the microelectronic devices.
[0037] Furthermore, the fuse opening 150 of the chip area, the
local opening 130 of the scribe lane, and a pad opening 140 may be
simultaneously formed.
[0038] Reference numerals 114 and 118 indicate interlayer
insulating films, reference numeral 124 indicates an intermetallic
insulating film, and reference numeral 129 indicates a passivation
film.
[0039] FIGS. 6 and 7 are plan views of scribe lanes of wafers
according to some embodiments.
[0040] As shown in FIG. 6, slit patterns 132 may be arranged so
that the ends thereof are aligned with one another. Alternatively,
as shown in FIG. 7, the slit patterns 132 may be alternately
arranged.
[0041] When the slit patterns 132 are alternately arranged as shown
in FIG. 7, it is possible to more effectively prevent mechanical
stress from being transmitted through bridges 133.
[0042] Hereinafter, exemplary methods of manufacturing wafers
according to some embodiments, and a reticle used in the exemplary
methods thereof will be described with reference to FIGS. 8 to 12.
Hereinafter, processes related to processes known to those skilled
in the art are schematically described in the following description
of the methods in order to avoid ambiguity.
[0043] Referring to FIG. 8, a wafer 10, in which all of the
processes until the process of manufacturing the passivation film
129 have been completed, is prepared. Specifically, the
microelectronic devices are formed in a microelectronic device area
(not shown) of the chip, and the fuse pattern 122a and guard ring
pattern 128a are formed in the fuse area. Further, the pad
electrode, which includes the first metal pattern 122b and the
second metal pattern 128b, is formed in the pad area, and the
monitoring patterns (not shown) are formed in the scribe lane.
Then, the passivation film 129 is ultimately formed. The process of
manufacturing each of the patterns forming the areas may be
variously modified in accordance with processes known to those
skilled in the art of a semiconductor device. Accordingly, the
process of manufacturing each of the patterns is schematically
described in order to avoid ambiguity.
[0044] After that, the slit patterns 132 are engraved on the scribe
lane. The engraving of the slit patterns will be described with
reference to FIGS. 9 to 12.
[0045] FIG. 9 is a plan view of a reticle used to form the slit
patterns 132, and FIG. 10 is a cross-sectional view taken along
lines A-A' and B-B' of FIG. 9.
[0046] Referring to FIGS. 9 and 10, the reticle 200 includes a
plurality of chip areas 220 and scribe lane areas 230. Each of the
chip areas 220 has a chip pattern formed thereon, and each of the
scribe lane areas 230 has a scribe lane pattern formed thereon.
Although a reticle used to expose 3.times.3 chips by one shot
exposure is shown in FIG. 9, the arrangement of the chips may be
modified in the form of 2.times.2, 2.times.3, or the like.
[0047] A light-shielding pattern 203 is formed on a reticle A-A',
which includes areas not having monitoring patterns of the scribe
lane areas 230 on a substrate 201, of the reticle 200. The
substrate 201 is transparent against exposure light. The
light-shielding pattern 203 defines transparent portions 260
corresponding to the slit patterns 132, another transparent portion
250 corresponding to the fuse opening 150, and still another
transparent portion 240 corresponding to the pad opening 140. In
addition, the light-shielding pattern 203 is also formed on a
reticle B-B', which includes areas having monitoring patterns
thereon. The light-shielding pattern 203 defines a transparent
portion 250 corresponding to the fuse opening 150 and another
transparent portion 240 corresponding to the pad opening 140. That
is, the light-shielding pattern 203 shields the exposure light in
the areas having monitoring patterns.
[0048] The transparent portions 260 corresponding to the slit
patterns 132 have substantially the same structure as the slit
patterns 132 shown in FIGS. 3A, 6, and 7.
[0049] FIGS. 9 and 10 illustrate a reticle to be applied to a
positive resist. On the other hand, it is apparent that a reticle
to be applied to a negative resist includes the light-shielding
pattern formed in the transparent portion illustrated in FIGS. 9
and 10, and areas having the light-shielding pattern thereon
changed into the transparent portion. Accordingly, the reticle to
be applied to a negative resist is not shown for the sake of
simplicity.
[0050] After a photoresist film 160 is coated on the passivation
film 129 shown in FIG. 8, the wafer 10 is loaded in the stepper in
which the reticle 200 shown in FIGS. 9 and 10 has been loaded.
Then, as shown in FIG. 11, an exposure process is performed.
[0051] The light-shielding pattern 203 formed on the reticle 200 is
transcribed on the wafer 10 by one shot exposure. Subsequently,
while the reticle 200 is transferred, the entire wafer 10 is
exposed.
[0052] Finally, as shown in FIG. 12, the exposed photoresist film
160 is developed to form a photoresist pattern 160a. Then, the
passivation film 129 and the intermetallic insulating film 124 are
partially etched, using the photoresist pattern 160a as an etching
mask, to engrave the slit patterns 132 on the scribe lanes.
[0053] At the same time, the fuse opening 150 having substantially
the same depth as that of each slit pattern 132 is also formed in
the fuse area. In addition, the pad opening 140 is also formed in
the pad area.
[0054] After that, the wafer 10 is sawed along the scribe lanes to
cut apart the wafer into a plurality of semiconductor dies (dicing)
so that each die can be mounted into its own package through
processes known to those skilled in the art, for example, die
attaching and wire bonding. The succeeding processes are
schematically described to avoid ambiguity.
[0055] More detailed descriptions related to some embodiments are
described with reference to the following specific example. Since
descriptions not described in this specification can be
sufficiently analogized by those skilled in the art, descriptions
not described in this specification will be omitted.
[0056] Several wafers, in which the width of each scribe lane is
about 10 .mu.m and a plurality of DRAM chips are formed, have been
prepared. A passivation film, which includes a plurality of holes,
e.g., slit patterns having a width of 3 .mu.m, a length of 300
.mu.m, and each space of 3 .mu.m in accordance with an embodiment,
is formed on the scribe lanes of a sample wafer of the wafers.
Meanwhile, a passivation film is not formed on the scribe lanes of
a comparative sample wafer.
[0057] Subsequently, after the sawing process is performed, whether
or not chipping occurs is observed. FIG. 13A shows the sample wafer
according to the embodiment, and FIG. 13B shows the comparative
sample wafer.
[0058] Referring to FIGS. 13A and 13B, it is understood that
chipping hardly occurs in the sample wafer according to the
embodiment, and occurs very much in the comparative sample
wafer.
[0059] While the invention has been particularly shown and
described with reference to exemplary embodiments thereof, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made therein without departing
from the spirit and scope of the invention as defined by the
following claims. Therefore, it is to be understood that the
above-described embodiments have been provided only in a
descriptive sense and will not be construed as placing any
limitation on the scope of the invention.
[0060] According to some embodiments of the invention, since the
passivation film including slit patterns, which are engraved on the
scribe lane, is provided, the mechanical stress occurring during
the sawing process using the blade can be easily dispersed.
Further, since passivation line patterns defined by the slit
patterns serve as barriers for the stress, it is possible to reduce
chipping as much as possible. Furthermore, since the slit patterns
are not formed on the passivation film in the area having the
monitoring patterns formed thereon, it is possible to effectively
prevent peeling from occurring on the monitoring patterns.
* * * * *